Vhdl & Digital Circuit Design

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M.KavyaRoll no 09


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About integrated circuits

Moores law

Introduction to vlsi

Brief introduction to vhdl

conclusion


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Integrated Circuits (IC) Meaning That All TheComponents In This Circuits Are Fabricated OnThe Same Chip.

ICs Have Become A Vital Part Of Modern

Electronics Circuits Design. They Are Used In The Computer Industry,

Automobile Industry, Home Appliances,Communication And Control Systems.

ICs Are Of Two Basic Types :

1. Digital ICs

2. Linear ICs


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Digital ICs Are Complete Functioning Logic

Network That Equivalents Of Basic Transistor

Logic Circuits.

They Are Used To Form Such Circuits AsGate,coutner,mux, Demux, Register,etc.

Digital Circuits Concerned With Only Two

Levels Of Voltage High And Low.

Digital Ckts Are Easy To Design And ProduceIn Large Quantities As Low Cost Devices.


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Linear ICs Are Equivalent Of Discrete

Transistor Networks Such As

Amplifier,Filter,Frequency Multipliers And

Modulators. It Requires Extra Components for Satisfactory

Operations.

In Linear Ckts The Output Of Electrical

Signals Vary In Proportion To The InputSignals Applied.

Linear Ckts Are Also Referred To As Analog

Circuits.


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Moore Who Is Known As Father Of Printer.

In 1970 Moore Gave The Law Which Is Known

As Moores Law.

Its State That After Each 18\24 Months TheNumber Of Components Is Doubled In IC's .

For Example Intel Processor P4 After Two

Years Later Comes Core 2 Dual ,But Processor

Dual Core Comes In Just Sixth Months LaterSo The Average Is 18 Months.


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PROCESSORYEAR OFINTRODUCTION

NUMBER OFTRANSISTORS

INITIAL CLOCKSPEED

4004 1971 2300 108KHz8008 1972 3500 200KHz8080 1974 6000 2MHz

8085 1976 6500 5MHz8086 1978 29000 5MHz8088 1979 29000 5MHz80286 1982 134000 8MHz80386 1985 275000 16MHz80486 1989 1.2M 25MHzPENTIUM 1993 3.1M 150MHzPENTIUM II 1997 8.8M 233MHzPENTIUM III 1999 9.5M 650MHzPENTIUM 4 2000 42M 1.4GHz


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TECHNOLOGY NO. OF TRANSISTERPER CHIP

YEAR

INVENTON OFTRANSISTOR

1 1947

DISCREATECOMPONENTS

1 1950

SMALL SCALEINTEGRATION 10 1961

MEDIUM SCALEINTEGRATION

100-1000 1966

LARGE SCALEINTEGRATION

1000-20,000 1971

VERY LARGE SCALEINTEGRATION

20,000-1,00,000 1980

ULTRA LARGE SCALEINTEGRATION

1,00,000-10,00,000 1990

GIANT SCALEINTEGRATION >10,00,000 2000


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VLSI Is A Process Of Integration Of Millions Of

Transistor In A Single Chip .Vlsi Design Involves

All Aspects Of Creating An IC's.

Vlsi Design Process Is Classified Into Two

Categories . Front End And Back End .

In Front End Vlsi Design Process A Design

Engineer Performs All Aspects Of Design Before

Handling The Design.

In Back End Vlsi Design Process Tasks Performed

By Design Engineers Are-

(A) MASK GENERATION (D)testing

(B)wafer PROCESSING (E)delivery OF SAMPLES

C packaging F final MASS PRODUCTION


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Vhdl Is One Of The Most Accepted And Widely

Used Language For Describing Digital System.

Vhdl Has Been Approved By Ieee As A

Standard Language For Designing Hardware.

Vhdl Is A Large And Verbose Language With

Many Complex Constructs And It Is Initially

Difficult To Understand.

However It Is Possible To Quickly UnderstandA Sub Set Of Vhdl Which Is Both Simple And

Easy To Use.

Vhdl Is Abbreviation For

Vhsic Hardware Description Language.


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Sequential Language

Concurrent Language

Net- List Language

Timing Specifications

Waveform Generation Language


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(A) Labour

(B) Cost

(C) Material

(D) TIME


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SIMULATEDWAVEFORMS

SIMULATION

DESIGN IDEA

SYNTHESIZER

CIRCUIT GENERATED

CIRCUITED IMPLEMENTED

VHDL MODLE


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ARCHITECTURE

LIBRARY/PACKAGE

ENTITY


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(A) ENTITY DECLARATION

(B) ARCHITECTURE BODY

(C) CONFIGURATION DECLARATION

(D) PACKAGE DECLARATION (E) PACKAGE BODY


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ENTITY:

AN ENTITY IS THE MOST BASIC BUILDING BLOCK IN A

DESIGN.

A HARDWARE DESCRIPTION OF A DIGITAL SYSTEM IS CALLED

AN ENTITY. AN ENTITY SPECIFIES THE EXTERNAL VIEW AND ONE OR

MORE INTERNAL VIEWS.

ARCHITECTURE BODY:

THE ARCHITECTURE BODY CONTAINS THE INTERNAL

DESCRIPTION OF THE ENTITY.

THE ARCHTECTURE DESCRIBES THE FUNCTIONALITY &

BEHAVIOUR OF THE ENTITY.

AN ARCHITECTURE IS ALWAYS RELATED TO AN ENTITY.


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CONFIGURATION:

IT SPECIFIES THE BINDING OF ONE ARCHITECTURE BODY

FROM THE MANY ARCHITECTURE BODIES.

CONFIGURATION DECLARATION IS USED TO BIND ONE OF

MANY ARCHITECTURE BODIES TO AN ENTITY. IT IS ALSO USED TO BIND COMPONENTS USED IN

STRUCTURAL MODEL TO OTHER ENTITY ARCHITECTURE

PAIR.

AN ENTITY MAY HAVE ANY NUMBER OF DIFFERENT

CONFIGURATION. PACKAGE:

A PACKAGE IS A COLLECTION OF COMMONLY USED DATA

TYPES AND SUB PROGRAMS USED IN A DESIGN.


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PACKAGE DECLARATION:

A PACKAGE DECLARATION ENCAPSULATES A SET OF RELATED

DECLARATIONS SUCH AS DATA TYPES, COMPONENTS, SUB

PROGRAM (PROCEDURE AND FUNCTIONS).

THE DECLARATION INSIDE A PACKAGE CAN BE SHARED BYOTHER DESIGN UNITS BY USING A USE CLAUSE.

PACKAGE BODY:

A PACKAGE BODY CONTAIN THE DEFINITIONS OF

SUBPROGRAMS DECLARED IN A PACKAGE DECLARATION.

NAME OF PACKAGE BODY SHOULD BE SAME AS PACKAGEDECLARATION


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ENTITY DECLARATION :

Entity Declaration Describes How An Entity Is Connected To

Outside World.

It Describes The External View Of The Entity.

Entity Declaration Specifies The Name Of Entity. It Also Specifies The Input And Output Ports Through Which Entity

Communicates With The External World.

SYNTEX OF ENTITY DECLARATION :

ENTITY entity-name IS

PORT (port1: port1-type:

port2: port2-type);

END entity-name;

E tit D l ti F 2 I t A d G t


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Entity Declaration For a 2 Input And Gate.

entity AND2is

port (a, b: in bit ;c : out bit);end AND2;

ENTITY DECLARATION FOR A FULL ADDER


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ENTITY DECLARATION FOR A FULL ADDER.

entity Full Adder is

port (X, Y, Cin: in bit; -- InputsCout, Sum: out bit); -- Outputsend Full Adder;

FullAdder


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ARCHITECTURE :

It Shows The Inside View Or What Are The Functions Operation

Are Done And Which Type Of That .

An Architecture Is Always Related To An Entity & Describes The

Behaviour Of The Entity.

Internal Details Of An Entity Are Specified By An Architecture

Body By Using Any One Of The Following Model:

SYNTEX OF ARCHITECTURE:

ARCHITECTURE arcitecture-name OF entityname IS

.declare some signals here

BEGIN

.put some concurrent statement here

END architecture-name;


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The Behavioral Style Of Modeling Specifies The

Behavioral Of An Entity As A Statements That Are

Executed Sequentially In The Specified Order.

All Statements Which Are Specified Inside A

Process Statement, Do Not Clearly Specifies The

Structure Of The Entity But Merely Its

Functionality.

A Process Statement Is A Concurrent Statement

That Can Appear With In An Architecture Body.


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THE BEHAVIORAL MODEL DESCRIPTION OF AND

GATE .

architecture AND-2-BEHAVIOR of AND-2 is

begin process (A,B)

begin

C


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In The Structure Style Of Modeling An Entity Is

Described In Terms Of Its Components And Their

Interconnections.

A Structure Model Does Not Tell About The

Functionality Of The Entity.

A Structure Description Is Easiest To Be

Synthesized.

The Architecture Body Is Composed Of Two Parts:

The Declaration Part (Before The Keyword Begin)

The Statement Part (After The Keyword Begin).

Half Adder Is Such Type Of Structure

Architecture.


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architecture HALF-ADDER-STRUCTURE of HALF-ADDER is

component AND2

port(IN1,IN2: in bit ; OUT1: out bit);

end component;

component XOR2

port(IN3,IN4: in bit ; OUT2 : out bit);

end component;

begin A1:AND2 port map (A,B, Sum);

X1:XOR2 port map (A,B,Carry);

end HALF-ADDER-STRUTURE;


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In The Dataflow Style Of Modeling An Entity Is Described In

Terms Of Data Flow By Using Concurrent Signal Assignment

Statements. A Dataflow Model Does Not Tell About The Structure Of The

Entity.

DATAFLOW DESCRIPTION OF HALF ADDER.

architecture HALF-ADDER-DATATFLOW of HALF-ADDER is

begin

SUM


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entity AND2 is

port (a, b: in bit ;

c : out bit);

end AND2;

architecture beh of AND2 is

begin c


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OUTPUT WAVE FORM

OUTPUT WAVE FORM


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OUTPUT WAVE FORM

OUTPUT WAVE FORM


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OUTPUT WAVE FORM


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THANK YOU

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