Project report

SUBMITTED BY:- SUDHIR KUMAR

R.NO->7080405656

V.H.D.L.

CONTENTS:-

1)Introduction2)Capabilities3)Hardware Abstraction4)Basic Declaration5)Entity Declaration6)Architecture Body7)Simulation8)Identifiers9)Data Objects & Types10)Operators11)Process Statement 12) Statements 13) Structural Modelling 14) Generic15) Overloading16) Package17) Advance Features18)program examples19)project: floating point arithematic

V.H.D.L.

INTRODUCTION:-

V.H.D.L. is an acronym for VHSIC Hardware Description Language (VHSIC Very High Speed Integrated Circuits) . It is an hardware description language that can be used to model a digital system at many levels of abstraction from the processor level to gate level .The V.H.D.L. language can be regarded as an integrated amalgamation of the following languages-1:-sequential language 2:-concurrent language3:-net-list language4:-timing specifications5:-waveform generation language It allows as to model the system as an interconnection of components. This language not only define the syntax but also defines very clear simulation semantics for each language construct .Therefore,Model written in this language can be verified using a V.H.D.L. simulator .The complete language has sufficient power to capture the descriptions of the most complex chips to a complete electronic system. Capabilities:-

1)This language supports the hierarchy , that is ,a digital system can be modeled as a set of interconnected components each component in turn can be modeled as a set of inter connected components.

2)This language supports flexible design methodology

3)It supports both synchronous and asynchronous timing models.

4)It is an I.E.E.E. and A.N.S.I. standard .model described using this language are portable .

5)It support a wide range of abstraction level ranging from process level to very precise gate level description.

V.H.D.L.

6)Test benches can be written using the same language to test other V.H.D.L. models.

7)Generic and attributes are also useful in describing parameterized design.

8)A model can not describe the functionality of design but also contain the information about the design itself in terms of user define attributes, such as total area and speed.

9)Models written in this language can be easily verified by simulation.

10)The capability of defining new data types provides power to describe and simulate.. a new design techniq.ues at a very high level of abstraction ..

Basic Declaration:- A hardware abstraction of this digital system is called entity . To describe entity V.H.D.L. provide five different type of constructs called design units.1)Entity Declaration 2)Architecture Body 3)Configuration Declaration 4)Package Declaration 5)Package Body>>>Entity declaration:-It describes only the external view of the entity.

>>>Architecture body:-It contains internal description of the entity. eg: set of inter connected components represents the structure of entity .

>>>Configuration declaration :-it is used to create a configuration for an entity. It specifies the binding of one architecture body from the many architecture bodies that may be associated with the entity.

V.H.D.L.

>>>Package declaration:-It encapsulates a set of related declaration such as type declaration ,subtype declaration and subprogram declaration, which can be shared across the two more design units . >>>Package body;-It contains the defination of subprogram declared in package declaration.

Entity declaration:- The entity declaration specifies the name of the entity being modeled and list of set the interface ports ,Ports are signals through which entity communicates with other models internal and external Eg:-for half_ adder is Entity half_ adder is Port(a, b: in bit; sum, Carry :out bit); end entity, The entity has two input port and two output ports.bit is a predefined type of the language it is an enumeration type containing the characters ,literals ‘0’ and ’1’.

Architecture body:-

The internal detail of an entity are specified by an architecture body using any of the following style . 1)set of interconnected components(to represent structure) 2)A set concurrent assignment statements (to represent dataflow) 3)A set of sequential assignment statements (to represent behavior) 4)As any combination of above three.

Difference between behavioral,structural and dataflow :-

1.behavioral and dataflow represent behavior of the system but behavioral style uses sequential statements and dataflow uses

V.H.D.L.

concurrent statements.On the other hand structure tells about structure of the system i.e by defining its interconnected components.2.behavioral style needs truth table as design specificationsdataflow style needs boolean equations as design specifications.And structural style needs logical diagram as design specifications.3.structural style is more close to hardware as it tells us about the components used in the system/device.

Simulation:- A simulation can be performed either one of the following:- 1)An entity declaration and a architecture body pair. 2)A configurationPreceding the actual simulation are two major steps:-

1)Elaboration phase :-The hierarchy of the entity is expanded and linked, components are bound to entity in a library. also storage is allocated for signals variables and constants declared in the design unit.

2) Initialization Phase:-Driving and effective values for all explicitly declared signals are computed implicit signals are assigned values, processes are executed once until they suspend and simulation time is set to 0ns.Simulation commences by advancing time to that of the next event. Values that are scheduled to be assigned to signals at this time are assigned. if the values of a signal changes, and if that signal is present in the sensitivity list of a process, the process is executed until it suspends. Simulation stops when an assertion violation occurs, depending on the implementation of the V.H.D.L. system or when the maximum time as defined by the language is reached.

Identifiers:- There are two kinds of identifiers in V.H.D.L. 1)Basic identifiers 2)Extended identifiers

V.H.D.L.

Basic identifiers:-Its composed of a sequence of one or more characters. A legal character is an upper case letter(A…Z),a lower-case letter (a…z) ,a digit(0…9),or the underscore(_)character. The first character in a basic identifier must be a letter, and the last character may not be an underscore. for eg:- a)DRIVE_BUS b)SET_CK_HIGH c)CONST32_59 d)Selectsignal

Extended identifiers:-It is a sequence of characters written between two backslashes. Any of the allowable character can be used, including character like. ,!,’ ,@ and $.within an extended identifiers, lower-case and upper-case letters are considered to be distinct. for eg:- a)\test\ c)\~q\ b)\-25\ d)\.$*******\

Data objects and type :-

A data objects holds the value of specified type it is created by means of an object declaration .an eg:- Variable count:integer; This result in the creation of a data object called count which can hold integer value Every data object belongs to one of the following four classes1) constant :-An object of constant class can hold a single value .this value is assigned to the constant before simulation starts and the can’t be changed during the course of simulation. Syntax:- Constant rise:time=10ns;

2) variable :-An object of variable class can hold a single value of a given type .however in this case different values can be assigned to the variable at different times using a variable assignment statement .

V.H.D.L.

Syntax:- Variable count:integer:=10;

3) Signal:-An object belonging to the signal class holds a list of values, which include the current value of the signal, and a set of possible future values that are to be appear on the signal . Syntax:- Signal type,vak:std_logic;

4) File:-An object belonging to the file class contains a sequences of values .values can be read or written to the file using read procedure and write procedure resp. Syntax:- File file-names:file-type-name{{open mode}is string_expression};

DATA TYPES:-

>>Every data objects can hold a value that belongs to the set of values th021is set of values is specified by type of Declaration .

>>A type is a name that has associated with set of values and a set of operations integer is a predefined type with set of values being integers in a specified range .

>>Boolean is a another predefined type that as the values false and true and some of its predefined operator are AND,NOT and OR .>>The declaration for the predefined types of the language are contained in a package STANDARD. it can be categorized into the four following major categories :-

1) scaler types : values belonging to this type appear in a sequential order. there are of the following types

a)Enumeration b) Integer c) Floating point d) Physical

V.H.D.L.

>>>Enumeration:-An enumeration type declaration defines a type that has a set of user defined values consisting of identifiers and character literals .eg- type MVL is(‘U’,’0’); MVL is an enumeration type that has set of ordered values ‘U’,’0’.

>>>Integer:-Integer type defines a type whose set of values fall with in a specified range.eg- type INDEX is range 0 to 15; INDEX is a integer type that includes the integer from 0 to 15

>>>Floating Point:-A floating point has a set of values in a given range of real number.eg- Type ITL is range -5.5 to -1.4; ITL is a floating point and its range from -5.5 to -4.4 .

>>>Physical types:-A Physical type contains values that represent measurement of some physical quantity like time, length , voltage or current.eg- type CURRENT is range 0 to 1E9 CURRENT is defined to be a physical type that contains values from 0nA to 10^9nA Operators:- Operators are the token that triggers some computation when applied to an object or an variable in an expression. The operators of following types; a)Logical operator b)Relational operator c)Shift operator d)Adding operator e)Multiplying operator

>>>Logical operator:-The seven logical operators are AND,OR,NAND,NOR,XNOR,XOR and NOT.

V.H.D.L.

>>>Relational operator:-These are =(equal to) , /= (not equal to), <(less than) , > (greater than), >=(greater then equal to) , <= (less than equal to). >>>Shift operator:-These are sll , srl ,sla .sra ,rol ,ror. Each of the operators takes an array of width as the left operand and integer value as the right operand and performs the specified operation. “1001010”sll 2 is “0101000” --filled with BITLEFT, which is’0’. “1001010”srl 3 is “0001001” --filled with ’0’. “1001010”sla 2 is “0101000” --filled with BITRIGHT, which is’0’. “1001010”sra 3 is “1111001” --filled with ‘1’,which is the leftmost bit. “1001010”rol 2 is “0101010” --rotate left.. “1001010”ror 3 is “0101001” --rotate right

>>>Adding operator:-These operator are + , - , &. The operands for the addition ,subtraction must be of the same numeric type with the result being of the same numeric type. >>>Multiplying operator:-These are *, / , mod , rem. 1)The multiplication and division operators are predefined for both operands being of the same integer or floating point type. The ‘rem’ and ‘mod’ operators operate on operands of integer types and the result is also of the same type . 2)The result of a ‘rem’ operation has the sign of its first operand and defined as .. A rem B=A-(A/B)*B The result of mode operator has the sign of second operand and defined as .. A mod B=A-B*n --for some integer Process statement:- The process statement contains sequential statements that describe the functionality of the portion of an entity in sequential terms . Syntax:- {process-label:}process{(sensitivity-list)}{is}

V.H.D.L.

{process-item-declarations} Sequential-statements; endprocess; A set of signals to which the process is sensitive is define by sensitivity list in other words each time an event occurs on any of the signal in the sensitivity list , the sequential statements with in the process are executed in a sequential order .

Statements:- Statements are the set of instructions given to a computer to perform a specific task.There are different types of statements a) Variable assignment statement b) Signal assignment statement c) Wait statement d) If statemente) Case statement f) null statement g) loop statement

>>> Variable assignment statement :-variables can be declared and used inside a process statement .variable is assigned a value using a variable assignment statement that typically has the form . Variable object:=expression; The expression is evaluated when the statement is executed and the computed value is assigned to the variable object instantaneously.

>>>Signal assignment statement:-Signals are assigned values using signal assignment statement the simplest form of signal assignment statement is : Signal-object<=expression; A Signal assignment statement can appear with in a process or outside the process .if it occurs outside the process then it is concurrent statement ,when it occurs inside the process then it is sequential statement.

V.H.D.L.

When a signal statement is executed the value of expression is computed and this value is scheduled to assigned to the signal after the specified delay.

>>>wait statement:-A process may be suspended by means of sensitivity list .It is always suspended after executing the last sequential statement in the process .The wait statement provides an alternative way to suspend the execution of a process. There are three basic forms of wait statement : =>wait on ---sensitivity list =>wait until ---boolean expression =>wait for ---time expressionSome eg;- Wait on A,B,C; Wait until A=B; Wait for 10ns; Wait on CLOCK for 20ns; Wait until Sum>100 for 50ms;The execution of the wait statement causes the enclosing process to suspend and then wait for an event to occur on signal A,B,C.The execution of second statement causes the enclosing process to suspend entil the specified condition true .The third statement when executed the enclosing process suspends for 10ns .The execution of statement fourth causes the enclosing process to suspend and then wait for an event to occur on signal clock for a time out interval of 20nsIn statement fifth the process suspend for a maximum of 50ms until the value of Sum is greater than 100.

>>>If statement:-If statement select the sequence of statement for execution based on the value of conditionIf Boolean-expression thenSequential- statement{elsif Boolean-expression then Sequential-statements}

V.H.D.L.

{else Sequential- statements} End if;The if statement is executed sequentially.

>>>Case statement:-Case statement selects one of the branches for execution based on the value of expression .the expression value must of a discrete type or one dimensional array type:Case expression isWhen choices=>sequential- statementEnd case;

>>>Null statement:-The statement Null is a type of sequential statement that does not cause any action to take place execution continues with the next statement.

>>>Loop statement:-A loop statement is used to iterate through a set of sequential statement :[loop_label:]iteration-scheme loopSequential- statementEnd loop[loop-label];There are three types of iteration scheme 1>>for iteration scheme Syntax:-For n in 0 to 15 loopF=f*n;End loop;The body of for loop is executed n-1 times.2>>While iteration schemeSyntax:- While Boolean-expressionJ:=0;sum:=10; Wh:while j<20 loop Sum:=sum*2; J:=j+3; End loop;

V.H.D.L.

The statement with in the body are executed sequentially and repeated as long as loop condition j<20.If the loop condition becomes false execution continues with the statement following the loop statement.

Structural modeling:-

In the structural style of modeling, an entity is described as a set of interconnected components. Model for the half_ adder as shown below.

Architecture structure of half_ adder isComponent xor2Port (x, y:In bit; Z:out bit);End component;Component and2Port(l, m: in bit; N: out bit);End component;BeginX1:xor2 port map(a,b,sum);A1:and2 port map(a,b,carry);End structure; The name of the architecture body is half-adder .the entity declaration for half_ adder specifies the interface port for this architecture body.>The architecture body is composed of two parts declarative part and the statement part .two components declaration are present in the declarative part of architecture body. The declared components are instantiated part of the architecture body using component instantiated statement x1 and a1 are the component labels for these component .the first component instantiation statement labeled x1 shows that signal a, b are connected to x and y input port of xor2 component while output port z of this component is connected to output port sum of half_ adder entity.>In the second component instantiation statement signal a, b are connected to ports L and m pf and2 component while port n is connected to the carry port of half_ adder.

V.H.D.L.

>Separate entity models would be described for components xor2 and and2 each having its own entity declaration and architecture body.

Generic:-

Generics of an entity are declared along with its ports in the entity declaration .An example of a generic n input and a gate is shown;Entity and_ gate isGeneric(n:natural);Port(a:in bit_ vector(1 to n);Z:out bit);End and_ gate;Architecture generic_ ex of and_ gate isBeginProcess(a)Variable and_ out:bit;BeginAnd_ out:=’1’;For k in 1 to n loopAnd_ out:=and_ out and a(k);Exit when and_ out=’0’;End loop;Z<=and-out;End process;End generic-ex; The size of input port has being modeled as a generic by doing this we have modeled an entire class and_ gate with the variable numbers of inputs using a single behavior description .the and_ gate entity may now be used with a different no. of input ports with different instantiations .The value of generic must be determinable at elaboration time i.e. a value for a generic must be a explicitly specified atleast once.

V.H.D.L.

Overloading :-Function overloading:-It is convenient to have two or more subprograms with the same name .In such a case ,the subprogram name is said to be overloaded .eg;Function count (orange:integer)return integer;Function count(appels:bit)return integer; Both functions are overloaded since they have the same name , count .when a call to either function is made, it is possible to identify the exact function to which the call is made from the type of Actuals passed because they different parameters types.>>A call to an overloaded subprogram is ambiguous, and hence an error ,if it is possible to identify the exact subprogram being called using the following information:

1. Subprogram name2. Number of actual3. types and order of actual. 4. Names of formal parameters5. Result type (for function )

The overloading does not distinguish by subtypes.

Operator overloading:-

Operator overloading one of the most useful feature in the language. A standard operator symbol is made to behave different ently based on the type of its operands, the operator is said to be overloaded.eg:The and operation is defined for arguments of type bit and Boolean and for one dimensional array or bit and Boolean onlyFunction bodies are written to define the behavior of overloaded operators the no. of parameters in such a function must match in cardinality with that of predefined operator.

Package:-

A package provides a convenient mechanism to store and share declarations that are common across many design units. A package contains1.A package declaration

V.H.D.L.

2.A package body

>>>a package declaration:-A package declaration contains a set of declarations that may possibly be shared by many design units. It defines the interface to the package ,that is, it defines items that can be visible to other design units.Syntax:-Package package-name isPackage-item-declaration---subprogram declaration---type declaration---subtype declaration---constant declarationEnd[package][package-name];

>>>Package body:-A package body primarily contains the behavior of the subprograms and the value of the deferred constants declared in a package declaration. It also may contain other declarations, as shown.Package body pakage-name is Package-body-item-declaration---subprogram bodies---complete constant declaration---files and alias declarationEnd [package body] [package-name]; The package name must be as the name of its corresponding package declaration.A package body is not necessary if its associated package declaration does not have any subprogram or deferred constant declaration.

Advance features:- Advance features are some special features in the language that includes 1.Entity statement2.Aliases

V.H.D.L.

>>>Entity statement:- common declarations appear in the entity declarative pert while other common statements used appear in the entity statement part.Entity entity-name is[generic(….);][port(….);][entity-item-declaration][ beginEntity-statements]End[entity][entity-name];Entity statement not assign any value to any signal the following statements are allowed as entity statement1.cocurrent assertion statement2.cocurrent procedure call statement3.process statement

>>>Aliases : -Aliases provides a convenient short hand notations for items that have long names .it also provides a mechanism to reffered to the same name item in different ways depending on context. Data bus can be used wherever dataword(15 downto 8) is needed.reset can be used wherever data word 4 is needed Variable data_word:bit_vector(15 downto 0);Alias data_bus:bit_vector(7 downto 0) is data_word (15 downto 8);Alias status:bit_vector(0 downto 3) is data_word (3 downto 0);

>>>BLOCK STATEMENTS :- the block statement is a representation of design or hierarchy section,used for partitioning architecture into self contained parts.Syntax is:- label: block (expression) Begin (Concurrent statements) End block label; Where label is the name of the block..A block contains a set of concurrent statements .the order of concurrent statements does not matter because all statements are always executing.

V.H.D.L.

There are two main reasons of using blocks:-1. to improve the readability of the specification.2. to disable some signals by using the guard expression.

>>>guarded block:-a Boolean expression associated with a block that controls assignmenys to guarded signals within a block. A guard expression defines an implicit signal GUARD that may be used to control the operation of certain statements within a block. Syntax is :- Some_signal_in_a_block<= guarded expression;

PROGRAMS:-

BCD TO SEVEN SEGMENT DISPLAY

entity bcd _seven is Port ( a : in STD_LOGIC_VECTOR (3 downto 0); y : out STD_LOGIC_VECTOR (6 downto 0));end bcd_seven;architecture Behavioral of bcd_seven is

beginprocess(a)beginif(a="0000") then y<="0000001";elsif(a="0001") then y<="1001111";elsif(a="0010") then y<="0010010";elsif(a="0011") then y<="0000110";elsif(a="0100") then y<="1001100";elsif(a="0101") then y<="0100100";elsif(a="0110") then y<="1100000";elsif(a="0111") then y<="0001111";elsif(a="1000") then y<="0000000";elsif(a="1001") then y<="0000100";

V.H.D.L.

end if;end process;end Behavioral;

SIMULATION

FULL ADDER(Behavioral)entity full_adder is Port ( A : in STD_LOGIC; B : in STD_LOGIC; C : in STD_LOGIC; Sum : out STD_LOGIC; Carry : out STD_LOGIC);end full_adder;

architecture Behavioral of full_adder is

beginprocess(a,b,c)variable temp : std_logic;variable x : std_logic;variable y : std_logic;variable z : std_logic;variable m : std_logic;begintemp:= a xor b;

V.H.D.L.

sum <= temp xor c;x:= a and b;y:= b and c;z:= c and a;m:= x or y;carry<= m or z;end process;end Behavioral;SIMULATION

FULL ADDER(Structural )

entity full_adder_struc is Port ( A : in std_logic; B : in std_logic; C : in std_logic; Sum : out std_logic; Carry : out std_logic);end full_adder_struc;

architecture Structural of full_adder_struc is

component xor2 isport (e1, e2 : in std_logic;

e3: out std_logic);end component;component and2 isport (a1, a2 : in std_logic;

a3: out std_logic);end component;component or2 is

V.H.D.L.

port (o1, o2 : in std_logic;o3: out std_logic);

end component;

signal t1,t2,t3,t4,t5 : std_logic;beginx1 : xor2 port map ( a,b,t1);x2 : xor2 port map (t1,c,sum);a1 : and2 port map (a,b,t2);a2 : and2 port map (b,c,t3);a3 : and2 port map (a,c,t4);o1 : or2 port map (t2,t3,t5);o2 : or2 port map (t5,t4,carry);

end Structural;Component ANDentity and2 is Port ( a1,a2 : in std_logic; a3 : out std_logic);end and2;

architecture Behavioral of and2 is

beginprocess(a1,a2)begina3 <= a2 and a1;end process;end Behavioral;

Component OR

entity or2 is Port ( o1,o2 : in std_logic; o3 : out std_logic);end or2;

V.H.D.L.

architecture Behavioral of or2 is

beginprocess(o1,o2)begino3 <= o1 or o2;end process;end Behavioral;

Component XORentity xor2 is Port ( e1 : in std_logic; e2 : in std_logic; e3 : out std_logic);end xor2;

architecture Behavioral of xor2 is

beginprocess(e1,e2)begine3 <= e2 xor e1;end process;end Behavioral;

SIMULATION

V.H.D.L.

J-K FLIP FLOP

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity ff_jk is Port ( j,k,clr,preset,clk: in STD_LOGIC; q,qbar : inout STD_LOGIC);end ff_jk;architecture Behavioral of ff_jk isbeginprocess(clr,preset,clk)beginif( clk='0' and clr ='0' and preset='1') then q<='0';qbar<='1';elsif( clk='0' and clr ='1' and preset='0') then q<='1';qbar<='0';else if (clk='1' and clk'event) thenif(j='0' and k='0') then q<=q;qbar<= not q;elsif(j='0' and k='1') then q<='0';qbar<='1';elsif(j='1' and k='0') then q<='1';qbar<='0';else q<= not q;end if;end if;end if;end process;end Behavioral;

V.H.D.L.

SIMULATION

ENCODER

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;

entity encoder8_3 is Port ( a,b,c,d,e,f,g,h : in STD_LOGIC; y : out STD_LOGIC_VECTOR (2 downto 0));end encoder8_3;

architecture Behavioral of encoder8_3 isbeginprocess(a,b,c,d,e,f,g,h)beginif(h='1')then y<="111";elsif(g='1')

V.H.D.L.

then y<="110";elsif(f='1')then y<="101";elsif(e='1')then y<="100";elsif(d='1')then y<="011";elsif(c='1')then y<="010";elsif(b='1')then y<="001";elsif(a='1')then y<="000";end if;end process; end Behavioral;SIMULATION:-

D-FF:library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity dff is

V.H.D.L.

Port ( a,pr,clr,clk : in STD_LOGIC; q,qbar : inout STD_LOGIC);end dff;

architecture Behavioral of dff isbeginprocess(a,clr,pr,clk)beginif(clk='0' and clr='0' and pr='1') thenq<='0';qbar<='1';elsif(clk='0' and clr='1' and pr='0') thenq<='1';qbar<= '0';elsif(clk='1' and clk'event) then if(a='0') thenq<='0';qbar<='1'; elseq<='1';qbar<='0'; end if;end if;end process;end Behavioral;

V.H.D.L.

simulation:-

Parallel adderlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;

entity parladr is Port ( x,y : in STD_LOGIC_VECTOR (7 downto 0); z : out STD_LOGIC_VECTOR (7 downto 0); count : out STD_LOGIC);end parladr;

architecture structural of parladr iscomponent fuladr isport(a,b,c: in std_logic;

sum,carry:out std_logic);end component;

component hfadr isport(i,j: in std_logic;

s,c:out std_logic);

V.H.D.L.

end component;signal cout:std_logic_vector(6 downto 0);beginh1: hfadr port map(x(0),y(0),z(0),cout(0));f1: fuladr port map(x(1),y(1),cout(0),z(1),cout(1));f2: fuladr port map(x(2),y(2),cout(1),z(2),cout(2));f3: fuladr port map(x(3),y(3),cout(2),z(3),cout(3));f4: fuladr port map(x(4),y(4),cout(3),z(4),cout(4));f5: fuladr port map(x(5),y(5),cout(4),z(5),cout(5));f6: fuladr port map(x(6),y(6),cout(5),z(6),cout(6));f7: fuladr port map(x(7),y(7),cout(6),z(7),count);end structural;

Simulation

Multiplexer

V.H.D.L.

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;

entity mux4_1a is Port ( a : in STD_LOGIC; b : in STD_LOGIC; c : in STD_LOGIC; d : in STD_LOGIC; sel : in STD_LOGIC_VECTOR (1 downto 0); o : out STD_LOGIC);end mux4_1a;

architecture Behavioral of mux4_1a isbeginprocess(sel,a,b,c,d)begincase sel iswhen "00"=> o <=a;when "01"=> o <=b;when "10"=> o <=c;when others=> o <=d;end case;end process;end Behavioral;

V.H.D.L.

ALU (STRUCTURAL)library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity alu is Port ( s0,x,y,c : in STD_LOGIC; s : in STD_LOGIC_VECTOR (1 downto 0); cout,q : out STD_LOGIC);end alu;

architecture structural of alu iscomponent mix isport (x,y,c: in std_logic;s: in std_logic_vector (1 downto 0);cout,t1: out std_logic);end component;component lu isport (x,y: in std_logic;s: in std_logic_vector (1 downto 0);t2:out std_logic);end component;component mux is

V.H.D.L.

port( t1,t2: std_logic;q:out std_logic);end component;signal t1,t2: std_logic;begina1: mix port map ( x,y,c,s,cout,t1);l1: lu port map (x,y,s,t2);m1: mux port map (t1,t2,q);end structural;MIX UNIT :_ library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity mn is Port ( x,y,c : in STD_LOGIC; s : in STD_LOGIC_VECTOR (1 downto 0); t1,cout : out STD_LOGIC);end mn;architecture Behavioral of mn isbeginprocess (x,y,c,s)beginif (s="00") thent1<=x xor y xor c;cout<=((x xor y)and c) or ( x and y);elsif (s="01") thent1<= x xnor y xnor c;cout<=(( x xnor y) and c) or ( not(x and y));elsif (s="10") thent1<=x;elset1<=x xor c;cout<=x and c;end if;end process;end Behavioral;

V.H.D.L.

AU UNIT :_ library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity bv is Port ( x,y : in STD_LOGIC; s : in STD_LOGIC_VECTOR (1 downto 0); t2 : out STD_LOGIC);end bv;

architecture Behavioral of bv isbeginprocess(x,y,s)beginif( s="00") thent2<=x and y;elsif( s="01") thent2<= x or y;elsif(s= "10") thent2<=x nor y;elset2<= x xor y;end if;end process;end Behavioral;

MUX UNIT:_library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity vc is Port ( t1,t2,s0 : in STD_LOGIC; q : out STD_LOGIC);end vc;architecture Behavioral of vc is

V.H.D.L.

beginprocess( t1,t2,s0)beginif(s0='0') thenq<=t1;elseq<=t2;end if;end process;end Behavioral;

Simulation:-

DEMUX(CASE)library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;

V.H.D.L.

--use UNISIM.VComponents.all;

entity demux is Port ( sel : in STD_LOGIC_VECTOR (1 downto 0); a : in STD_LOGIC; i1,i2,i3,i4 : out STD_LOGIC);end demux;

architecture Behavioral of demux isbeginprocess(sel,a)begincase sel iswhen "00"=> i1<=a ;when "01"=> i2<=a ;when "10"=> i3<=a ;when others=> i4<=a ;end case;end process;end Behavioral;

Simulation;-

T-FF( using clk)entity T is Port ( a,prst,clr,clk : in STD_LOGIC; q,qbar : inout STD_LOGIC);end T;

V.H.D.L.

architecture Behavioral of T isbeginprocess(a,clk,prst,clr)beginif(clk='0' and clr='0' and prst='1') then q<='0';qbar<='1';elsif(clk='0' and clr='1' and prst='0') then q<='1';qbar<='0';elsif(clk='1' and clk'event) then if(a='0') then q<=q;qbar<= not q;elseq<=not q;qbar<=q;end if;end if;end process;end Behavioral; Simulation:-

COUNTER-UPlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;

entity CCOU is

V.H.D.L.

Port ( clk,prst,clr : in STD_LOGIC; count : inOUT STD_LOGIC_VECTOR (3 downto 0));end CCOU;

architecture structural of CCOU iscomponent ffjk isport (j,k,reset,set,clk: in std_logic;q,qbar: inout std_logic);end component;beginf1:ffjk port map('1','1',clr,prst,clk,count(0),open);f2:fFjk port map('1','1',clr,prst,count(0),count(1),open);f3:fFjk port map('1','1',clr,prst,count(1),count(2),open);f4:ffjk port map('1','1',clr,prst,count(2),count(3),open);end structural;

jk:-library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;

entity jk is Port ( j,k,clr,clk,prst : in STD_LOGIC; q,qbar : inout STD_LOGIC);end jk;

architecture Behavioral of jk is

beginprocess(clr,prst,clk)begin

V.H.D.L.

if( clk='0' and clr ='0' and prst='1') then q<='0';qbar<='1';

elsif( clk='0' and clr ='1' and prst='0') then q<='1';qbar<='0';

else if (clk='1' and clk'event) then

if(j='0' and k='0') then q<=q;qbar<= not q;elsif(j='0' and k='1') then q<='0';qbar<='1';elsif(j='1' and k='0') then q<='1';qbar<='0';else q<= not q;end if;

end if;end if;end process;end Behavioral;

FUNCTION NO. 1CONVERTOR

entity convert is Port ( x : in STD_LOGIC_VECTOR (3 downto 0); y : out integer);

function conversion(a:std_logic_vector(3 downto 0))

return integer isvariable d:integer; begind:=0;

V.H.D.L.

for n in 3 downto 0 loopd:=d*2;if(a(n)='1')thend:=d+1;end if;end loop;return d;

end conversion;end convert;architecture Behavioral of convert isbeginy<= conversion(x);end Behavioral;Simulation:-

Entity conversion isPort (x: in integer; Y:out std_logic_vector(7 downto 0));

function int2bit (f:integer)return std_logic_vector isvariable f1:std_logic_vector(7 downto 0);variable n,t,w:integer;beginw:=f;for n in 0 to 7 loopt:=w rem 2;if t=0 thenf1(n):='0';else f1(n):='1';end if;

V.H.D.L.

w:=w/2;end loop;return f1;end int2bit;end conversion;

architecture Behavioral of convert isbeginy<= int2bit(x);end Behavioral;

FUNCTION NO. 23 INPUT AND GATE

entity and_fnc is Port ( a,b,c : in STD_LOGIC; d : out STD_LOGIC);

function and1( x,y,z:std_logic)return std_logic isvariable w:std_logic;beginw:= x and y and z;return w;end function and1; end and_fnc;

architecture Behavioral of and_fnc isbegind<= and1(a,b,c);end Behavioral;Simulation:-

V.H.D.L.

PROCEDURE(adder)library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity vin_procedure is Port ( a : in STD_LOGIC; b : in STD_LOGIC; cin : in STD_LOGIC; sum : out STD_LOGIC; carry : out STD_LOGIC);PROCEDURE Push(p : in STD_LOGIC; q : in STD_LOGIC; r : in STD_LOGIC; signal s : out STD_LOGIC; signal cout : out STD_LOGIC) ISBEGINs<=p xor q xor r;cout<= (p and q) or (q and r) or (p and r); END PROCEDURE Push;end vin_procedure;architecture Behavioral of vin_procedure isbeginpush(a,b,cin,sum,carry);end Behavioral;

V.H.D.L.

Simulation:-

PROJECT: FLOATING POINT ARITHEMATIC:-

>>> In computing, floating point describes a system for numerical representation in which a string of digits (or bits) represents a rational number.

The term floating point refers to the fact that the radix point (decimal point, or, more commonly in computers, binary point) can "float"; that is, it can be placed anywhere relative to the significant digits of the number. This position is indicated separately in the internal representation, and floating-point representation can thus be thought of as a computer realization of scientific notation. Over the years, several different floating-point representations have been used in computers; however, for the last ten years the most commonly encountered representation is that defined by the IEEE 754 Standard.

The advantage of floating-point representation over fixed-point (and integer) representation is that it can support a much wider range of values. For example, a fixed-point representation that has seven decimal digits, with the decimal point assumed to be positioned after the fifth

V.H.D.L.

digit, can represent the numbers 12345.67, 8765.43, 123.00, and so on, whereas a floating-point representation (such as the IEEE 754 decimal32 format) with seven decimal digits could in addition represent 1.234567, 123456.7, 0.00001234567, 1234567000000000, and so on. The floating-point format needs slightly more storage (to encode the position of the radix point), so when stored in the same space, floating-point numbers achieve their greater range at the expense of slightly less precision.

The speed of floating-point operations is an important measure of performance for computers in many application domains. It is measured in FLOPS.

Floating-point representation is similar in concept to scientific notation. Logically, a floating-point number consists of:

A signed digit string of a given length in a given base (or radix). This is known as the significand, or sometimes the mantissa (see below) or coefficient. The radix point is not explicitly included, but is implicitly assumed to always lie in a certain position within the significand—often just after or just before the most significant digit, or to the right of the rightmost digit. This article will generally follow the convention that the radix point is just after the most significant (leftmost) digit. The length of the significand determines the precision to which numbers can be represented.

A signed integer exponent, also referred to as the characteristic or scale, which modifies the magnitude of the number.

The significand is multiplied by the base raised to the power of the exponent, equivalent to shifting the radix point from its implied position by a number of places equal to the value of the exponent—to the right if the exponent is positive or to the left if the exponent is negative.

Symbolically, this final value is

where s is the value of the significand (after taking into account the implied radix point), b is the base, and e is the exponent.

Historically, different bases have been used for representing floating-point numbers, with base 2 (binary) being the most common, followed by base 10 (decimal), and other less common varieties such as base 16 (hexadecimal notation).

V.H.D.L.

Range of floating-point numbers

By allowing the radix point to be adjustable, floating-point notation allows calculations over a wide range of magnitudes, using a fixed number of digits, while maintaining good precision. For example, in a decimal floating-point system with three digits, the multiplication that humans would write as

0.12 × 0.12 = 0.0144

would be expressed as

(1.2 × 10−1) × (1.2 × 10−1) = (1.44 × 10−2)

In a fixed-point system with the decimal point at the left, it would be

0.120 × 0.120 = 0.014

A digit of the result was lost because of the inability of the digits and decimal point to 'float' relative to each other within the digit string.

The range of floating-point numbers depends on the number of bits or digits used for representation of the significand (the significant digits of the number) and for the exponent. On a typical computer system, a 'double precision' (64-bit) binary floating-point number has a coefficient of 53 bits (one of which is implied), an exponent of 11 bits, and one sign bit. Positive floating-point numbers in this format have an approximate range of 10−308 to 10308 (because 308 is approximately 1023 × log10(2), since the range of the exponent is [−1022,1023]). The complete range of the format is from about −10308 through +10308 (see IEEE 754).

>> The IEEE has standardized the computer representation for binary floating-point numbers in IEEE 754. This standard is followed by almost all modern machines. Notable exceptions include IBM mainframes, which support IBM's own format (in addition to the IEEE 754 binary and decimal formats), and Cray vector machines, where the T90 series had an IEEE version, but the SV1 still uses Cray floating-point format.

Floating-point arithmetic operations

For ease of presentation and understanding, decimal radix with 7 digit precision will be used in the examples, as in the IEEE 754 decimal32 format. The fundamental principles are the same in any radix or precision, except that normalization is optional (it does not affect the

V.H.D.L.

numerical value of the result). Here, s denotes the significand and e denotes the exponent.

Addition and subtraction

A simple method to add floating-point numbers is to first represent them with the same exponent. In the example below, the second number is shifted right by three digits, and we then proceed with the usual addition method:

123456.7 = 1.234567 * 10^5 101.7654 = 1.017654 * 10^2 = 0.001017654 * 10^5 Hence: 123456.7 + 101.7654 = (1.234567 * 10^5) + (1.017654 * 10^2) = (1.234567 * 10^5) + (0.001017654 * 10^5) = (1.234567 + 0.001017654) * 10^5 = 1.235584654 * 10^5

In detail:

e=5; s=1.234567 (123456.7)+ e=2; s=1.017654 (101.7654)

e=5; s=1.234567+ e=5; s=0.001017654 (after shifting)-------------------- e=5; s=1.235584654 (true sum: 123558.4654)

This is the true result, the exact sum of the operands. It will be rounded to seven digits and then normalized if necessary. The final result is

e=5; s=1.235585 (final sum: 123558.5)

Note that the low 3 digits of the second operand (654) are essentially lost. This is round-off error. In extreme cases, the sum of two non-zero numbers may be equal to one of them:

e=5; s=1.234567+ e=-3; s=9.876543

e=5; s=1.234567+ e=5; s=0.00000009876543 (after shifting)----------------------

V.H.D.L.

e=5; s=1.23456709876543 (true sum) e=5; s=1.234567 (after rounding/normalization)

Another problem of loss of significance occurs when two close numbers are subtracted. In the following example e = 5; s = 1.234571 and e = 5; s = 1.234567 are representations of the rationals 123457.1467 and 123456.659.

e=5; s=1.234571- e=5; s=1.234567---------------- e=5; s=0.000004 e=-1; s=4.000000 (after rounding/normalization)

The best representation of this difference is e = −1; s = 4.877000, which differs more than 20% from e = −1; s = 4.000000. In extreme cases, the final result may be zero even though an exact calculation may be several million. This cancellation illustrates the danger in assuming that all of the digits of a computed result are meaningful. Dealing with the consequences of these errors is a topic in numerical analysis; see also Accuracy problems

Multiplication

To multiply, the significands are multiplied while the exponents are added, and the result is rounded and normalized.

e=3; s=4.734612× e=5; s=5.417242----------------------- e=8; s=25.648538980104 (true product) e=8; s=25.64854 (after rounding) e=9; s=2.564854 (after normalization)

Division is done similarly, but is more complicated.

There are no cancellation or absorption problems with multiplication or division, though small errors may accumulate as operations are performed repeatedly. In practice, the way these operations are carried out in digital logic can be quite complex.

V.H.D.L.

PROGRAM FOR FLOATING POINT ARITHEMATIC:-

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity fpa is

Port ( a:in STD_LOGIC_VECTOR (31 downto 0); b:in STD_LOGIC_VECTOR (31 downto 0); c:out STD_LOGIC_VECTOR (31 downto 0); overflow:out bit; underflow:out bit; normalised:out bit );

function bit2int(a:std_logic_vector(7 downto 0))

return integer isvariable d:integer; begind:=0;

for n in 7 downto 0 loopd:=d*2;

if(a(n)='1')thend:=d+1;end if; end loop;return d;

end bit2int;function bit23_2int(a:std_logic_vector(22 downto 0))

return integer isvariable d:integer; begind:=0;

for n in 22 downto 0 loopd:=d*2;

V.H.D.L.

if(a(n)='1')thend:=d+1;end if; end loop;return d;

end bit23_2int;function int2bit (f:integer)return std_logic_vector isvariable f1:std_logic_vector(7 downto 0);variable n,t,w:integer;beginw:=f;for n in 0 to 7 loopt:=w rem 2;if t=0 thenf1(n):='0';else f1(n):='1';end if;w:=w/2;end loop;return f1;end int2bit;

function int25_2bit (f:integer)return std_logic_vector isvariable f1:std_logic_vector(25 downto 0);variable n,t,w:integer;beginw:=f;for n in 0 to 25 loopt:=w rem 2;if t=0 thenf1(n):='0';else f1(n):='1';end if;w:=w/2;end loop;

V.H.D.L.

return f1;end int25_2bit;function int24_2bit (f:integer)return std_logic_vector isvariable f1:std_logic_vector(24 downto 0);variable n,t,w:integer;beginw:=f;for n in 0 to 24 loopt:=w rem 2;if t=0 thenf1(n):='0';else f1(n):='1';end if;w:=w/2;end loop;return f1;end int24_2bit;

function int23_2bit (f:integer)return std_logic_vector isvariable f1:std_logic_vector(23 downto 0);variable n,t,w:integer;beginw:=f;for n in 0 to 23 loopt:=w rem 2;if t=0 thenf1(n):='0';else f1(n):='1';end if;w:=w/2;end loop;return f1;end int23_2bit;

V.H.D.L.

end fpa;

architecture Behavioral of fpa issignal x1:integer:=0;signal x2:integer:=0;signal z:integer:=0;signal r,q:integer:=0; signal k1,g1,k2,g2,k3,g3,k4,g4,k5,g5:integer :=0;signal overf1,overf2:bit;signal underf1,underf2:bit;signal o:std_logic_vector(7 downto 0);signal o1:std_logic_vector(7 downto 0);signal p:std_logic_vector(25 downto 0);signal j:std_logic_vector(25 downto 0);signal w:std_logic_vector(24 downto 0);signal t:std_logic_vector(24 downto 0);signal v:std_logic_vector(23 downto 0);signal s3:std_logic;signal e3,e4,e5,e6,e7,e8:std_logic_vector(7 downto 0);signal m3,m4,m5,m6,m7,m8:std_logic_vector(22 downto 0);alias s1:std_logic is a(31);---sign bit of 1st floating point noalias e1:std_logic_vector (7 downto 0) is a(30 downto 23);---exponent of 1st floating point noalias m1:std_logic_vector (22 downto 0)is a(22 downto 0);---mantissa of 1st floating point no

alias s2:std_logic is b(31);---sign bit of 2nd floating point noalias e2:std_logic_vector (7 downto 0) is b(30 downto 23);---exponent of 2nd floating point noalias m2:std_logic_vector (22 downto 0)is b(22 downto 0);---mantisa of 2nd floating point no

beginx1<=bit2int(e1);--exponent1 in integer form x2<=bit2int(e2);--exponent2 in integer formr<=bit23_2int(m1);--mantissa1 in integer formq<=bit23_2int(m2);--mantissa2 in integer form

V.H.D.L.

z<=abs(x1-X2);

b1: block(z>=3 and x1>x2)beginoverf1<='1' when guard else '0';k1<=(r * 8) when guard else 0; --mantissa1 gets left shited by 3 placesg1<=(k1+q) when guard else 0;o<=int2bit(x2);j<=int25_2bit(g1);e3<=o when guard else "00000000";m3<=j(22 downto 0);end block b1;

b2: block(z<=2 and z/=0 and x1>x2)beginunderf1<='1' when guard else '0';k2<=(r *4) when guard else 0; --mantissa1 gets left shited by 2 placesg2<=(k2+q) when guard else 0;o<=int2bit(x2);w<=int24_2bit(g2);e4<=o when guard else "00000000";m4<=w(22 downto 0);end block b2;

b3:block(z=0)beginnormalised<='1' when guard else '0';g3<=(r+q) when guard else 0;--no shifting just additiono<=int2bit(x1);v<=int23_2bit(g3);m5<=v(22 downto 0);e5<=o when guard else "00000000";end block b3;

b4: block(z>=3 and x1<x2)begin

V.H.D.L.

overf2<='1' when guard else '0';k4<=(q * 8)when guard else 0;--mantissa2 gets left shited by 3 placesg4<=(k4+r)when guard else 0;o1<=int2bit(x1);p<=int25_2bit(g4);e6<=o1 when guard else "00000000";m6<=p(22 downto 0);end block b4;

b5: block(z<=2 and z/=0 and x1<x2)beginunderf2<='1' when guard else '0';k5<=(q * 4) when guard else 0;--mantissa2 gets left shited by 2 placesg5<=(k5+r)when guard else 0;o1<=int2bit(x1);t<=int24_2bit(g5);e7<=o1 when guard else "00000000";m7<=t(22 downto 0);end block b5;

overflow<=overf1 xor overf2;underflow<=underf1 xor underf2;e8<=e3 xor e4 xor e5 xor e6 xor e7;--exponent of outputm8<= m3 xor m4 xor m5 xor m6 xor m7;--mantissa of outputs3<=s1 xor s2;--sign bit of output

c<=s3 & e8 & m8;--outputend Behavioral;

V.H.D.L.

Simulation:-For x1=x2

V.H.D.L.

For x1>x2

V.H.D.L.

For x2>x1:-

V.H.D.L.

V.H.D.L.

V.H.D.L.

V.H.D.L.

V.H.D.L.

V.H.D.L.

V.H.D.L.

V.H.D.L.

V.H.D.L.

V.H.D.L.

V.H.D.L.

V.H.D.L.

V.H.D.L.

V.H.D.L.

V.H.D.L.

V.H.D.L.

V.H.D.L.

V.H.D.L.

V.H.D.L.

V.H.D.L.

V.H.D.L.