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Hands-

By:- Saur

Sr.As

Dept. Of C

Saurabh_singh19

n VHDL

bh Singh

t.Pro .

E BIT Durg

3@rediffmail.com

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VH

SUDSystem Under

Design

I/P

DL

O/P

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VH

SUDSystem Under

Design

I/P

O/P DL Input And Output

are Interface of

Digital System. IN VHDL it is

known as Ports

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VH

SUDSystem Under

Design

DL

FunctionalDiscription of SUD

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VH Functional Descrip

as ARCHITECTUR

There are 3 BasicARCHITECTURE

Behavioural Style- M

Data Flow Style- CoStructural Style- M

Abstraction (ONETHEM)

DLion of SUD is KnownE.

tyle for describing the

s Abstract,Sequential

curren Stmt.os detail Level of

CAN MIX ALL OF

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Points To

VHDL is Case In S

Comments:---

Decimal Integers:-

Based Integer :- 2

Signal:- An Intenal

VHDL Architecturedesign together

emembe

nsitive

1,2 ,3_455

1001,16#0011_0000

Connection with in

that connects parts of

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Structure of V DL Programe

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Package (optional)

Entity (design I/0)

Architecture (design

c

Signal declaration

Component instantiati

Conditional signal assi

Selected signal assign

Generate statement

Process statement

Variable decla

Signal assignVariable assig

Procedure call

if, case, loop,

Wait statemen

function)

oncurrent statements

n statement

nment statement

ent statement

equential statements

ation

entment

ext, exit, return

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Documentation Part

Library and Package Part

ENTITY and Port Part

ARCHITECTURE PART

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VHDL Objec

Constant

Signal

Variable

File

HowObject_NameName_Identifier:Type [

Declarations

o Userange_Constraint] [:=Expression]

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VHDL Objec

-:ExaSignal s :

Signal s1 : std_logic

ObjectNam

Declarations

ple:-Bit := 1_vector(3 downto 0)

for objec Type

Range constraint

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VHDL Logical Operat

boolean,std_logic,length.Noton integ

Relational Opeoperands of the saboolen(,=)

Arithmatic Operan,real,std_logic

Concatenation:- '&'

perato:-works on bit,vector of equal

.

ato :-Compare twome type and produce a

ds:- Works on ineger

(abb &wsx=abbwsx)

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Signals an

Both are used to represent wires

Signals are used to transfer datacomponents

< = when assigning to si

Variables can only be used insid

Variable assignment is immediatprocess occurs after leaving th

: = when assigning to variables

Variables

nd/or logic

etween processes and

nals

processes

, while signal assignment in aprocess

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Writing and Unders anding VHDL Prog.

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Use Lib_name.packaExa

Use IEEE.STD_

Library anName of library

Pac

ge_name.item_nameple

LOGIC_1164.all

Package

age Name All Item

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Entity a

entity encoderisport (a,b: in std_logic;

enable : in std_logic;y : out std_logic_v

);endencoder;Defines I/O ONLY

if this is the top level entity for you des for a lower level entity, ports are like p

No hint of underlying structure

d Ports

ctor(3 downto 0)

ign, the port lists your pinsorts on schematic symbol

ODE of Por

Type of Port

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Architect

Architecture name_arc

begin

end name_arch

Used for declarationsignal

Used for prOne can Use an

DataConcStru

Mi

ure Bod

OF Entity_name IS

f

grammingy Modeling styleFlowrrenturaled

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Design of

entity fa is

Port ( a,b,cin : in ST

sum,carry : out

end fa;

Full Adde

D_LOGIC;

STD_LOGIC);

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Design of

architecture Behavioral

begin

sum

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Design of

architecture Behavioral

signal axor,a_and : st

begin

axor

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Design ofarchitecture Behavioralbegin

process (a,b,cin)

variable axor,a_and : std

begin

axor :=a xor b;

a_and :=a and b;sum

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The Proc

Process ( S_LIST)

begin

end process;

Used for deVari

Seq

ss Stmt.

claration ofble

ential Stmt.

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The Proc

In side process we can

IF condition THEN

sequential stmt.

{ELSIF condition THE

[ ELSE sequential stmt

end if;

ss Stmt.

use following stmt.

stmt

]

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The Proc

In side process we can

CASE expression IS

WHEN choices-1 =>

WHEN choices-n => s

WHEN OTHERS => st

END CASE;

ss Stmt.

use following stmt.

equenc of stm

equenc of stm

t.

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Ex. of Iarchitecture behv of D_latch is

begin

process(data_in, enable)

beginif (enable='1') then

-- no clock signal here

data_out

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EX.of CAarchitecture behv of ALU is

begin

process(A,B,Sel)

begincase Sel is

when "00" =>

Res Res

SE Stmt.

Res

Res

Res

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Concurr

target_signal

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Conurre

architecture behv of D

begin

data_out