VLA Technical Report No, 49 MODULE T5C BASEBAND DRIVER W...

VLA Technical Report No, 49

MODULE T5C BASEBAND DRIVER

W. E. Duinke

December 1980

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CONTENTS

GENERAL DESCRIPTION

CIRCUIT DETAILS

2.1 Module Shielding and Filtering

2.2 ALC/Driver Amplifier Assembly A2

2.3 Power Amp/Sq Law Detector Assembly A3B

2.4 Synchronous Detector/Gated ALC Loop Amp Assembly A1

2.5 Voltage Regulator Assembly A4

FRONT PANEL INDICATORS AND CONTROLS

3.1 Total Power Meter

3.2 Monitor Jacks

3.3 "GAIN” Control

3.4 "Baseband Out" BNC Jack

TEST PROCEDURE

4.1 Test Set-Up

4.2 Detector "OFFEST" Adjustment

4.3 Detector "GAIN” Resistor Selection (R2q) an<*Gain Adjustment

4.4 Synchronous Detector '’GAIN MATCH” Adjustment

4.5A Check Front Panel Voltages

4.5B Check DCS Voltages at Test Fixture Outputs

4.6 Check ALC Operation

4.7 Return SI on A1 Board to D1 Sampler Detector Position

LIST OF DRAWINGS

DATA SHEETS

APPENDICES

7.1 Baseband System Specifications

7.2 Power Amp/Square Law Detector Assembly A3A

1.0 GENERAL DESCRIPTION

The T5C Baseband Driver performs a number of functions.

Refer to Block Diagram C13820B3D. First, it amplifies the output

of the T4C Baseband Filter module to a level required by the D1

Sampler module input including the cable loss from "D” rack to

Screen Room.

Second, the output level is stabilized by a Sample and Hold

ALC loop during the time the IF signals are being received at the

Central Electronics Room MD" rack at the !,Cal Off*' period (the

time the Front End calibration noise source is turned off). The

detector for this level can either be the D1 Sampler Input Level

detector (normal operation) or the internal T5C Precision Square

Law Detector (used for ALC bench testing). By using the D1

Sampler Detector the level can be more precisely set at the input

to the sampler, because the coax cable/filter loss (which varies

from "D” rack to "D” rack) is within the loop.

Third, a precision synchronous Square Law Detector in the

T5C Baseband Driver is used to derive the "SYN11 and "Cal Off”

voltages from which the Tgyg/T^^ rati° can be calculated after

the final analog filtering in the T4C Baseband Filter, for use in

the spectral line observing mode. This can be used to calibrate

out Front End noise temperature variations and signal/noise ratio

variations from the IF transmission system versus frequency.

However, IF transmission compression effects must be compensated

to assure accuracy.

2.0 CIRCUIT DETAILS

2.1 Module Shielding and Filtering

Refer to module Schematic D13820S1E. Because of the

operating frequency range of 200 KHz to 50 MHz in the T4C

and T5C baseband system, special precautions had to be taken

to insure adequate shielding and filtering to prevent interference

from L0 and digital signals. Special modules were designed

with shielding as the prime concern. To prevent interference

from LO signals (5 MHz and above) the module was designed

with tight fitting lids (with eleven fastening screws rather

than the usual six), and all inputs and outputs filtered,

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through shielded compartments. All power supply lines are

filtered with 7t section low pass feedthrough filters. All

digital signals are fed through 0.01 |JF feedthrough capacitors

to not degrade rise and fall times excessively. No wires or

cables enter or leave the chassis without feedthrough filtering

or proper grounding. This prevents signals entering the

module flowing on the outsides of coax, for example.

However, even these steps proved inadequate for lower

frequency interference from the fundamental and harmonics of

various digital communications system clock signals. The

worst culprit, in this case, was a 10 KHz LED driver clock

signal from the M2 Data Tap module. It and its harmonics

could enter the module on any of the power supply buss lines

common to the entire "D" rack. Since the specified bandwidth

of operation in the entire baseband system is 200 KHz to 50

MHz with less than 1.5 dB peak to peak variation, and since

signal levels are low in several locations, serious interference

could occur in the spectral line mode which uses the narrower

and consequently lower frequency filters.

A filter for general use on the T3, T4, T5 module power

supply lines consists of a 250 pH low resistance choke with

a 33 |iFd low series resistance tantalum capacitor. This

provides -30 dB attenuation at 10 KHz under worst case

conditions. The capacitors are mounted on the printed

circuit boards in the T4C and T5C modules. The chokes are

mounted inside the rear module shielded compartment near the

Amp connector.

The T4C and T5C module housing are unique designs that

provide shielding, optimum air flow, and excellent grounding

for the microstrip and analog printed circuit boards.

Maximum air flow is achieved by using the largest diameter

holes consistent with the mechanical constraints of the top

and bottom rail design. The holes are small enough to also

provide adequate shielding in the operating frequency range.

The modules are designed such that the PC boards are

accessible from both sides by removing each side plate for

2

ease in servicing. By using adjustable divider rails, PC

boards can be moved to different positions within the module.

Also PC boards of different sizes can be accommodated for

versatility with possible future changes.

Microwave power transistors or hybrid amplifiers (such

as those used in the T5C modules) can be readily heatsunk to

the top or bottom rails using special heatsink brackets that

allow for short RF connections to the PC board microstrip

lines as well as low thermal resistance. These heatsink

brackets can be moved to any rail location again for versatility

with possible future changes.

2.2 ALC Driver Amplifier Assembly A2

Refer to Schematic C13820S6F. To obatin excellent

phase stability versus temperature, along with non-variation

of amplitude and phase non-linearity of the 200 KHz to 50

MHz passband over the typical ALC range of the T5 module, a

differential amplifier ALC system is used.

A pin diode or "mixer" type variable attenuator constitutes

a variable resistance to vary attenuation. If a single

device is driving any substantial reactance at the load, the

phase linearity versus passband response will vary with

varying attenuation. Another requirement of operation of

such a device, is low level RF drive to minimize intermodulation

distortion.

A differential amplifier ALC with a 51Q input and

output load resistance resolves these problems while providing

excellent phase stability versus temperature.

The CA3102E transistor array forms the differential

amplifier in the T5C ALC system. Because the amplifier gain

is based on the difference in RF voltage across the two

transistor base to emitter junctions, and because these

transistors are closely matched, the phase stability versus

temperature is excellent. Since the input and output are term

inated immediately in 51Q, and only the voltage gain and not

input and output impedances change with ALC voltage, the phase

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non-linearity versus passband response versus ALC voltage

remains constant.

Phase change versus ALC has been measured at less than

0.6°/dB at 50 MHz at the typical operating point over a

±10 dB range, for this particular amplifier after frequency

compensation. Phase non-linearity versus passband response

was measured at less than 2° from 10 MHz to 50 MHz. This

varied less than 2° per ±10 dB ALC variation about the

typical operating point from 10 MHz to 50 MHz.

Frequency compensation is required because of the

uncompensated amplifier. This is accomplished through the

use of a 10 pF capacitor in a positive feedback configuration.

Passband amplitude variation will only occur as a result of

component tolerances, and otherwise was shown to be negligible

over a 10 MHz to 50 MHz range.

Maximum gain of the amplifier was measured at +3.1 dB

at -0.7 VDC. Minimum gain (or isolation) was measured at

-62 dB at -6.0 VDC at 50 MHz.

Hybrid amplifiers GPD 461, GPD 462 and GPD 463 (with

heatsink) comprise most of the gain in the Driver Amplifier.

Because all 3 stages along with the ALC amplifier were

contributing significantly to module compression, -12.5 dB

of attenuation was added to the ALC amplifier input to

compensate for the +12.5 dB of extra power amplifier gain

while keeping the ALC amplifier operating near it’s most

stable (versus temperature) range.

2.3 Power Amplifier/Square Law Detector Assembly A3B

To minimize compression in the T5C output stage a two

stage discrete transistor power amplifier is utilized. This

was required as the result of the inability of any available

hybrid driver amplifier to operate at a required power level

of +16.5 dBm - 12.5 dBm = +4 dBm with less than 1% compression.

The E1E5 stage Q1 is identical to the power amplifier of the

obsolete A3A board. A Schematic of the obosolete version is

given in Appendix 8.2, Drawing No. C13820S5H, for reference

only.

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The new version two stage amplifier is shown in Schematic

C13820S5L.

Both stages operate on the resistor negative feedback

Class A mode for low distortion and 50Q input/output matching.

Resistor values have been chosen to obtain this matching,

and thereby result in a gain of +12.5 dB per stage independent

of transistor hyj,. Passband flatness in both stages is

limited by three major effects. First the passband performance

of the collector choke limits flatness, especially at high

DC currents which tend to saturate the core. A special

choke was wound on stacked iron cores, for high inductance

at 200 KHz with DC current and simultaneous low interwinding

capacitance. At zero DC current the shunt effect of the

inductor in a 50Q system was measured at -0.00 dB at 200 KHz

and -0.07 dB at 50 MHz. Because of the minimal effect on

passband response the temperature variation of the inductor

core material should have negligible effect on system phase

stability.

The second passband rolloff effect is due to the series

inductance of the emitter resistor. Inductance will cause a

gain decrease IF comparable to the collector impedance.

Therefore A resistors with short leads and wide PC board

pads are used in parallel to minimize this effect.

The third major contribution to passband rolloff is due

to positive feedback through the power supply lines with

cascaded amplifiers. This will occur usually at low frequencies

(due to the ineffectiveness of power supply bypass capacitors)

and will result in a peaking of the total gain response

toward the 200 KHz end. Because the coupling capacitor

reactances limit low end frequency response total gain will

peak at some frequency below 200 KHz. Since this peaking is

the opposite effect as passband rolloff at the high frequency

end, it, in effect, contributes to total passband rolloff.

This effect has been minimized through the use of large

value, low series resistance and low series inductance

tantalum bypass capacitors. If frequency compensation is

5

desired later, this effect will have to be corrected indepen

dently of the high frequency rolloff to minimize passband

phase non-linearity.

No frequency compensation has been added to any of the

baseband amplifier stages with the exception of the ALC

amplifier in the T3, T4 and T5 modules since it appeared

that the passband response design goals could be met without

it.

Passband response profiles of the two stage amplifier

have not been made at this time. However, earlier measurements

of the single stage A3A amplifier (somewhat in compression)

indicated -0.55 dB total amplitude rolloff with a total

phase non-linearity of 3.7° peak to peak from 200 KHz to 50

MHz.

Total amplifier compression in the T5C module was

measured at -1.3% or -1.5% at actual system noise power

output levels for two modules.

The precision Square Law Detector is a BD-4 back diode.

A back diode is used for combined linearity and temperature

stability. A hot-carrier diode is totally unsuitable for a

temperature stable detector. Because of the low DC level

out of the diode, a very low input offset voltage bipolar OP

Amp (0P-05-EY) was required as a preamplifier.

"CERMET" trimpots for the OP Amp gain and offset adjustments

were found to be unsuitable because of wiper contact problems

resulting in 10 tiroes worse temperature stability than the

"CERMET" material specification along with significant low

frequency noise.

Thus wirewould trimpots were chosen instead. These

trimpots have a disadvantage in that they have limited

resolution. Thus a fixed gain control resistor R20 has to

be chosen during module checkout to provide a coarse adjustment.

Precision measurement of diode non-linearity on noise

power at the system operating point resulted in -0.7% or

-2.7% absolute compression for two different modules.

Temperature stability at the normal operating point for the

complete T5C breadboard detector and amplifier resulted in

0.1%/°C error.

6

2.4 Synchronous Detector/Gated ALC Loop Amp Assembly Al

Refer to Schematic D13820S4F.

The synchronous detector in the T5C Baseband Driver had

some stringent requirements on stability and accuracy. For

this reason ultra-low offset voltage bipolar Op Amps are

used in the detector circuit. Offset trimpots were unnecessary

with these amplifiers resulting in simpler module set-up and

less possibility of operator error. Bipolar Op Amps also

have a major advantage over JFET Op Amps (commonly used in

synchronous detectors) in that input offset voltages will

remain stable with time. However, higher input bias and

offset currents require smaller sample and hold timing

resistances, to minimize total input offset voltage. Thus

large value low leakage polycarbonate capacitors (10 jjF) are

required.

Detailed analysis of synchronous detector and ALC loop

amplifier worst case errors is given in Figure 2.4.2. Note

that a "Gain Match" potentiometer (again wirewound) was

utilized to match the input gains of the difference amplifier

U4, determined by 1% resistance values.

AD 741 LN Op Amps are used as output buffers to isolate

the system from DCS noise feeding back from the T6C module.

"SYN", "CAL OFF", and "ALC" monitor voltages are isolated in

this manner.

Figure 2.4.3 shows the relationship of and

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Figure 2.4.3

2.5 Voltage Regulator Assembly A4

The ALC amplifier on the ALC/Driver amplifier requires

±6 VDC for proper operation. Three terminal IC regulators

of the 7805 family were found to be inherently unstable.

Because of the broad frequency range of the T5C module,

these were abandoned in favor of a simpler stable Zener

diode system. The Schematic is given by B13820S7D.

3.0 FRONT PANEL INDICATORS AND CONTROLS

3.1 Total Power Meter

This meter is connected to the "CAL OFF" output of the

synchronous detector. Thus it is always connected to the

T5C internal square law detector. It is calibrated to 50 |jA

(+5 VDC @ v cax. oFF^ *or +1^*^ outPut. Note that in the

system it will read higher than 50 pA because of cable

losses to the sampler module, which is normally used to set

the T5C output level.

3.2 Monitor Jacks

"DET" is connected to the detector line that feeds the

ALC loop filter. In normal operation the detector switch on

the Al card is in the "D1 Sampler" detector position, and

this monitor jack will read the sampler detector output at

+5.00 VDC gated with the modem T/R pulse. In the test

position (switch in the "T5" detector position) this monitor

jack will read the internal T5C detector output. If the

internal switch is accidently left in the test position when

placed ‘in the system, both the total power meter and the

detector monitor jack will read +5.00 VDC.

"CAL ON" is connected to the Al card "CAL ON" synchronous

detector output. This voltage is sampled when the front end

calibration noise source is turned on. Therefore in normal

operation it would be 3 to 10% higher than the "CAL OFF"

monitor jack.

"CAL OFF** is connected to the Al card "CAL OFF” synchronous

detector output. This voltage is sampled when the front end

10

REV. OATE DRAWN BY APPRVOBV DESCRIPTION

J l-3 > - 15V

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NEXT ASSY USEO ON

UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHESTOLERANCES: ANGLES ±1 PLACE DECIMALS (.XXX): ±2 PLACE DECIMALS (.XX): ±1 PLACE DECIMALS (.X): ±

MATERIAL:

FINISH:

T 5 -C £BASEBAND DfclVEB

VOLTA6E RE6ULATOR RC. CA&O

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ORAM BY I DATE

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calibration noise source is turned off. It should normally

read somewhat higher than +5 VDC in the system.

"SYNM is connected to the difference amplifier output

of the T5C synchronous detector output. The difference

amplifier has a gain of 10 so that

TSYS _ VCAL0FF x 10T ~ VCAL SYN

The percentage increase is normally 3 to 10% of 5 VDC.

Therefore V g ^ should be positive and between 0.15 and 0.5

VDC. If it is negative, check the gating system.

"ALC" is connected to the ALC voltage feeding the A2

card ALC amplifier. This voltage is clamped to -6.7 volts

at minimum gain and about **0.7 volts at maximum gain by

Zener diode CR7 on the A1 card. At normal system operation

it should read about -4 VDC. When the T5C module is first

plugged into the rack this voltage will be at maximum gain

-0.7 volts until the integrator capacitor charges to its

normal state. Also the total power meter will peg high as a

result.

3.3 "Gain" Control

This pot is connected to the ALC amplifier input when

the T6C Baseband Control module is switched to the manual

position for that channel. Clockwise is increasing gain.

3.4 "Baseband Out" BNC Jack

This jack is connected to the output of the T5C power

amplifier through a -40 dB resistor voltage divider network

when both the T5 output and the BNC jack are terminated in

50Q.

Note that this is connected to a resistive voltage

divider and not a directional coupler. Therefore the total

voltage across the T5C output is being measured and not

forward power. Total voltage is the sum of the forward

voltage and the return voltage from the Screen Room filters

and sampler input return losses.

11

Calculation of maximum in-band (200 KHz - 50 MHz)

amplitude ripple and frequency due to D1 sampler and Screen

Room filter VSWR as measured at T5C "Baseband Out" BNC

monitor jack is given below:

Assume cable loss negligible

D1 Sampler ps = .056 for s = 1.12 max

70 MHz LPF pf = .20 for s = 1.5 max

Total coax to LPF 100 ft > Z > 50 ft.

"Baseband Out" ripplepp < 20 dB L0G jQ ( )

<4.5 dB HORST CASEP P

fripple i 2~1_~ <Hz> r max

i ( f ( 3 0 X«8l)m/S) = 3 '25 for 100 ft' max

< vp cripple - 2 1 .

rr m m(Hz)

> = 7 * 5 m z for 50 ft-

Calculation of maximum in-band (200 KHz - 50 MHz) amplitude

ripple due to D1 sampler, Screen Room filter and T5C VSWR as

measured at D1 sampler input is given below:

Assume cable loss negligible

D1 Sampler ps = .056 for s = 1.12 max

70 MHz LPF pf = .20 for s = 1.5 max

T5C output pt = .060 for s = 1.13 max

D1 input ripplepp < 20 dB LOG10 ( ]^[pstpf) >

< 0.27 dB worst case p p

12

Check wiring harness with ohmmeter against module Schematic

D13820S1.

Check that all ICfs are oriented properly in their sockets.

(Dot on component side marks Pin 1. Tab on TO-99 packages marks

Pin 8.) DO NOT confuse these markings.

Check that GPD amplifiers are correctly mounted against

board, ( n marks tab of GPD amplifier.)

Set power supply voltages at filter inductors for ±10 mV.

Place T5B in Manual mode and turn Front Panel Gain Control

clockwise. Check for increasing power output past +20 dBm. If

this cannot be obtained, check to be sure the E1E and CD2810 are

soldered in correctly. Removing A3-P1 should lower +28 VDC power

supply current by 200 mA if power amplifiers are functioning

properly.

If the ALC Driver Board lacks output check for -1 to -6

volts on line as gain is adjusted. Use a high speed scope

(such as a 475) to trace through the various stages for signal if

Va l c is satisfactory.

Place spectrum analyzer on output jack. If oscillation

appears (usually near 900 MHz) at any given setting of the Front

Panel Gain Control, check all component values, plated-through

holes, and chip capacitors for leaching. (Sudden changes in

meter reading versus gain control setting is also a symptom of

this problem.)

4.0 TEST PROCEDURE

13

BASEBAND ALIGNMENT PROCEDURES

T5B Alignment - as follows

4.1 Test Set-up

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14

4.2 Detector "OFFSET" Adjustment

Terminate J2 (baseband input) and connect J1 (baseband

output) to HP8482A power sensor. Turn T5B front panel gain

to minimum in manual mode. With left side panel secured to

module let module stabilize to room temperature. (Approximately

\ hour.)

Install 71.5 KQ 1% resistor at R20 on A3 board.

Connect DVM to DET and GND and adjust "Offset" pot on

A3 board for 0.0000 ± .0005 VDC output.

4.3 Detector "GAIN" Resistor Selection (R£q ) an^ Gain Adjustment

Connect J2 (Baseband Input) to noise source through

fixed attenuator pad selected to give approximately -28.5

dBm noise power as measured with HP8482A and HP435A. Record

level.

Connect DVM to "DET" and "GND".

Connect J1 (Baseband Output) to HP8482A power sensor.

With T5B in manual mode, adjust front panel manual gain

control for +16.5 dBm output power.

Set power meter cal factor for 30 MHz.

Measure detector voltage with A3 Board "Gain" adjust

trimpot at minimum and maximum settings. Calculate R^q

value using following formula:

D = R ____________________1 2 ____________________

20 20(Initial) VDET Max + ^ g ^ M i n )

Insert R^q on A3 board and set "Gain" adjust trimpot for

+5.000 ± .001 VDC output at "DET". Check front panel meter

for midscale. Change R^q if necessary.

Recheck offset.

4.4 Synchronous Detector "Gain Match" Adjustment

Set SI on A1 Board to T5 detector position.

With "DET" at 5 VDC as in 4.3, move DVM to "SYN" and

"GND".

15

Adjust "Gain Match" trimpot on A1 Board to 0.000 VDC ±

.001 VDC averaged over many DVM samples.

4.5 (A) Check Front Panel Voltages

(Use set up of 4.4.)

DET = 5.000 ± .001 VDC

CAL OFF = 5.000 ± .005

CAL ON = 5.000 ± .005

SYN = 0.000 ± .001 VDC

ALC - -4.0 VDC

(B) Check DCS Voltages at Test Fixture Outputs

DCS CAL OFF = 5.000 ± .005 VDC

DCS SYN = 0.000 ± .001 VDC

DCS ALC ~ -4.0 VDC

4.6 Check ALC Operation

(Use set up of 4.4.)

Set SI on A1 Board to T5 Detector position.

Set T5B in automatic mode and remeasure front panel

voltages after stabilization.

DET = 5.00 ± .15 VDC

CAL OFF = 5.00 ± .020 VDC

CAL ON = 5.00 ± .020 VDC

SYN = 0.000 ± .001 VDC

ALC ~ -4.0 VDC

4.7 Return SI on A1 Board to D1 Sampler Detector Position

16

T5B ALIGNMENT RESULTS

Module Serial No. ______________________________

Date ____________________________________________

By ______________________________

1*20 = ____________________________________ - ® (From 3.)

DET = ____________________________________ V (From 5.)

CAL OFF = ________________________________ V

CAL ON = __________________________________ V

SYN = ____________________________________ _ V

ALC = _____________________________________ V

DCS CAL OFF = V

DCS SYN =

DCS ALC =

DET (AUTO) = _____________________________ V (From 6.)

CAL OFF (AUTO) = _________________________ V

CAL ON (AUTO) = __________________________ V

SYN (AUTO) = _____________________________ V

ALC (AUTO) = V

17

5.0 LIST OF DRAWINGS

1 8

REVISIONS

REV DATE DRAWN BY A P P R V D BY D E S C R IP T IO N

ORAWN BY DATE

DESIGNED BY DATE

APPROVED BY DATEN E X T A S S Y U S E D ON

NATIONAL RADIO ASTRONOMY 03SERVAT0RY

SOCORRO, NEW ME XICO 8 7 8 0 1

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PROJECT

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/I I I 3 Z o 2 2 7 — S)i.c/r>r?\\j££ a m p r c s r /^ /x rc e« - 2 <2>Mc / 3 3 •Cm9 /=■2 &3 - s is s yc ) 33 2 0 5 ; 0 —* - scM ZM ftnc

3 1 S3 *w S I 1 A Pu)Z AtA P JS4 /) J r 7^57" ,-//& £ £ ~ 5c#<CMAr/C

c / 3 3 c 05 i Z a Bs;s&&9/jd 7>&ve(> amp. rc v r ~Sc#&<AArti

A 1 3 3 2 o £a 6 — ALc)PR! 1/6R AMP T£$T r/XT/ZZe <OABL£ - 3 & MB ) 3 a Qp2 5 -

A 1 3 3 o £ z flu,? /!*»*>/SQ UJ && r, CTS93£6' — 75 ga4C / 3 0 2 p 2 7 — - ^ 5-iX

/I ! •2.3 z O£ 3 S c ,V o /re . / - 4 > » t f - B £ M3 / 5 3 2. P 34) ~ s± ss </■............ ...... .... ...................... — .-../r-.....

3 1 3 05 OM0 4 2> /

C 1 3 a 2 0 Al4 2 . s rx o A ir

c 1 3 a 2 V4 5 — F /)/V & . j A ’Z /IR -

USED ON

» «O a

NOTES:

I. GENERAL USE ITEM

assembly NAME ^ - 3 ^ ) & Q S £ - £ A H V ~ D ? ? l U £ ^ SERIES/MOOEL USED ON

DRAWING NO.10 11 12 14 15 16 17 18

REV. T IT L E NOTES

D 3 OtA<t> ) T>~ PI/'} 7 ' <

B / ) # s w w z r . ? & / * * & o r r o / A

M £ a J > / s / z > £ R * & & r e c s

* *O ei

( a )

CON

O

0>

A

\

* NOTES:

I. GENERAL USE ITEM

<i .

6.0 DATA SHEETS

19

DUAL HIGH-FREQUENCY DIFFERENTIAL AMPLIFIERSFor Low-Power Applications at Frequencies up to 500 MHz

Features:• Power Gain 23 dB (typ .) a t 200 M H *

• Nona Figure 4 .6 dB (typ .) a t 200 MHz

• Two diWw a iilia l a w p H ia n on a common in W n ia

• Independently accessible inputs and outputs

• F u ll m ih ta rv - temperature- range capability- ( -5 6 °C to ♦ 12S*C) to r the CA3102E and fo r the CA3049T

CA3049T, CA3102E

c o m b in a t ie m — R F /M in e r/O e e iB e le r :

* The C A 3049 is available in a sealed-junction Beam-Lead version (CA3049L). For further information see File No. 515, "Beam-Lead Devices for Hybrid Circuit Applications".

RCA-CA3049T and CA3102E consist o l tw o independent d iffe ren tia l amplifiers w ith associated constant-current transistors on a common m ono lith ic substrate The sin transistors which comprise the amplifiers are general-purpose deviccs w hich exhib it low l/ f noise and a value o f fT ,n excess o f 1 G H i. These features make the CA3049T and CA3102E usefu l from dc to 500 MHz. Bias and toad resistors have been om itted to provide m aximum application fle x ib ility .

The m onolith ic construction o f the CA3049T and CA3102E provides close electrical and thermal matching o f the am plifiers. This feature makes these deviccs particularly useful in dual-channel applications where matched performance o f the tw o channels is required.

The C A3I02E is like the CA3049T except that i t has a separate substrate connection fo r greater design fle x ib ility . The CA3049T is supplied m the 12-lead TO 5 package: the C A 3I02E . in the 14-lead plastic dual-in-line package.

AppUctOOnt

• VHF amplifiers• VHF rmaan• Multifunction

Converter/IF• IF amplifiers (differential and/or caacode)• Product detector*• Doubly balanced modulators and demodulators• Balanced quadrature detectors• Cascade limiters• Synchronous detectors• Balanced mixers• Synthesizers• Balanced (push-pull) caacode amplifiers• Seme amplifiers

f r f tw i iw c f t i y m tor CA3049T

MAXIMUM RATINGS. ABSOLUTE-MAXIMUM VALUtS. A T T a - 2 ? C

Powar Dissipetion. P:A n y one tra n s is to r............

Tota l package.....................For Ta > 5 5 'C Derate at:

Temperature Rang*:

300

600

6

Operating............................ —55 to ♦ 125

S to rage ............................... - 6 5 to ♦ 160

300 mW

750 mW

6.67 mW/*C

-5 5 to ♦ 125 *C

-6 5 to ♦ 150 *C

Lead Temperature (During Soldering):A t distance 1/16 t 1/32 inch (1 S9 t 0.79mm) from case fo r 10 seconds m ax............................. 265°C

Tha following ratings apply for each transistor in tha devices

Scftanwnc P»»r m » ta r C A JtO tf

Typical Characteristics (o r CA3049T and CA3102E

Col lector-to-Em itter Voltage, V g g ................. 15

CoHector-to-Base Voltage. VCBO ...................... 20

Collcctor-to-Subilra te Voltage V g io * ........... 20

Em itttr-to-Base Voltage. V ^ g g ......................... 5

Collector Current, Iq ............................................ 50

♦TM colector of Mdt hotovtf from (h« mM lu r m lm l M m u d M •utemai ckcuM to M m ioa DHww d trm w o ft and to

tor normal troMlator action.r » m * eumem ( i j . v

4 Iftpu l offtm i ’p»f O w . • w tN r c v /

t i n i o m

fi+ 1-Static Ch*r*cftttuc* Im t c*cm t toe CA3t02€.

L | . L j • A p p ro i 1/? Turn #1 8 T ion td C o o iw W in , V 8 " On.

C |. C j - IS p f V<fi«bt« C JO K ito it IH m um rlu nd . MAC IS . o>

EounKitnll

A ll C *p*citors iM ic u O th c rw w lnd<C4l«d

A ll R fu ito n m O h m U n i« « O tN fw iM IndKOCwt

3-200 MM* cmcodi pommr f M and aom hjurm tmt w w rt

tbm c**0At a wmmr

120

ClECTRICAL CHARACTERISTICS •< TA - 2S*CCA3049T, CA3102E

CH A K ACTCIIISTICS l Y w o a T O T C O N O I n o n >

T t t TO R -CUfT

C A J04T T LIM ITST m C A L CHA*AC»

T tm S T IC S c u n v t t

f t a ftfllM. | TYP. |M A X U N IT S *K L

STATIC C N A M C T C N IS T IC SfM i t c k 0 «t**ro«Ttoi A m eM n«

lN0Mt O t t « l VO<U«l w io 1 ~ a 2« “ mV • 4

InpMl 0 « « t Cu*r«Ml '■ o l 3 • 19 • 2 t a s ~ A *

input I I m C u rrtM 'I I *A ftT«mpo»o<v#« Co«WkWW M « A.twtf* •* In p u t O ttw i v o l t t f l

i4 V ,0 lAT

1 i t - »V /*C 4

(o« {«eit TrtAiiMW0C * I m t » C*Mt«M V o l t t f l « l l

wc l • * V lg • 1 mA - "* 174 - mV •

• m o io - I m m or v g i u f iA V „

ATVc t • • V. IC • 1 m A - > a » - m V /*C •

CftlMclOf CwtoH C u ^ « * t 'C BO < O < O 0 0 0 0 100 «A 7CAWeiOf lo -im itt** |rM h«O w A VOIUM v ISM ICEO IC • 1 mA (S - 0 i t 24 v -

C«H«tO» tO-ftOMv l« n iC S O Ig • 1 0 » A . I f • 0 20 M - V -

C «M (W > t» SuM V IHv l« « IC IO • lO n A . i | • 0. ' ( • 0 20 •0 V ~

to- I m |> m « 4* w aVO<tOfl» v i > n i f * o l{ • *©»*A. tg • 0 ft 7 V "

OVNAMICCHARACTERISTICSI'ff N««w * ifwr* t*Ot

I S<A|l« T >|iv«i|IO« 1 Hr • • to o K H ). * s * nIC . Im A 1 S « • 12

6 » * 8 >«<wiOW» Of S.AftO •t V « • • V *C • ft mA 1 39 - C h 9 11

Co*toe to r Bo m Copocooaco Cc i i c - 0 v c e . ftV

O O

as P*

O* •

Cotiatto* SuD ttf* tt Copocxomco * 0 • c • 0 * c i • * * 1 • » P> ft* 0* ( t e f t 0 >l<wtAt>»i

1 MO0O t>©« Bit*© CM A J 1* ' ' • » 7 ~ A 100 Oft —■ i f c t A#**9O. On* >(•«• AUV 8 • • </ok*90 • 6 V 7 *» * •

Voitov* G*«*V S*A«t» t A4*d A ft** Volt«9* • >4 }V t • (O M N I 3 22 « • ft. 10

1 wMft»o" > m i » C m c * • • 200 Mm , Cow 000 . 3 n oft

11i N f VCC - 12V Cm coo« 3 4 « Oft -

<AOwt A tfA ittin t* • * „

f o» C « k M «

i ? . 19 • 2 mA

C**coo« 1 9 • 1 2 4ft 14. Ift. 1ft

0 -f* A mo 0 » 7 I * | U 1ft. 17. 1ft

k*»w m T ftA fi* ' A«m*tt«MCo V 12

Pp# O.H I m f tilw * C oa*>|u«oiiom

CoK «do O 9 3

" w w-

0.*« A m p 0 • 1 0 0 * 3 -

* W «O d T«OM#Of A tffllltttM * VJ1I - "

<c - ^mA)

Cm c m o 1? ft - 1 30 .1 m m fil 20. 2ft. 30

O '” A mp . 1 0 f t «1 13 - 27. 2ft. 31

Oui0wt A om .tto«e* V2JCowotfo • 0 503 • i 1ft 20. 22. 240»** A m p 0 0 7 * ♦ 1 0 .42 21 . 23. 2ft

UCIITM

-«oo -f» -*o - n o a so n too

Fi§> 7-Cb *k w * tv to M o tf fm f .

fropMowty

10

- 20

»

i>0

tM K K I T f« K 44fUAi(T4 )*n *C "SOWKC * ' " 0 *

J /

7 S

A

------------------------^

Y

l > -

5= + +

I I I I

ux<.c era* a«*c»r tt«i - «* <»>■ 6*<* O*namt0r* on>0oct n co<«rf9 c***n

COllCC'O* C U H I1 ' «»c I*» !« t»0Uf0 ¥* 1

121

CA3049T, CA3102EELECTRICAL CHARACTERISTICS at TA - 26*C

CH AM A C Ti R IST1C3 S V M S O U TC STC O M O ITIO N t

T E fTc ir -c u i t

CAJ103C LIM ITSTYW CALCMAftAC*

T c m t n c tc u * v t s

n o . M IN . MAX. UNITS n o .

STATIC CMAAACTCMISTICSFor (te n Oi<t«rfAti»i Ampiidaf

Inpvt V oiug i v iO » 0 7S S .4

Input 0 « « t Currtftt •iO '3 * 1 * ' Jm A i - 0 3 3 mA

iRVtft I lM Cw»«nt i 13.5 33 <lA SCo«Hlcl»A| M «f

AituM Of Input O ^ IM V o ltt ft■Av,0 i

ATi 1 1 - * v / * c 4

f O' E k a TOC fetm tO • • •» < » 6m .n*f VelU9« V | |

v C i - S V IC • 1 « A I? 4 »»4 • 14 mV •

Volt***i V | (

AT v C f • s v . *c - « mA •0 9 m V /'C 0

Co"*<to« C«t©*« v C i - 10 v I E • 0 0 0 01 3 too a A 7Con*cto 'to fm ilt* i

v (« A ic e o lc - » mA la • 0 IS 24 v

C«i>Kte> < » I m l»M k*M »A VO H«* v ttA IC O O •c • 1 0 MA • ( • 0 20 00 V -

C«ll«Ct«> t« S yM lf*H VOM*9* v t8«>C<0 I f • 10 |»A. I | • 0. <C • 0 20 •0 V -

tm il t v tO-SM* Sr**kOO«wn VOItlfll v i9 *» e a o I f • 1 0 m* . >c 0 S 7 V

OVNAMICCm AA a CTEM iST i CS1/* No>«* * I f o t N* • • 100 « « ) " i * soo n 1 S 00 12

C*<A>liA4w4th ^rOtfuCt 1*0 ' S«n#l« Tr#rt*.**0'» •t wce • • V IC S mA 1 3ft C m , 11

Coi^cto* I m * C*o«c>t*nc* C c * 'c • o v c t . sv as o0 IS

0*p* •

Cftl'KtO' SwO*t'«IO C*0*«'t*AC« «c- IC • 0 v Cl Sv 1 ss o> •tot t*cn

ACC RlAgt. On« &*•«• A «J * • —

• •*« Vo>l»9* * •6V 2 >5 d lVo<t*9*G *>" S<a«I»Ca000 A • •M VOlt*0* •

1 • 10 M H I4 2V 3 I t 22 « • 9. 10

Inw'HOA ►o**r»' G»*« On • • 200 M H | Cmcoo* 3 23 oft*o>«« *+*•• N* VCC . l? v C*«coo« 9 4 1 oo -

*« * Cm c o m CmcoO* 1 S • . 2 45 14. IS. 11V 11 Ij * 1) • 2 * A CM* Am * IS. 17. IS

A*v**«* Tr«A|<«f A om ittlA ti

fo r 0 *«AmoMior C lK O M 0 - (0 0 0 0 ..

v 12 COA(.|W'«(>OA'3 ' '9 * 4mA 0.«» A ~ 0 0 • i 0 013(M t» Cm c o m 17 9 > i 30 7 mm*o 26. 31 30

•c = ?mA) 0»M Amo • 10S • i 13 27 29. 31

y JJCttcoo* • 0S 03 • i IS mmno 20. 22. 24

t»«.t AO U**C 0»«* Amp 0 071 ♦ , 0 « 2 21 23. 3ft

1 ft ««. e> > ft • IC A H O J fl 1 4 D o > < t > IC A J**»T | ••Tw x w tM t l i f t 4. «> * f t • • IC A l lO t t l «0 ft I I O* * ft S IC A M M T I

i M r n n tr t yun c r .

t f t i i c w i « i vaT ic i ivcci - w <n> *»

* * «*•»>»<•» i r l t i a M r w a v M r iW a ^

<* f f j n . coJMcra/ x a e V * • * « * • ^ U - ( i « M < * m i M » | i r t ) l n M > i M ' c i i n « tt- lnpu t nm m tKct ( Y , ft n » « W ira i> n iH

122

CA3049T, CA3102ETypical Output Admittance OunamhtHa for CA304ST and CA3102E

fl$. jO -C v tw r adbi/KMc»

11

: r: i :h .

!u!?<(3 _ o •

ii=i r fnT

iUl : : : : E §"r": # N K ? 3 = p f t =::rr cw trc* (Z )*s 9i< «

oe(M«r«c '•cov£*»c* »»!• ?oo*»«IMMDf TCM»C**'U«t y % 1 » JVC

•il

I**

i t . . .

COlUCTO* $».**.* v o .r«x »w€C)*vm t m «

i ^ J - O v tp v r itfw u w w ( K j j l f t cotbcw* a m V

'•coucacr <m — mm»

f f 2 l- O u lp * t adm tn m e$ n fn m * * ty .

ft$. 71-Output tdmimwnet fY jg l a tm it f r cvfr*H.

Typical Forward Tram far O w ra e ttvM ca lo r CA3049T and CA3102C

^ 22—0*tpvt «dbvWa»MC9 rt ciWKW vflfV vo/isy«i

2S -0U flp*f <d»Wff» x » n wwftwcwfrwut

f«f. X-f0rwm*d #r*wfer ttfm/fWWt r t* )U • >*M

2?~ f onm r* tr»ng*w tdm /ftum (Y^ f) n f t f . 29—f mrwm*& t f m to* >»wift» ic i n mmmmt

J23

GPD-400 SeriesPatented*

Thin Film Amplifier

5 to 400 MHz

MiniatureTransistor

AmplifierFEATURES

• Low Cost

• Cascadable

• Low Profile TO-12 (4-leaded TO-5) Package

• Thin Film Sapphire Construction

• Over 6 Octaves of Amplifier Bandwidth

• Avantek® Silicon Transistor Chips

.009 i_L

Plane V

4 LEADS 019 016

A 1 1

All dimensions in inches

DESCRIPTION

The GPD is a complete transistor am plifier, ready to operate in a m icrostrip c ircu it upon application o f DC voltage. Packaged in-a m iniature TO-12 transistor package, the Avantek® GPD serves as a completely cascadable am plifier, w ithou t bandwidth shrinkage, from 5 to 400 MHz. The low frequency response o f the GPD-460 series may be set arb itra rily low by selection o f external series input and output capacitors, and the DC bypass capacitor.

The Avantek GPD is an entire ly new kind of basic device, designed to provide the c ircu it engineer major savings in both time and money. Various gain and power ou tpu t choices are available to perm it the user to cascade modules to meet the performance characteristics required in his equipment design. Small size, excellent performance, ready availability and substantial cost savings in equipment manufacture and parts handling are significant advantages that can be gained over standard discrete component methods o f manufacture by the use o f GPD amplifiers. The costly and time-consuming problems accompanying in-house am plifier design, construction and testing can be to ta lly avoided by inserting GPD's, either singly or cascaded, in to a system circuit.

The Avantek GPD is a wideband, single-stage un it o f gain, featuring fla t response across its greater-than-six-octave bandwidth. The tin y GPD modular am plifier is made w ith highly reliable ceramic substrates, Avantek microwave transistor chips, th in film circuits, th in film resistors and chip capacitors. A ll the complex c ircu itry is encapsulated inside the tin y TO-12 package. The using engineer is spared the normal frustrating RF design problems — impedance matching networks, feedback loops, biasing and stabilization elements.

APPLICATIONS:

The GPD-400 Series amplifier is designed fo r applications requiring very broadband amplifiers, preamplifiers, isolation am plifiers, and IF am plifiers. The patented circu it design o f the G PD permits cascading o f units to achieve gain up to any desired level w ithou t interstage matching when cascaded in 50-ohm systems. The specified band edges (5 to 400 MHz) are not 3 dB points, but are the points between which the specified gain performance is guaranteed. The low frequency response o f the G P D -460 units may be set as close to DC as required.

* U .S. Patent 3 4 9 3 8 8 2

Avantek, Inc., Advanced solid-state products • 3175 Bowers Avenue, Santa Clara, California 95051 • Phone (408) 249-0700 • TWX 910-339-9274 • Telex 34-6337

G P D -4 0 0 S e rie sIN S TA LLA TIO N A N D O PERATING INSTRUCTIO NS:

Installation of the GPD amplifier is similar to the installation of any standard semi-conductor product in a TO-8 or TO-5 package. A clamp is provided to secure the GPD firm ly to the ground plane. This step insures positive contact between the GPD package and the ground plane so that no problems w ith VSW R or oscillation in a multi-stage system will be encountered.

The GPD amplifier is designed for use in a 50-ohm microstrip system. It can be used in other impedance systems, but performance may be degraded.

The microwave transistor used in the GPD must be protected from current surges which may be generated by energy storage in system capacitances. Always remove bias voltages from the GPD before inserting or removing the unit under test.

The use of a high-pass filte r a n d /o r pad is recommended at th=j cu ip u t o f g3sdischarge-tube noise sources. This protects the transistor in the amplifier from possible high-level ignition-pulse transients which may appear at the RF output ports of these generators (see appropriate manufacturer's literature for further details).

The amplifiers may be stored at temperatures from -65°C to +200°C . The transistors are silicon and all metallization is gold. The operating case temperature is specified at +71°C (+ 160°F ). The amplifiers w ill operate reliably at temperatures through + 125°C (+ 2 5 7 °F) although an external heat sink should be used, particularly on the GPD-403.

More information concerning applications and use of the GPD amplifier is available from Avantek. Write for the Applications Bulletin Designing With GPD Amplifiers.

T Y P IC A L PERFO RM AN CE

GAIN

16

14CD■o

IT 12<O

10

8

GPO-401

GPD-402

GP0 -4QJ

100 200 300 FREQUENCY, MHz

VSWR

400 500

> 1.0

2.01.51.0

.npv/t CD-402 -“-* ~ J

INPUT====db=T--- 1 —G=>0-403---

OUT PUTI


400 500

j 6cc3g 5

S 4z

♦ 18 I +17

*16

BO CL •O Q_- 5 o o

z < e>

♦ 7♦ 6

♦ I 0 -I

NOISE FIGURE

GPD-403

GPD-402

GPD-401

100 200 300 400 FREQUENCY, MHz

OUTPUT POWER

500


400 500

G U A R A N T E E D SPEC IF IC A TIO N S

M o d e l

F»»»OuencvR esoonse

IM H / I

M in im u m

C.d.oM B )

M in im u m I -

I

No»se F M ju.e

M B ) T y p ic a l

R t-v e rwIs o la t io n

(d B )T y p ic a l

P o w e r O u tp u t fo r 1 d B

G a mC o m p re s s io n

IU 8 m )

T y p ic a l

A v a n te k In te r c e p t P o in t to r IM P ro d u c ts

(d B m )

T y p ic a l

V S W R 150 o h m s )

T y p ic a l In O u l

iiV o l ts

O C

r>put P o w e rC u r r e n t ( m A )

T y p ic a l

S to ra q eT e m p e ra tu re

<°C)W e ig h t

(g ram s)

G P O 4 0 1 5 4 0 0 13 1 0 4 6 2 0 2 * 8 2 0 2 0 15 10 6 5 to * 2 0 0 1 0

G P D 4 6 1 S a m e as G P O 4 0 1 . e x c e p t th re e e x te r n a 1 c . tp jc i lo r s a re i«*«|uiire tj to e s ta b lis h lo w lr« '< ju e n cv r o l l o f f

G P D 4 0 2 6 -4 0 0 13 1 0 6 0 20 * 6 ♦ 18 2 0 2 0 15 24 6 5 t o * 2 0 0 1 0

G P D 4 6 2 S a m e as G P D 4 0 2 . p x c e p t th re e e x te rn a l c a p a c ito rs a re re q u ir e d t o e s ta b lis h lo w f re q u e n c y r o l l o f f .

G P D 4 0 3 5 4 0 0 9 1 0 ? 5 ? 0 * IS ♦ 2 6 2 0 2 0 24 0 5 6 5 to * 2 0 0 1 0

G P D 4 6 3 S a m e as G P O 4 0 3 . th re e e x tw <>d« l. t fM O to rS are rp<|u« re d to e s ta b lis h lo w fre q u e n c y r o l l o f f

November 1972 ADS-1020 Printed in U .S.A.

COMMUNICATIONS TRANSISTOR CORPORATIONE1E

F1E

MICROWAVE • CLASS A LINEAR RF POWER TRANSISTORS

GENERAL DESCRIPTION - The E1E & FIE are specifically designed for operation in Class A broadband or narrow-band applications covering the frequency range of 200-3000 MHz'.

FEATURES

• SUPERIOR LINEARITY DUE TO HIGHER f t .• MAXIMUM RELIABILITY DUE TO SINGLE CHIP CONSTRUCTION.• GREATER HIGH FREQUENCY PERFORMANCE IN LOW INDUC

TANCE CERAMIC STRIPLINE PACKAGES.• IDEAL FOR USE IN LINEAR APPLICATIONS REQUIRING OPERA

TION IN CLASS A DUE TO IMPROVED FORWARD BIASED SAFE AREA.

.1851 005

03X45*064056

TT

| 005i 001 - j 0451002J 505U~ 062- 1 022058

060R-\145115

Note: Studless package also available

COMMUNICATIONS TRANSISTOR CORPORATION An A ffilia te of Eimac. Varian301 Industrial Way, San Carlos. C aliforn ia 9 4 0 7 0 (415 ) 591 -8 9 2 1 T W X 9 1 0 -3 7 6 -4 8 9 3

E1E. F1E

Aug. 1973

2.0.8.3D

COMMUNICATIONS TRANSISTOR E1E • FIE

POWER OUTPUT VERSUS FREQUENCY

30

24

EIEVCE=I5V — Ic1120mA

500 WOO

f-FREOUENCY-MHi

1500

4 0

32

24

FIEVC E* ID V -----Ic * 120mA

5 0 0 1000 1500 2 00 0 2 50 0 3000

f-FREQUENCY-MHi

POWER 6AIN VERSUS FREQUENCY

f - FREQUENCY-M H i f-FREQUENCY-MHz

DC SAFE OPERATING AREA

VCE -COLLECTOR TO EMITTER VOLTAGE- VOLTS VCE - COLLECTOR TO EMITTER VOLTAGE-VOLTS

3

COMMUNICATIONS TRANSISTOR E1E #F1E

E1E S11. S22

4

COMMUNICATIONS TRANSISTOR E1E *F 1 E

FIE S11, S22

s

COMMUNICATIONS TRANSISTOR E1E • F I E

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

MAXIMUM TEMPERATURES

Storage Temperatures Operating Junction Temperatures Lead Temperature (Soldering 8 seconds time limit) < 1 /3 2" from Ceramic

MAXIMUM POWER DISSIPATION (Note 2)

Total Power Dissipation at 25° C Case Temperature

MAXIMUM VOLTAGES AND CURRENT

BVCBO Collector to Base Voltagebvebo Emitter to Base VoltageLVCEO Collector to Emitter VoltageIq Collector Current

E1E FIE

-65° C to + 200° C 200° C

-65° C to + 200° C 200° C

260° C 260° C

5.3 W 5.3 W

50 V 4 V

20 V .25 A

50 V 4 V

20 V .25 A

ELECTRICAL CHARACTERISTICS (25° C unless otherwise specified)

SYMBOL CHARACTERISTIC E1E F1E UNIT LIMIT TEST CONDITIONS

100% TESTED AND GUARANTEED

Pg Power Gain (Note 3) 9.0 dB MIN. f = 1 GHz7.0 dB MIN. f = 2 GHz

LVc e o Collector to Emitter Voltage 20 20 VOLTS MIN. Ic = 10 mABVebo Em'tter Base Voltage 4.0 4.0 VOLTS MIN. Ic = 5 mABVc b o Collector to Base Breakdown Voltage 50 50 VOLTS MIN. Ic = 10 mAH fe Current Gain 20 20 — MIN. V c e = 5V, Ic = 50 mA

NOTES:1. At 1 dB compression point.2. These ratings give a maximum junction temperature of 200° C with junction to case thermal resistance of 33° C /w att.3. Values measured at bias point: V^g = 15 Volts, Ic = 120 mA.

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Maximum Voltages and Currents

b v CES Collector to Emitter Voltage ^ E B O Emitter to Base Voltage I c Collector Current

ELECTRICAL CHARACTERISTICS (25°C unless otherwise specified)

50 V 4.0 V 0.5 A

PACKAGE

SYMBOL CHARACTERISTICS MIN. TYP. MAX. UNITS TEST CONDITIONS

P„ 10 sync Power Output .75 0.9 WATTS ^vision = MHzVcc =+25V l c = 200 mA dim = -60 dBc

C P Power Gain 8.0 9.2 dB ^vision — 800 MHz Vcc = +25V I c = 200 mA dim =-60 dBc

^ C Collector Efficiency 18 % f vi si on = 800 MHz Vcc =+25V Ic = 200 mA dim = -60 dBc

0 j C 2 Thermal Resistance 11.0 13.0 °c /w IR ScanJunction to Case Vcc = +25V Ic = 200 mA

h FE DC Current Gain 50 IC = 100 mA v c e = +5v

O O 0D Collector to Base Capacitance

4 pF VCB = +25V|E = 0 f = 1 .0 MHz

b v ebo Emitter to Base 4 VOLTS If = 5 mAVoltage

b v cesCollector to Emitter 50 VOLTS IC =20 mAVoltage

NOTES:

1. European three tone test method: vision carrier -8 dB, sound carrier -7 dB, sideband signal -16 dB. O dB corresponds to peak sync level.

2 . Th is ra tin g g iv e s a m axim um power d is s ip a tio n ra tin g o f 1 5 w a tts a t a m aximum ju nction tem perature o f 2 0 0 °C .

COMMUNICATIONS TRANSISTOR CORPORATION A Subsidiary of Varian Associates301 Industrial Way, San Carlos, C alifo rn ia 94070 (415) 592-9390 TWX 910-376-4893

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C 11 • C 16 W/Ul\ electrolytic Sprague

C 12 ’ C 15 220 pf ceramic chip ATC pkg B

C13 ’ C14 390 pf ceramic chip ATC pkg B

L 1 * L 9 .154” wide line any length

L2 .154” wide line .115” longL3 .154” wide line .785” long

L4 .154” wide line .650” long

L5 .275” wide line .300” long

6 .275” wide line .300” long followed by .154” wide line, .345”

L7 .154” wide line 1.050” long8 .154” wide line .135” long

L 10 4.7 /ih deciductor

L 11 Yj turn #22 wire, I . D. = .150”

L 12 L 13 6 tu rn s #20 w ire on F 627-8Q to ro id

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BOARD MATERIAL = 1/16” teflon fiberglass

7.0 APPENDICES

7.1 Baseband System Specifications (L. R. D'Addario 7/19/78)

Goals:

1. In the complete signal processing, loss of sensitivity

due to non-ideal bypass should be <5%.

2. Closure errors (which result from mismatch between

antennas) should be <1° phase, <1% amplitude.

To achieve this, gain flatness must be better than 4 dB

(pp). I believe we can afford to allocate 1.5 dB of this to

the IF receiver subsystem (including IF Converter), neglecting

any contribution from the filters. In addition, to meet

Goal 2 above, matching between units must be better than 5°

in phase (peak difference) and 0.3 dB in amplitude. Most of

this is already allowed in the filters, but I think we can

allow 2.5° and 0.2 dB in the rest of the subsystem.

Thus we have the following specification for T3, T4, T5

combined, excluding the filters:

For frequencies 0.19 to 50.0 MHz -

1. Gain flatness shall be <1.5 dB peak to peak.

2. Ratio of gains of any two units shall be constant

with frequency to ±0.1 dB (0.2 dB pp).

3. Difference between two units of departures from

linear phase shall not exceed ±2.5°.

20

7.2 Power Amp/Square Law Detector Assembly A3A

(FOR REFERENCE ONLY)

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