Vlsi Design Study Notes12

7/31/2019 Vlsi Design Study Notes12

1/37

VLSI Design Flow

The design process, at various levels, is usually evolutionary in nature. It starts with a given set of

requirements. Initial design is developed and tested against the requirements. When requirements

are not met, the design has to be improved. If such improvement is either not possible or too

costly, then the revision of requirements and its impact analysis must be considered. The Y-chart(first introduced by D. Gajski) shown in Fig. 1.4 illustrates a design flow for most logic chips,

using design activities on three different axes (domains) which resemble the letter Y.

The Y-chart consists of three major domains, namely:


2/37

behavioral domain,

structural domain, geometrical layout domain.

The design flow starts from the algorithm that describes the behavior of the target chip. The

corresponding architecture of the processor is first defined. It is mapped onto the chip surface byfloorplanning. The next design evolution in the behavioral domain defines finite state machines

(FSMs) which are structurally implemented with functional modules such as registers andarithmetic logic units (ALUs). These modules are then geometrically placed onto the chip surface

using CAD tools for automatic module placement followed by routing, with a goal of minimizing

the interconnects area and signal delays. The third evolution starts with a behavioral moduledescription. Individual modules are then implemented with leaf cells. At this stage the chip is

described in terms of logic gates (leaf cells), which can be placed and interconnected by using a

cell placement & routing program. The last evolution involves a detailed Boolean description ofleaf cells followed by a transistor level implementation of leaf cells and mask generation. In

standard-cell based design, leaf cells are already pre-designed and stored in a library for logic

design use.

VLSI DESIGN FLOW


3/37

provides a more simplified view of the VLSI design flow, taking into account the variousrepresentations, or abstractions of design - behavioral, logic, circuit and mask layout. Note that the


4/37

verification of design plays a very important role in every step during this process. The failure to

properly verify a design in its early phases typically causes significant and expensive re-design at a

later stage, which ultimately increases the time-to-market.

Although the design process has been described in linear fashion for simplicity, in reality there are

many iterations back and forth, especially between any two neighboring steps, and occasionallyeven remotely separated pairs. Although top-down design flow provides an excellent design

process control, in reality, there is no truly unidirectional top-down design flow. Both top-downand bottom-up approaches have to be combined. For instance, if a chip designer defined an

architecture without close estimation of the corresponding chip area, then it is very likely that the

resulting chip layout exceeds the area limit of the available technology. In such a case, in order tofit the architecture into the allowable chip area, some functions may have to be removed and the

design process must be repeated. Such changes may require significant modification of the original

requirements. Thus, it is very important to feed forward low-level information to higher levels(bottom up) as early as possible.

IC Design Flow


5/37


6/37

Fig. provides a view of the Very large scale integration (VLSI) design flow based on schematiccapture systems. Although the design process has been described in a linear fashion for simplicity,

in reality there are many iterations back and forth, especially between any two neighboring steps,

and occasionally even remotely separated pairs. Although top-down design flow provides an

excellent design process control, in reality, there is no truly unidirectional top- down design flow.

Both top-down and bottom-up approaches have to be combined. For instance,

if a chip designer defined an architecture without close estimation of the corresponding chip area,

then it is very likely that the resulting chip layout will exceed the area limit of the available

technology. In such a case, in order to fit the architecture into the allowable chip area, some

functions may have to be removed and the design process must be repeated. Such changes may

require significant modification of the initial requirements. Thus, it is very important to feed

forward low-level information to higher levels (bottom up) as early as possible.

Design Specifications

The bottom-up design flow for a transistor-level circuit layout always starts with a set of design

specifications. The "specs" typically describe the expected functionality (Boolean operations) of

the designed block, as well as limits on delay times, silicon area and other properties such as

power dissipation. Usually, the design specifications allow considerable freedom to the circuit

designer on issues concerning the choice of a specific circuit topology, individual placement of

the devices, the locations of input and output pins, and the overall aspect ratio (width-to-height

ratio) of the final design. Note that the limitations spelled out in the initial design specs typically

require certain design trade-offs, such as increasing the dimensions of the transistors in order to

reduce the delay times. It can be seen that one can design a number of different adders (with

different topologies, different maximum delays, different total silicon areas, etc.), all of which

essentially conform to the specs listed above. This indicates that the starting point of a typical

bottom-up design process usually leaves the designer a considerable amount of design freedom.

Schematic Capture

The traditional method for capturing a transistor-level or gate-level design is via a schematic

editor. Schematic editors provide simple, intuitive means to draw, place and connect individual

components that make up a design. The resulting schematic drawing must accurately describe the


7/37

main electrical properties of all components and their interconnections. Also included in the

schematic are the power supply and ground connections, as well as all pins for the input/output

interface of the circuit. This information is crucial for generating the corresponding netlist, which

is used in later stages of the design. The generation of a complete circuit schematic is therefore the

first important step of the transistor-level design flow. Usually, some properties of the components

and/or the interconnections between the devices are subsequently modified as a result of iterative

optimization steps.

Symbol Creation

If a certain circuit design consists of smaller hierarchical components, it is usually very beneficial

to identify such modules early in the design process and to assign each module a correspondingsymbol to represent that circuit. This step greatly simplifies the schematic representation of the

overall system. The symbol view of a circuit module is an icon that represents the collection of all

components within the module. A symbol view of the circuit is also required for some of the

subsequent simulation steps; therefore the schematic capture of the

circuit topology is usually followed by the creation of a symbol to represent the entire circuit.

Simulation

After the transistor-level description of a circuit is completed using the Schematic Editor, the

electrical performance and the functionality of the circuit must be verified using a Simulation 4

tool. The detailed transistor-level simulation of a design will be the first in-depth validation of its

operation, and it is therefore extremely important to complete this step before proceeding to the

subsequent design optimization steps. Based on simulation results, the designer usually modifies

some of the device properties in order to optimize the performance. The initial simulation phase

also serves in detecting possible design errors that may have been created during the schematic

entry step. It is quite common to discover errors such as a missing connection or an extra

connection (an unintended crossing of two signals) in the schematic. The second simulation phase

follows the extraction of a mask layout to accurately assess the electrical performance of

the completed design.

Layout


8/37

The creation of the mask layout is one of the most important steps in the full-custom (bottom-up)

design flow. This is where the designer describes the detailed geometries and the relative

positioning of each mask layer to be used in actual fabrication, using a Layout Editor. Physical

layout design is very tightly linked to overall circuit performance (area, speed and powerdissipation) since the physical structure determines the transconductances of the transistors, the

parasitic capacitances and resistances, and obviously, the silicon area which is used to realize a

certain function. On the other hand, the detailed mask layout of logic gates requires a very

intensive and time-consuming design effort. The physical design of CMOS logic gates is an

iterative process which starts with the circuit topology and the initial sizing of the transistors.

Design Rule Check (DRC)

The created mask layout must conform to a complex set of design rules, in order to ensure a lower

probability of fabrication defects. A tool built into the Layout Editor, called Design Rule Checker,

is used to detect any design rule violations during and after the mask layout design. The designer

must perform DRC, and make sure that all errors are eventually removed from the mask layout,

before the final design is saved.

Circuit Extraction

Circuit extraction is performed after the mask layout design is completed in order to create a

detailed net-list for the simulation tool. The circuit extractor is capable of identifying the

individual transistors and their interconnections as well as the parasitic resistances and

capacitances that are inevitably present between these layers. The extracted net-list can provide a

very accurate estimation of the actual device dimensions and device parasitics that ultimately

determine circuit performance. The extracted net-list file and parameters are subsequently used in

Layout-versus-Schematic comparison and in detailed transistor-level simulations (post-layout

simulation).

Layout versus Schematic (LVS) Check


9/37

After the mask layout design of the circuit is completed, the design should be checked against the

schematic circuit description created earlier. By comparing the original network with the one

extracted from the mask layout the designer can check that the two networks are indeed

equivalent. The LVS step provides an additional level of confidence for the integrity of thedesign, and ensures that the mask layout is a correct realization of the intended circuit topology.

Note that the LVS check only guarantees a topological match. In other words, a successful LVS

will not guarantee that the extracted circuit will actually satisfy the performance requirements.

Any errors that may show up during LVS such as unintended connections between transistors, or

missing connections/devices, etc. should be corrected in the mask layout - before proceeding to

post-layout simulation.

Post-layout Simulation

The electrical performance of a full-custom design can be best analyzed by performing a post-

layout simulation on the extracted circuit net-list. At this point, the designer should have a

complete mask layout of the intended circuit/system, and should have passed the DRC and LVS

steps with no violations. The detailed (transistor-level) simulation performed using the extracted

netlist will provide a clear assessment of the circuit speed, the influence of circuit parasitics such

as parasitic capacitances and resistances, and any glitches that may occur due to signal delay

mismatches. If the results of post-layout simulation are not satisfactory, the designer shouldmodify some of the transistor dimensions and/or the circuit topology, in order to achieve the

desired circuit performance under realistic conditions. This may require multiple iterations on the

design until the post-layout simulation results satisfy the original design requirements. However, a

satisfactory result in post-layout simulation is still no guarantee for a completely successful

product; the actual performance of the chip can only be verified by testing the fabricated

prototype.

Design Hierarchy

The use of hierarchy, or?divide and conquer?technique involves dividing a module into sub-

modules and then repeating this operation on the sub-modules until the complexity of the smaller

parts becomes manageable. This approach is very similar to the software case where large

programs are split into smaller and smaller sections until simple subroutines, with well-defined


10/37

functions and interfaces, can be written. In Section 1.2, we have seen that the design of a VLSI

chip can be represented in three domains. Correspondingly, a hierarchy structure can be described

in each domain separately. However, it is important for the simplicity of design that the hierarchiesin different domains can be mapped into each other easily.

As an example of structural hierarchy, Fig. 1.6 shows the structural decomposition of a CMOSfour-bit adder into its components. The adder can be decomposed progressively into one- bit

adders, separate carry and sum circuits, and finally, into individual logic gates. At this lower levelof the hierarchy, the design of a simple circuit realizing a well-defined Boolean function is much

more easier to handle than at the higher levels of the hierarchy.

In the physical domain, partitioning a complex system into its various functional blocks willprovide a valuable guidance for the actual realization of these blocks on chip. Obviously, the

approximate shape and size (area) of each sub-module should be estimated in order to provide a

useful floorplan. Figure 1.7 shows the hierarchical decomposition of a four-bit adder in physical

description (geometrical layout) domain, resulting in a simple floorplan. This physical view

describes the external geometry of the adder, the locations of input and output pins, and how pinlocations allow some signals (in this case the carry signals) to be transferred from one sub-block to

the other without external routing. At lower levels of the physical hierarchy, the internal mask


11/37

Figure- 1.6 Structural decomposition of a four-bit adder circuit, showing the hierarchy down to

gate level.

Figure-:1.7 Hierarchical decomposition of a four-bit adder in physical (geometrical) description

domain.


12/37

Figure 1.8 : Layout of a 16-bit adder, and the components (sub-blocks) of its physical hierarchy.


13/37

Figure: 1.9 The structural hierarchy of a triangle generator chip.


14/37

Figure-:1.10 Physical layout of the triangle generator chip.

layout of each adder cell defines the locations and the connections of each transistor and wire.

Figure 1.8 shows the full-custom layout of a 16-bit dynamic CMOS adder, and the sub-modules

that describe the lower levels of its physical hierarchy. Here, the 16-bit adder consists of a cascadeconnection of four 4-bit adders, and each 4-bit adder can again be decomposed into its functional

blocks such as the Manchester chain, carry/propagate circuits and the output buffers. Finally, Fig.

1.9 and Fig. 1.10 show the structural hierarchy and the physical layout of a simple trianglegenerator chip, respectively. Note that there is a corresponding physical description for every

module in the structural hierarchy, i.e., the components of the physical view closely match thisstructural view.


15/37

Concepts of Regularity, Modularity and Locality

The hierarchical design approach reduces the design complexity by dividing the large system into

several sub-modules. Usually, other design concepts and design approaches are also needed tosimplify the process. Regularity means that the hierarchical decomposition of a large system

should result in not only simple, but also similar blocks, as much as possible. A good example ofregularity is the design of array structures consisting of identical cells - such as a parallel

multiplication array. Regularity can exist at all levels of abstraction: At the transistor level,uniformly sized transistors simplify the design. At the logic level, identical gate structures can be

used, etc. Figure 1.11 shows regular circuit-level designs of a 2-1 MUX (multiplexer), an D-type

edge-triggered flip flop, and a one-bit full adder. Note that all of these circuits were designed byusing inverters and tri-state buffers only. If the designer has a small library of well-defined and

well-characterized basic building blocks, a number of different functions can be constructed by

using this principle. Regularity usually reduces the number of different modules that need to bedesigned and verified, at all levels of abstraction.

Regular design of a 2-1 MUX, a DFF and an adder, using inverters and tri-state buffers.


16/37

Modularity in design means that the various functional blocks which make up the larger system

must have well-defined functions and interfaces. Modularity allows that each block or module can

be designed relatively independently from each other, since there is no ambiguity about thefunction and the signal interface of these blocks. All of the blocks can be combined with ease at the

end of the design process, to form the large system. The concept of modularity enables the

parallelisation of the design process. It also allows the use of generic modules in various designs -the well-defined functionality and signal interface allow plug-and-play design.

By defining well-characterized interfaces for each module in the system, we effectively ensure that

the internals of each module become unimportant to the exterior modules. Internal details remain at

the local level. The concept of locality also ensures that connections are mostly betweenneighboring modules, avoiding long-distance connections as much as possible. This last point is

extremely important for avoiding excessive interconnect delays. Time-critical operations should be

performed locally, without the need to access distant modules or signals. If necessary, thereplication of some logic may solve this problem in large system architectures.


17/37

Introduction to CAD tools

A CAD system usually includes the following

tools Design entry

Synthesis and optimization

Simulation Physical design

Design entry

The process of entering into the CAD system a description of a circuit being designed is

called design entry Three common design entry methods

Using truth tables User enters a truth table in plain text format or draws a waveform that represents the desired

functional behavior

Schematic capture

User graphically enters a desired logic circuit

Hardware description languages User enters a programming language-like description of a desired logic circuit

Electrical Design entry with truth tables

Commonly use a waveform editorto enter a timing diagram that describes a desired functionality

for a logic circuit

CAD system transforms this into equivalent logic gates Not appropriate for large circuits, but can be used for a small logic function that is to be part of a

larger circuit

Schematic capture

Most common type of CAD tool

Schematic: refers to a diagram of a circuit in which circuit elements (logic gates) are shown as

graphical symbols and connections between them are drawn as lines.

Tool provides a collection of symbols that represent gates of various types with different inputs

and outputs. A library. Previously designed circuits can be represented with a graphical symbol and used in larger

circuits. Known as hierarchical design and provides a way of dealing with complexities of large

circuits


18/37

Hardware description languages

A hardware description language (HDL) is similar to a computer program except that itis used to describe hardware

Common HDLs VHDL (VHSIC Hardware Description Language)

Verilog Many others (vendor specific)

VHDL and Verilog are standards Offer portability across different CAD tools and different types of programmable

Synthesis

Synthesis CAD tools perform the process of generating a logic circuit from some stated

functional behavior

Translating(compiling) VHDL code into a network of logic gates is a part of synthesis Not only will the CAD tool produce a logic circuit, but it can also optimize that circuit

In terms of speed and/or size (logic optimization)

Called logic synthesis orlogic optimization Finally, technology mappingand layout synthesis (physical design) complete the synthesisprocess

Simulation

Once designed, it is necessary to verify that the design circuit functions as expected

In afunctional simulation the user specifies valuations of the circuits inputs and the CAD tool

generates the outputs (commonly in the form of a timing diagram)

User verifies generated outputs against expected outputs Functional simulators assume the time needed for signals to propagate through the logic gates is

negligible For a real implementation this is not sufficient Use a timing simulatorto obtain accurate (complete) simulation

CAD Tools at Various Levels of Design Hierarchy


19/37

CAD TOOLS


20/37

CAD Tools Classification : Interaction-Based

Front-end Tools :

Design Entry, Editors, Simulation, Synthesis, Timing Analysis, DFT Insertion,Test Generation, . . .

Back-end Tools :

Floor Planning, Place-and-Route, Extraction, LVS (Layout vs. Schematic),LVL (Layout vs. Logic), ERC, DRC, Pattern Generators, Format Converters,Mask Graphics, . . .

CAD Tools Classification : Function-Based

Design Capture Tools :

Editors, VHDL, SystemVerilog, SystemC, State Charts, FSM Capture, . . .

Synthesis Tools :

Behavioral Synthesis, RTL Synthesis, FPGA Synthesis, Logic Synthesis,Physical Synthesis, Module/Cell Generators (ROM, PLA, RAM), Data-pathCompiler, Adder/Multiplier Generators, DSP Synthesis, . . .

Analysis Tools :

Checkers : DRC, ERC, Net Compare, Ratio Checker, Short-circuit Checker,Fan-in / Fan-out Checker, Power Checker, . . .

Verifiers : Timing Verifier, Simulators, ICE/Hardware Simulators, FormalVerifier, . . .

Testing Related Tools :

ATPG, DFT Tools, . .

Design Methodologies and CAD Tools : First Epoch (1959-1979)

Full-custom design methodology.

Layout level tools, Circuit level tools.

Technology at SSI, MSI, LSI levels.

Designer, User and Tools Developer all at a single company (monolithic).


21/37

Productivity of designer (notionally) = 10 transistors/day

Design Methodologies and CAD Tools : Second Epoch (1980-1989)

Standard-Cell / Gate-Array / ASIC design methodology. Shorter synthe-sis/analysis loop.

Logic level tools, Macro generators, Module compilers.

Technology at LSI, VLSI levels.

User/Designer separated from Tools Developer i.e. separate companiesselling tools come into being.

Productivity of designer (notionally) = 10 gates/day.

Design Methodologies and CAD Tools : Third Epoch (1990-1999)

HDL-based design methodology. FPGA-based prototyping. Designexploration made easier, Estimators for performance become available.

RT-level synthesis, Preliminary Behavioural synthesis tools; HDL-baseddesign entry, HDL Code analyzers/advisers.

Technology at VLSI levels. Deep-submicron (DSM) issues.

User, Designer and Tools Developer become separate groups/companies.Fabless companies.

CAD tools move towards PC platforms.

Productivity of designer (notionally) = 10 lines of VHDL code/day.

Design Methodologies and CAD Tools : Third Epoch (1990-1999)

Low-power gains importance. Mixed-signal design issues.

Tools for designing MEMS and Embedded systems appear.

Intellectual Property, Design Re-use, Reconfigurable Computing, Cores, ASIP,

ASSP, DSP, . . .

Design Methodologies and CAD Tools : Fourth Epoch (2000-. . . )

System-on-Chip design methodology. Block-level chip design (using cores,IP blocks).


22/37

System-level synthesis, MEMS design tools. Mixed-signal design tools.

Consolidation among EDA companies.

Technology at VLSI, ULSI levels. Deep-submicron (DSM) and power-leakageissues. Copper metallization, new dielectric materials, new devicestructures.

Productivity of designer (notionally) = 10 lines of specification code/day


23/37

GDSII stream format, common acronym GDSII, is a database file format which is the de facto

industry standard for data exchange of integrated circuit or IC layout artwork. It is a binary fileformat representing planar geometric shapes, text labels, and other information about the layout in

hierarchical form. The data can be used to reconstruct all or part of the artwork to be used in

sharing layouts, transferring artwork between different tools, or creating photomasks.

Initially, GDSII was designed as a format used to control integrated circuit photomask plotting.Despite its limited set of features and low data density, it became the industry conventional format

for transfer of IC layout data between design tools of different vendors, all of which operated with

proprietary data formats.

It was originally developed by Calma for its layout design software, "Graphic Data System"

("GDS") and "GDSII". Now the format is owned by Cadence Design Systems.

GDS II files are usually the final output product of the IC design cycle and are given to IC

foundries for IC fabrication. GDS II files were originally placed on magnetic tapes. This momentwas fittingly called tape out though it is not the original root of the term.

Objects contained in a GDSII file are grouped by assigning numeric attributes to them including a

"layer number", "datatype" or "texttype". While these attributes were designed to correspond to the

"layers of material" used in manufacturing an integrated circuit, their meaning rapidly becamemore abstract to reflect the way that the physical layout is designed.

In the design of integrated circuits, the most popular format for interchange is the Calma GDS IIstream format (GDS II is a trademark of Calma Company, a wholly owned subsidiary of General

Electric Company, U.S.A.). For many years, this format was the only one of its kind and manyother vendors accepted it in their systems. Although Calma has updated the format as their CAD

systems have developed, they have maintained backward compatibility so that no GDS II files

become obsolete. This is important because GDS II is a binary format that makes assumptionsabout integer and floating-point representations.

A GDS II circuit description is a collection of cells that may contain geometry or other cell

references. These cells, called structures in GDS II parlance, have alphanumeric names up to 32

characters long. A library of these structures is contained in a file that consists of a library header,

a sequence of structures, and a library tail. Each structure in the sequence consists of a structureheader, a sequence ofelements, and a structure tail. There are seven kinds of elements: boundarydefines a filled polygon, path defines a wire, structure reference invokes a subcell, array

reference invokes an array of subcells, text is for documentation, node defines an electrical path,and box places rectangular geometry.

Record Format


24/37

In order to understand the precise format of the above GDS II components, it is first necessary to

describe the general record format. Each GDS II record has a 4-byte header that specifies the

record size and function. The first 2 bytes form a 16-bit integer that contains the record length inbytes. This length includes the 4-byte header and must always be an even number. The end of a

record can contain a single null byte if the record contents is an odd number of bytes long. The

third byte of the header contains the type of the record and the fourth byte contains the type of thedata. Since the data type is constant for each record type, this 2-byte field defines the possible

records as shown in Figs. C.1 and C.2.

File Header Records: Bytes 3 and 4 Parameter Type

HEADER 0002 2-byte integer

BGNLIB 0102 12 2-byte integers

LIBNAME 0206 ASCII string

REFLIBS 1F06 2 45-character ASCII strings

FONTS 2006 4 44-character ASCII strings

ATTRTABLE 2306 44-character ASCII stringGENERATIONS 2202 2-byte integer

FORMAT 3602 2-byte integer

MASK 3706 ASCII string

ENDMASKS 3800 No data

UNITS 0305 2 8-byte floats

File Tail Records: Bytes 3 and 4 Parameter Type

ENDLIB 0400 No data

Structure Header Records: Bytes 3 and 4 Parameter Type

BGNSTR 0502 12 2-byte integers

STRNAME 0606 Up to 32-characters ASCII string

Structure Tail Records: Bytes 3 and 4 Parameter Type

ENDSTR 0700 No data

FIGURE C.1 GDS II header record types.

Magnetic tapes containing GDS II files will have 2048 byte blocks that contain these records. The

block size is standardized but has no bearing on record length or position. There is also a capabilityfor circuits that require multiple reels of tape.

Element Header Records: Bytes 3 and 4 Parameter Type

BOUNDARY 0800 No data

PATH 0900 No data

SREF 0A00 No data


25/37

AREF 0B00 No data

TEXT 0C00 No data

NODE 1500 No data

BOX 2D00 No data

Element Contents Records: Bytes 3 and 4 Parameter Type

ELFLAGS 2601 2-byte integer

PLEX 2F03 4-byte integer

LAYER 0D02 2-byte integers

DATATYPE 0E02 2-byte integer

XY 1003 Up to 200 4-byte integer pairs

PATHTYPE 2102 2-byte integer

WIDTH 0F03 4-byte integer

SNAME 1206 Up to 32-character ASCII string

STRANS 1A01 2-byte integer MAG 1B05 8-byte float

ANGLE 1C05 8-byte float

COLROW 1302 2 2-byte integers

TEXTTYPE 1602 2-byte integer

PRESENTATION 1701 2-byte integer

ASCII STRING 1906 Up to 512-character string

NODETYPE 2A02 2-byte integer

BOXTYPE 2E02 2-byte integer

FIGURE C.2 GDS II element record types.

Library Head and Tail

A GDS II file header always begins with a HEADER record the parameter of which contains the

GDS II version number used to write the file. For example, the bytes 0, 6, 0, 2, 0, 1 at the start of

the file constitute the header record for a version-1 file. Following the HEADER comes a BGNLIB

record that contains the date of the last modification and the date of the last access to the file. Datestake six 2-byte integers to store the year, month, day, hour, minute, and second. The third record of

a file is the LIBNAME, which identifies the name of this library file. For example, the bytes 0, 8,

2, 6, "C", "H", "I", "P" define a library named "CHIP." Following the LIBNAME record there maybe any of the optional header records: REFLIBS to name up to two reference libraries, FONTS to

name up to four character fonts, ATTRTABLE to name an attribute file, GENERATIONS to

indicate the number of old file copies to keep, and FORMAT to indicate the nature of this file. Thestrings in the REFLIBS, FONTS, and ATTRTABLE records must be the specified length, padded

with zero bytes.

The parameter to FORMAT has the value 0 for an archived file and the value 1 for a filtered file.

Filtered files contain only a subset of the mask layers and that subset is described with one or more


26/37

MASK records followed by an ENDMASK record. The string parameter in a MASK record names

layers and sequences of layers; for example, "1 3 5-7."

The final record of a file header is the UNITS record and it is not optional. The parameters to thisrecord contain the number of user units per database unit (typically less than 1 to allow granularity

of user specification) and the number of meters per database unit (typically much less than 1 for ICspecifications).

Eight-byte floating-point numbers have a sign at the top of the first byte, a 7-bit exponent in therest of that byte, and 7 more bytes that compose a mantissa (all to the right of an implied decimal

point). The exponent is a factor of 16 in excess-64 notation (that is, the mantissa is multiplied by

16 raised to the true value of the exponent, where the true value is its integer representation minus64).

Following the file header records come the structure records. After the last structure has been

defined, the file terminates with a simple ENDLIB record. Note that there is no provision for the

specification of a root structure to define a circuit; this must be tracked by the designer.

Structure Head and Tail

Each structure has two header records and one tail record that sandwich an arbitrary list of

elements. The first structure header is the BGNSTR record, which contains the creation date and

the last modification date. Following that is the STRNAME record, which names the structureusing any alphabetic or numeric characters, the dollar sign, or the underscore. The structure is then

open and any of the seven elements can be listed.

The last record of a structure is the ENDSTR. Following it must be another BGNSTR or the end of

the library, ENDLIB.

Boundary Element

The boundary element defines a filled polygon. It begins with a BOUNDARY record, has an

optional ELFLAGS and PLEX record, and then has required LAYER, DATATYPE, and XY

records.

The ELFLAGS record, which appears optionally in every element, has two flags in its parameter toindicate template data (if bit 16 is set) or external data (if bit 15 is set). Thisrecord should be

ignored on input and excluded from output. Note that the GDS II integer has bit 1 in the leftmost ormost significant position so these two flags are in the least significant bits.

The PLEX record is also optional to every element and defines element structuring by aggregating

those that have common plex numbers. Although a 4-byte integer is available for plex numbering,

the high byte (first byte) is a flag that indicates the head of the plex if its least significant bit (bit 8)

is set.


27/37

The LAYER record is required to define which layer (numbered 0 to 63) is to be used for this

boundary. The meaning of these layers is not defined rigorously and must be determined for each

design environment and library.

The DATATYPE record contains unimportant information and its argument should be zero.

The XY record contains anywhere from four to 200 coordinate pairs that define the outline of the

polygon. The number of points in this record is defined by the record length. Note that boundaries

must be closed explicitly, so the first and last coordinate values must be the same.

Path Element

A path is an open figure with a nonzero width that is typically used to place wires. This element is

initiated with a PATH record followed by the optional ELFLAGS and PLEX records. The LAYER

record must follow to identify the desired path material. Also, a DATATYPE record must appearand an XY record to define the coordinates of the path. From two to 200 points may be given in a

path.

Prior to the XY record of a path specification there may be two optional records called

PATHTYPE and WIDTH. The PATHTYPE record describes the nature of the path segment ends,according to its parameter value. If the value is 0, the segments will have square ends that

terminate at the path vertices. The value 1 indicates rounded ends and the value 2 indicates square

ends that overlap their vertices by one-half of their width. The width of the path is defined by theoptional WIDTH record. If the width value is negative, then it will be independent of any structure

scaling (from MAG records, see next section).

Structure Reference ElementHierarchy is achieved by allowing structure references (instances) to appear in other structures.The SREF record indicates a structure reference and is followed by the optional ELFLAGS and

PLEX records. The SNAME record then names the desired structure and an XY record contains a

single coordinate to place this instance. It is legal to make reference to structures that have not yetbeen defined with STRNAME

Prior to the XY record there may be optional transformation records. The STRANS record must

appear first if structure transformations are desired. Its parameter has bit flags that indicate

mirroring inx before rotation (if bit 1 is set), the use of absolute magnification (if bit 14 is set), and

the use of absolute rotation (if bit 15 is set). The magnification and rotation amounts may then bespecified in the optional MAG and ANGLE records. The rotation angle is in counterclockwise

degrees

Array of Structures Element

For convenience, an array of structure instances can be specified with the AREF record. Following

the optional ELFLAGS and PLEX records comes the SNAME to identify the structure being


28/37

arrayed. Next, the optional transformation records STRANS, MAG, and ANGLE give the

orientation of the instances. A COLROW record must follow to specify the number of columns

and the number of rows in the array. The final record is an XY with three points: the coordinate ofthe corner instance, the coordinate of the last instance in the columnar direction, and the coordinate

of the last instance in the row direction. From this information, the amount of instance overlap or

separation can be determined. Note that flipping arrays (in which alternating rows or columns aremirrored to abut along the same side) can be implemented with multiple arrays that are interlaced

and spaced apart to describe alternating rows or columns.

Text Element

Messages can be included in a circuit with the TEXT record. The optional ELFLAGS and PLEX

follow with the mandatory LAYER record after that. A TEXTTYPE record with a zero argument

must then appear. An optional PRESENTATION record specifies the font in bits 11 and 12, the

vertical presentation in bits 13 and 14 (0 for top, 1 for middle, 2 for bottom), and the horizontalpresentation in bits 15 and 16 (0 for left, 1 for center, 2 for right). Optional PATHTYPE, WIDTH,

STRANS, MAG, and ANGLE records may appear to affect the text. The last two records are

required: an XY with a single coordinate to locate the text and a STRING record to specify theactual text.

Node Element

Electrical nets may be specified with the NODE record. The optional ELFLAGS and PLEX

records follow and the required LAYER record is next. A NODETYPE record must appear with a

zero argument, followed by an XY record with one to 50 points that identify coordinates on theelectrical net. The information in this element is not graphical and does not affect the manufactured

circuit. Rather, it is for other CAD systems that use topological information.

Box Element

The last element of a GDS II file is the box. Following the BOX record are the optional ELFLAGSand PLEX records, a mandatory LAYER record, a BOXTYPE record with a zero argument, and an

XY record. The XY must contain five points that describe a closed, four-sided box. Unlike the

boundary, this is not a filled figure. Therefore it cannot be used for IC geometry.

Standard Cell Libraries


29/37

Standard cell libraries are required by almost all CAD tools for chip design Standard cell libraries

contain primitive cells required for digital design However, more complex cells that have been

specially optimized can also be included.

The main purpose of the CAD tools is to implement the so called RTL-to-GDS flow The input to

the design process, in most cases, is the circuit description at the register- transfer level (RTL) Thefinal output from the design process is the full chip layout, mostly in the GDSII (gds2) format To

produce a functionally correct design that meets all the specifications and constraints, requires acombination of different tools in the design flows These tools require specific information in

different formats for each of the cells in the standard cell library provided to them for the design

Library-Cell Design

The optimum cell layout for each process generation changes because the

design rules for each ASIC vendors process are always slightly different

even for the same generation of technology. For example, two companies may

have very similar 0.35 m CMOS process technologies, but the third-level

metal spacing might be slightly different. If a cell library is to be used with

both processes, we could construct the library by adopting the most stringent

rules from each process. A library constructed in this fashion may not be

competitive with one that is constructed specifically for each process. Even

though ASIC vendors prize their design rules as secret, it turns out that they

are similarexcept for a few details. Unfortunately, it is the details that stop usmoving designs from one process to another. Unless we are a very large

customer it is difficult to have an ASIC vendor change or waive design rules

for us. We would like all vendors to agree on a common set of design rules.

This is, in fact, easier than it sounds. The reason that most vendors have similar

rules is because most vendors use the same manufacturing equipment and a

similar process. It is possible to construct a highest common denominator

library that extracts the most from the current manufacturing capability. Some

library companies and the large Japanese ASIC vendors are adopting this

approach.

Layout of library cells is either hand-crafted or uses some form ofsymbolic

layout . Symbolic layout is usually performed in one of two ways: using either


30/37

interactive graphics or a text layout language. Shapes are represented by

simple lines or rectangles, known as sticks or logs , in symbolic layout. The

actual dimensions of the sticks or logs are determined after layout is completed

in a postprocessing step. An alternative to graphical symbolic layout uses a text

layout language, similar to a programming language such as C, that directs a

program to assemble layout. The spacing and dimensions of the layout shapes

are defined in terms of variables rather than constants. These variables can be

changed after symbolic layout is complete to adjust the layout spacing to a

specific process.

Mapping symbolic layout to a specific process technology uses 1020

percent more area than hand-crafted layout (though this can then be further

reduced to 510 percent with compaction). Most symbolic layout systems do

not allow 45 layout and this introduces a further area penalty (my experience

shows this is about 515 percent). As libraries get larger, and the capability to

quickly move libraries and ASIC designs between different generations of

process technologies becomes more important, the advantages of symbolic

layout may outweigh the disadvantages.

Library Architecture

Figure 3.13 (a) shows cell use data from over 150 CMOS gate array designs.

These results are remarkably similar to that from other ASIC designs using

different libraries and different technologies and show that typically

80 percent of an ASIC uses less than 20 percent of the cell library.
http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.5.htm#28051http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.5.htm#28051


31/37

FIGURE 3.13 Cell library statistics

We can use the data in Figure 3.13 (a) to derive some useful conclusions

about the number and types of cells to be included in a library. Before we do

this, a few words of caution are in order. First, the data shown in Figure 3.13

(a) tells us about cells that are included a library. This data cannot tell us

anything about cells that are not (and perhaps should be) included in a library.

Second, the type of design entry we useand the type of ASIC we are

designingcan dramatically affect the profile of the use of different cell types.

For example, if we use a high-level design language, together with logic

synthesis, to enter an ASIC design, this will favor the use of the complex
http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.5.htm#28051http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.5.htm#28051http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.5.htm#28051http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.5.htm#28051


32/37

combinational cells (cells of the AOI family that are particularly area efficient

in CMOS, but are difficult to work with when we design by hand).

Figure 3.13 (a) tells us which cells we use most often, but does not take into

account the cell area. What we really want to know are which cells are most

important in determining the area of an ASIC. Figure 3.13 (b) shows the area of

the cellsnormalized to the area of a minimum-size inverter. If we take the

data in Figure 3.13 (a) and multiply by the cell areas, we can derive a new

measure of the contribution of each cell in a library (Figure 3.13c). This new

measure, cell importance , is a measure of how much area each cell in a library

contributes to a typical ASIC. For example, we can see from Figure 3.13 (c) that

a D flip-flop (with a cell importance of 3.5) contributes 3.5 times as much areaon a typical ASIC than does an inverter (with a cell importance of 1)

Figure 3.13 (c) shows cell importance ordered by the cell frequency of use

and normalized to an inverter. We can rearrange this data in terms of cell

importance, as shown in Figure 3.13 (d), and normalized so that now the most

important cell, a D flip-flop, has a cell importance of 1. Figure 3.13 (e)

includes the cell use data on the same scale as the cell importance data. Both

show roughly the same shape, reflecting that both measures obey an 8020rule. Roughly 20 percent of the cells in a library correspond to 80 percent of

the ASIC area and 80 percent of the cells we use (but not the same 20 percent

that is why cell importance is useful).

Figure 3.13 (e) shows us that the most important cells, measured by their

contribution to the area of an ASIC, are not necessarily the cells that we use

most often. If we wish to build or buy a dense library, we must concentrate on

the area of those cells that have the highest cell importancenot the most

common cells.

Standard-Cell Design

Figure 3.19 shows the components of the standard cell from Figure 1.3. Each

standard cell in a library is rectangular with the same height but different
http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.5.htm#28051http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.5.htm#28051http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.5.htm#28051http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.5.htm#28051http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.5.htm#28051http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.5.htm#28051http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.5.htm#28051http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.5.htm#28051http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.7.htm#15737http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.5.htm#28051http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.5.htm#28051http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.5.htm#28051http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.5.htm#28051http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.5.htm#28051http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.5.htm#28051http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.5.htm#28051http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.5.htm#28051http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.7.htm#15737


33/37

widths. The bounding box ( BB ) of a logic cell is the smallest rectangle that

encloses all of the geometry of the cell. The cell BB is normally determined by

the well layers. Cell connectors or terminals (the logical connectors ) must be

placed on the cell abutment box ( AB ). The physical connector (the piece ofmetal to which we connect wires) must normally overlap the abutment box

slightly, usually by at least 1 , to assure connection without leaving a tiny

space between the ends of two wires. The standard cells are constructed so

they can all be placed next to each other horizontally with the cell ABs

touching (we abut two cells).


34/37

FIGURE 3.19 (a) The standard cell shown in Figure 1.3. (b) Diffusion,

poly, and contact layers. (c) m1 and contact layers. (d) The equivalent

schematic.

A standard cell (a D flip-flop with clear) is shown in Figure 3.20 and

illustrates the following features of standard-cell layout:

FIGURE 3.20 A D flip-flop standard cell. The wide power buses and

transistors show this is a performance-optimized cell. This double-entry

cell is intended for a two-level metal process and channel routing. The
http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.7.htm#10967http://iroi.seu.edu.cn/books/asics/Book2/CH03/CH03.7.htm#10967


35/37

five connectors run vertically through the cell on m2 (the extra short

vertical metal line is an internal crossover).

Layout using 45 angles. This can save 10%20% in area compared to acell that uses only Manhattan or 90 geometry. Some ASIC vendors do not

allow transistors with 45 angles; others do not allow 45 angles at all. Connectors are at the top and bottom of the cell on m2 on a routing grid

equal to the vertical (m2) track spacing. This is a double-entry cell intendedfor a two-level metal process. A standard cell designed for a three-level

metal process has connectors in the center of the cell. Transistor sizes vary to optimize the area and performance but maintain a

fixed ratio to balance rise times and fall times.

The cell height is 64 (all cells in the library are the same height) with a

horizontal (m1) track spacing of 8 . This is close to the minimum heightthat can accommodate the most complex cells in a library.

The power rails are placed at the top and bottom, maintaining a certainwidth inside the cell and abut with the power rails in adjacent cells.

The well contacts (substrate connections) are placed inside the cell at

regular intervals. Additional well contacts may be placed in spacers

between cells. In this case both wells are drawn. Some libraries minimize the well or moat

area to reduce leakage and parasitic capacitance. Most commercial standard cells use m1 for the power rails, m1 for internal

connections, and avoid using m2 where possible except for cell connectors.

When a library developer creates a gate-array, standard-cell, or datapath

library, there is a trade-off between using wide, high-drive transistors that

result in large cells with high-speed performance and using smaller

transistors that result in smaller cells that consume less power. A

performance-optimized library with large cells might be used for

ASICs in a high-performance workstation, for example. An area-

optimized library might be used in an ASIC for a battery-powered

portable computer.


36/37

Standard Cell Library Formats

The formats explained here are for Cadence tools, howerver similar information

is required for other tool suites.

Physical Layout (gdsII, Virtuoso Layout Editor)

Should follow specific design standards eg. constant height, offsets etc.

Logical View (verilog description or TLF or LIB)

Verilog is required for dynamic simulation. Place and route tools usually can

use TLF.

Verilog description should preferably support back annotation of timinginformation.

Abstract View (Cadence Abstract Generator, LEF)

LEF: Contains information about each cell as well as technology information

Timing, power and parasitics (TLF or LIB)

Transistor and interconnect parasitics are extracted using Cadence or other

extraction tools.

Spice or Spectre netlist is generated and detailed timing simulations are

performed.

Power information can also be generated during these simulations.

Data is formatted into a TLF or LIB file including process, temperature and

supply voltage variations.

Logical information for each cell is also contained in this file.

Standard Cell Design


37/37

Date post:	05-Apr-2018
Category:	Documents
Upload:	gpuonline
View:	220 times
Download:	0 times

Vlsi Design Study Notes12

Documents