EE141
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EE1411
Tu-Th 9:30-11am203 McLaughlin
EE141- Fall 2001Introduction to Digital
Integrated Circuits
EE1412
What is this class about?
� Introduction to digital integrated circuits.» CMOS devices and manufacturing technology.
CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Sequential circuits. Arithmetic, interconnect, and memories. Programmable logic arrays. Design methodologies.
� What will you learn?» Understanding, designing, and optimizing digital
circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability
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Practical Information
� Instructor» Prof. Borivoje Nikolic
570 Cory Hall, 643-9297, [email protected] hours: Mo 10:30-12am, Th 11-12pm
� TAs:» Joshua Garrett» Hangching Fuh, [email protected]» Kevin Cao, [email protected] hours: 353 Cory
� Web page: http://bwrc.eecs.berkeley.edu/Classes/ICDesign/EE141_f01/
EE1414
Discussions and Labs
� Discussion sessions» W 2-3pm, 285 Cory » Tu 2-3pm, 293 Cory Cancelled!» F 9-10am, 409 Davis
� Labs (353 Cory)» Tu 2-5pm -> 3:30-6:30pm» F 11-2pm» W 11-2pm» Th 3-6pm -> 3:30-6:30pm» W 5-8pm
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Class Organization
� 10 Assignments� One design project with three phases� Labs: 6 software, 1 hardware� 2 midterms, 1 final
» Midterm 1: Thursday, October 4, evening » Midterm 2: Thursday, November 8, evening» Final: TBA
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Grading Policy
� Homeworks: 10%� Labs: 10%� Projects: 20%� Midterms: 30%� Final: 30%
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Class Material
� Textbook: “Digital Integrated Circuits – A Design Perspective”, by J. Rabaey
� Class notes: Web page + Copy Central (New stuff!)
� Lab Reader:Available on the web page!Selected material will be made available from Copy
Central� Check web page for the availability of tools
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Software
� MicroMagic» Schematic editor: Sue» Layout editor: Max» Online documentation and tutorials
� HSPICE and IRSIM for simulation
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Getting Started
� Assignment 1: Getting SPICE to work –see web-page on Thursday
� NO discussion sessions or labs this week.
� First discussion sessions in Week 2� First Software Lab in Week 2
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Digital Integrated Circuits
� Introduction: Issues in digital design� The CMOS inverter� Combinational logic structures� Sequential logic gates; timing� Arithmetic building blocks� Interconnect: R, L and C� Memories and array structures� Design methods
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Introduction
� Why is designing digital ICs different today than it was before?
� Will it change in future?
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The First Computer
The BabbageDifference Engine(1832)25,000 partscost: £17,470
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ENIAC - The first electronic computer (1946)
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Intel 4004 Micro-Processor
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Intel Pentium (II) microprocessor
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Moore’s Law
In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.
He made a prediction that semiconductor technology will double its effectiveness every 18 months
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Moore’s Law16151413121110
9876543210
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
LOG
2 OF
THE
NUM
BER
OF
CO
MPO
NEN
TS P
ER IN
TEG
RATE
D F
UNCT
ION
Electronics, April 19, 1965.
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Evolution in Complexity
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Transistor Counts
1,000,000
100,000
10,000
1,000
10
100
11975 1980 1985 1990 1995 2000 2005 2010
808680286
i386i486
Pentium®Pentium® Pro
K 1 Billion Transistors
Source: Intel
Projected
Pentium® IIPentium® III
EE14120
Moore’s law in Microprocessors
400480088080
8085 8086286
386486 Pentium® proc
P6
0.001
0.01
0.1
1
10
100
1000
1970 1980 1990 2000 2010Year
Tran
sist
ors
(MT)
2X growth in 1.96 years!
Transistors on Lead Microprocessors double every 2 years
S. Borkar
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Moore’s Law - Logic Density
�Shrinks and compactions meet density goals�New micro-architectures drop density
Sour
ce: I
ntelPentium (R)
Pentium Pro (R) 486386
i860
1
10
100
1000
1.5µ
1.5µ
1.5µ
1.5µ
1.0µ
1.0µ
1.0µ
1.0µ
0.8µ
0.8µ
0.8µ
0.8µ
0.6µ
0.6µ
0.6µ
0.6µ
0.35
µ0.
35µ
0.35
µ0.
35µ
0.25
µ0.
25µ
0.25
µ0.
25µ
0.18
µ0.
18µ
0.18
µ0.
18µ
0.13
µ0.
13µ
0.13
µ0.
13µ
Logi
c D
ensi
ty
2x trend
Logi
c Tr
ansi
stor
s/m
m2
Pentium II (R)
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Die Size Growth
40048008
80808085
8086 286386
486Pentium ® procP6
1
10
100
1970 1980 1990 2000 2010Year
Die
siz
e (m
m)
~7% growth per year~2X growth in 10 years
Die size grows by 14% to satisfy Moore’s Law
S. Borkar
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Frequency
P6Pentium ® proc
48638628680868085
8080800840040.1
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Freq
uenc
y (M
hz)
Lead Microprocessors frequency doubles every 2 years
Doubles every2 years
S. Borkar
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Processor Frequency Trend
386486
Pentium(R)
Pentium Pro(R)
Pentium(R) IIMPC750
604+604
601, 603
21264S
2126421164A
2116421064A
21066
10
100
1,000
10,000
1987
1989
1991
1993
1995
1997
1999
2001
2003
2005
Mhz
1
10
100
Gat
e D
elay
s/ C
lock
IntelIBM Power PCDECGate delays/clock
Processor freq scales by 2X per
generation
� Frequency doubles each generation� Number of gates/clock reduce by 25%
V.De, S. BorkarISLPED’99
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Power
P6Pentium ® proc
486386
2868086
808580808008
4004
0.1
1
10
100
1971 1974 1978 1985 1992 2000Year
Pow
er (W
atts
)
Lead Microprocessors power continues to increase
S. Borkar
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Obeying Moore’s Law…
400480088080
8085 8086286
386486Pentium ® proc
P6
0.001
0.01
0.1
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Tran
sist
ors
(MT)
900M
1.8B
425M200M
200M--1.8B transistors on the Lead Microprocessor
S. Borkar
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Processor Power
386 386
486 486
Pentium(R) Pentium(R) MMX
Pentium Pro (R)
Pentium II (R)
1
10
100
1.5µ1.5µ1.5µ1.5µ 1µ1µ1µ1µ 0.8µ0.8µ0.8µ0.8µ 0.6µ0.6µ0.6µ0.6µ 0.35µ0.35µ0.35µ0.35µ 0.25µ0.25µ0.25µ0.25µ 0.18µ0.18µ0.18µ0.18µ 0.13µ0.13µ0.13µ0.13µ
Max
Pow
er (W
atts
) ?
� Lead processor power increases every generation� Compactions provide higher performance at lower power
Sour
ce: I
ntel
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Power will be a problem
5KW 18KW
1.5KW 500W
4004800880808085
8086286
386486
Pentium® proc
0.1
1
10
100
1000
10000
100000
1971 1974 1978 1985 1992 2000 2004 2008Year
Pow
er (W
atts
)
Power delivery and dissipation will be prohibitive
S. Borkar
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Power density will increase
400480088080
8085
8086
286 386486
Pentium® procP6
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Pow
er D
ensi
ty (W
/cm
2)
Hot Plate
NuclearReactor
RocketNozzle
Power density too high to keep junctions at low temp
S. Borkar
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Power delivery challenges
P6Pentium® proc
486386286
8086
80858080
800840040.01
0.10
1.00
10.00
100.00
1,000.00
1970 1980 1990 2000 2010Year
Icc
(am
p)
P6Pentium® proc
486386
286
8086
80858080
80084004
1.E-041.E-031.E-021.E-011.E+001.E+011.E+021.E+031.E+041.E+051.E+061.E+07
1970 1980 1990 2000 2010Year
L(di
/dt)/
Vdd
High supply currents at low voltage:Challenges: IR drop and L(di/dt) noise
S. Borkar
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Not Only Microprocessors
Digital Cellular Market(Phones Shipped)
1996 1997 1998 1999 2000
Units 48M 86M 162M 260M 435M Analog Baseband
Digital Baseband(DSP + MCU)
PowerManagement
Small Signal RF
PowerRF
(data from Texas Instruments)
CellPhone
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Productivity Trends
1
10
100
1,000
10,000
100,000
1,000,000
10,000,000
2003
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2005
2007
2009
10
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000Logic Tr./ChipTr./Staff Month.
xxxxxx
x21%/Yr. compound
Productivity growth rate
x
58%/Yr. compoundedComplexity growth rate
10,000
1,000
100
10
1
0.1
0.01
0.001
Logi
c Tr
ansi
stor
per
Chi
p(M
)
0.01
0.1
1
10
100
1,000
10,000
100,000
Prod
uctiv
ity(K
) Tra
ns./S
taff
-Mo.
Source: Sematech
Complexity outpaces design productivity
Com
plex
ity
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Design Abstraction Levels
n+n+S
GD
+
DEVICE
CIRCUIT
GATE
MODULE
SYSTEM
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Why Scaling?
� Technology shrinks by 0.7/generation� With every generation can integrate 2x more
functions per chip; chip cost does not increase significantly
� Cost of a function decreases by 2x� How to design chips with more and more functions?� Design engineering population does not double every
two years…� Need to understand different levels of abstraction
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This Class
� Introduces basic metrics for design of integrated circuits – how to measure delay, power, etc.
� Groups layout rectangles into transistors and wires» Transistors and wires into gates» Gates into functions
� Need to verify that the assumptions are valid