1 COMP541 Combinational Logic and Design Montek Singh Jan 30, 2007.

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COMP541COMP541

Combinational Logic Combinational Logic and Designand Design

Montek SinghMontek Singh

Jan 30, 2007Jan 30, 2007

Homework 1Homework 1 On web pageOn web page Due next ThursdayDue next Thursday

TopicsTopics Common Logic FunctionsCommon Logic Functions

DecodersDecoders EncodersEncoders MultiplexersMultiplexers

A little more Verilog syntaxA little more Verilog syntax Verilog for creating test vectorsVerilog for creating test vectors

Comb. Logic in ContextComb. Logic in Context

Typically part of system with storageTypically part of system with storage Computer looks like this at high levelComputer looks like this at high level

EnableEnable EnableEnable is a common input to logic functions is a common input to logic functions See it in memories and today’s logic blocksSee it in memories and today’s logic blocks

DecodersDecoders Typically n inputs and 2n outputsTypically n inputs and 2n outputs Drives high the output corresponding to binary Drives high the output corresponding to binary

code of inputcode of input

2-to-4 Line Decoder2-to-4 Line Decoder

2-to-4 with Enable2-to-4 with Enable

Truth Table, 3-to-8 DecoderTruth Table, 3-to-8 Decoder

Notice they are mintermsNotice they are minterms

SchematicSchematic

Multi-Level 3-to-8Multi-Level 3-to-8

Enable Used for ExpansionEnable Used for Expansion

Multi-Level 6-to-64Multi-Level 6-to-64

Uses for DecodersUses for Decoders Binary number might serve to select some Binary number might serve to select some

operationoperation Computer op codes are encodedComputer op codes are encoded

Decoder lines might select add, or subtract, or Decoder lines might select add, or subtract, or multiply, etc.multiply, etc.

Memory address linesMemory address lines

VariationsVariations

At rightAt right Enable notEnable not Inverted outputsInverted outputs

VerilogVerilog

EncoderEncoder Encoder is the opposite of decoderEncoder is the opposite of decoder 22nn inputs (or less – maybe BCD in) inputs (or less – maybe BCD in) n outputsn outputs

Truth TableTruth Table

Inputs are MintermsInputs are Minterms

Can OR them together appropriatelyCan OR them together appropriately AA00 = D = D11 + D + D33 + D + D55 + D + D77

What’s the Problem?What’s the Problem? What if D3 and D6 both high?What if D3 and D6 both high? Simple OR circuit will set A to 7Simple OR circuit will set A to 7

Priority EncoderPriority Encoder Chooses one with highest priorityChooses one with highest priority

Largest number, usuallyLargest number, usually

Note “don’t cares”Note “don’t cares”

What if all inputs are zero?

Need Another OutputNeed Another Output

A “Valid” outputA “Valid” output

Valid is OR of inputsValid is OR of inputs

Multiplexer (or Mux)Multiplexer (or Mux) Selects one of a set of inputs to pass Selects one of a set of inputs to pass

on to outputon to output Binary control code, n linesBinary control code, n lines

Choose from 2Choose from 2nn inputs inputs

Useful for choosing from sets of dataUseful for choosing from sets of data Memory or register to ALUMemory or register to ALU

Very commonVery common

Two Input MuxTwo Input Mux

LogicLogic

Logic is Decoder PlusLogic is Decoder Plus

Structural VerilogStructural Verilogmodule mux_4_to_1_line_structural(S, D, Y);module mux_4_to_1_line_structural(S, D, Y);

input [1:0] S;input [1:0] S;input [3:0] D;input [3:0] D;output Y;output Y;

wire [1:0] not_S;wire [1:0] not_S;wire [0:3] N;wire [0:3] N;

not(not_S[0], S[0]);not(not_S[0], S[0]);not(not_S[1], S[1]);not(not_S[1], S[1]);

and(N[0], not_S[1], not_S[0], D[0]);and(N[0], not_S[1], not_S[0], D[0]);and(N[1], not_S[1], S[0], D[1]);and(N[1], not_S[1], S[0], D[1]);and(N[2], S[1], not_S[0], D[2]);and(N[2], S[1], not_S[0], D[2]);and(N[3], S[1], S[0], D[3]);and(N[3], S[1], S[0], D[3]);

or(Y, N[0], N[1], N[2], N[3]);or(Y, N[0], N[1], N[2], N[3]);

endmoduleendmodule

We can do betterwith dataflow

(next)

Dataflow VerilogDataflow Verilogmodule mux_4_to_1_df(S, D, Y);module mux_4_to_1_df(S, D, Y); input [1:0] S;input [1:0] S; input [3:0] D;input [3:0] D; output Y;output Y;

assign Y = (~ S[1] & ~ S[0] & D[0])| assign Y = (~ S[1] & ~ S[0] & D[0])| (~ S[1] & S[0] & D[1]) |(~ S[1] & S[0] & D[1]) | ( S[1] & ~ S[0] & D[2]) |( S[1] & ~ S[0] & D[2]) |

( S[1] & S[0] & D[3]);( S[1] & S[0] & D[3]);endmoduleendmodule

Can do even better (next)

But First an AsideBut First an Aside Verilog constantsVerilog constants Conditional assignmentConditional assignment

Constants in VerilogConstants in Verilog SyntaxSyntax

[size][‘radix]constant[size][‘radix]constant Radix can be d, b, h, or o (default d)Radix can be d, b, h, or o (default d) ExamplesExamples

assign Y = 10;assign Y = 10; // Decimal 10// Decimal 10assign Y = ‘b10;assign Y = ‘b10; // Binary 10, decimal 2// Binary 10, decimal 2assign Y = ‘h10;assign Y = ‘h10; // Hex 10, decimal 16// Hex 10, decimal 16assign Y = 8‘b0100_0011 // Underline ignoredassign Y = 8‘b0100_0011 // Underline ignored

Binary values can be 0, 1, or xBinary values can be 0, 1, or x

Conditional AssignmentConditional Assignment Equality testEquality test

S == 2'b00S == 2'b00

AssignmentAssignment

assign Y = (S == 2'b00)?‘b0:assign Y = (S == 2'b00)?‘b0:‘‘b1;b1;

If true, assign 0 to YIf true, assign 0 to Y If false, assign 1 to YIf false, assign 1 to Y

4-to-1 Mux Truth Table-ish4-to-1 Mux Truth Table-ishmodule mux_4_to_1_dataflow(S, D, Y);module mux_4_to_1_dataflow(S, D, Y); input [1:0] S;input [1:0] S; input [3:0] D;input [3:0] D; output Y;output Y;

assign Y = (S == 2'b00) ? D[0] :assign Y = (S == 2'b00) ? D[0] : (S == 2'b01) ? D[1] :(S == 2'b01) ? D[1] : (S == 2'b10) ? D[2] :(S == 2'b10) ? D[2] : (S == 2'b11) ? D[3] : 1'bx ;(S == 2'b11) ? D[3] : 1'bx ;endmoduleendmodule

Verilog for Decision TreeVerilog for Decision Treemodule mux_4_to_1_binary_decision(S, D, Y);module mux_4_to_1_binary_decision(S, D, Y); input [1:0] S;input [1:0] S; input [3:0] D;input [3:0] D; output Y;output Y;

assign Y = S[1] ? (S[0] ? D[3] : D[2]) :assign Y = S[1] ? (S[0] ? D[3] : D[2]) : (S[0] ? D[1] : D[0]) ;(S[0] ? D[1] : D[0]) ;

endmoduleendmodule

Binary DecisionsBinary Decisions If S[1] == 1, branch one wayIf S[1] == 1, branch one way assign Y = S[1] ? (S[0] ? D[3] : D[2])assign Y = S[1] ? (S[0] ? D[3] : D[2])

and decide Y = either D[2] or D[3] based on S[0]and decide Y = either D[2] or D[3] based on S[0] ElseElse : (S[0] ? D[1] : D[0]) ;: (S[0] ? D[1] : D[0]) ;

decide Y is either D[2] or D[3] based on S[0]decide Y is either D[2] or D[3] based on S[0] Notice that conditional test is for ‘1’ condition Notice that conditional test is for ‘1’ condition

like in Clike in C

Quad 2-to-4 Line MuxQuad 2-to-4 Line Mux Select one set of 4 Select one set of 4

lineslines Can gang theseCan gang these Select a whole 64-Select a whole 64-

bit data busbit data bus

Three-State ImplementationThree-State Implementation

DemultiplexerDemultiplexer Takes one inputTakes one input Out to one of 2Out to one of 2nn possible outputs possible outputs

Demux is a DecoderDemux is a Decoder With an enableWith an enable

Code Converters Code Converters One code to anotherOne code to another Book puts seven-segment decoder in this Book puts seven-segment decoder in this

categorycategory Typically multiple outputsTypically multiple outputs

Each output has function or truth tableEach output has function or truth table

Seven-Segment DecoderSeven-Segment Decoder This Friday’s lab: Verilog of hex to LEDsThis Friday’s lab: Verilog of hex to LEDs

Extended version of book exampleExtended version of book example You may want to work out mapping (truth You may want to work out mapping (truth

table/function) before labtable/function) before lab

Change Topics toChange Topics to VerilogVerilog

First a couple of syntax stylesFirst a couple of syntax styles Help you program more efficientlyHelp you program more efficiently

Verilog test programsVerilog test programs

Instance Port NamesInstance Port Names ModuleModule module modp(output C, input A);module modp(output C, input A);

Ports referenced asPorts referenced as

modp i_name(conC, conA)modp i_name(conC, conA)

Also asAlso as modp i_name(.A(conA), .C(conC));modp i_name(.A(conA), .C(conC));

ParameterParameter Can set constantCan set constant

Like #defineLike #define

parameter SIZE = 16;parameter SIZE = 16;

Verilog for SimulationVerilog for Simulation Code more convenient than the GUI testbenchCode more convenient than the GUI testbench

Also more complex conditionsAlso more complex conditions Can test for expected resultCan test for expected result

ISEISE Make Verilog Test FixtureMake Verilog Test Fixture Will create a wrapper (a module)Will create a wrapper (a module)

Instantiating your circuitInstantiating your circuit It’ll be called UUT (unit under test)It’ll be called UUT (unit under test)

You then add your test codeYou then add your test code Example on next slidesExample on next slides

Module and Instance UUTModule and Instance UUTmodule syn_adder_for_example_v_tf();module syn_adder_for_example_v_tf();

// DATE: 21:22:20 01/25/2004 // DATE: 21:22:20 01/25/2004 // ...Bunch of comments...// ...Bunch of comments...

......// Instantiate the UUT// Instantiate the UUT syn_adder uut (syn_adder uut ( .B(B), .B(B), .A(A), .A(A), .C0(C0), .C0(C0), .S(S), .S(S), .C4(C4).C4(C4) ););

......endmoduleendmodule

RegReg It will create storage for the inputs to the UUTIt will create storage for the inputs to the UUT

// Inputs// Inputs reg [3:0] B;reg [3:0] B; reg [3:0] A;reg [3:0] A; reg C0;reg C0; We’ll talk more about We’ll talk more about regreg next class next class

Wires for OutputsWires for Outputs That specify bus sizesThat specify bus sizes

// Outputs// Outputs

wire [3:0] S;wire [3:0] S;

wire C4;wire C4;

Begin/EndBegin/End Verilog uses begin and end for blockVerilog uses begin and end for block instead of curly bracesinstead of curly braces

InitialInitial Initial statement runs when simulation beginsInitial statement runs when simulation begins

initial initial beginbegin

B = 0;B = 0; A = 0;A = 0; C0 = 0;C0 = 0; endend

Procedural assignmentProcedural assignment Why no “assign”?Why no “assign”? Because it’s not a continuous assignmentBecause it’s not a continuous assignment Explain more next class when we look at Explain more next class when we look at

storage/clockingstorage/clocking

Initialize in Default Test FileInitialize in Default Test File There’s one in ISE generated file, but don’t think There’s one in ISE generated file, but don’t think auto_initauto_init is defined is defined

// Initialize Inputs// Initialize Inputs `ifdef auto_init`ifdef auto_init

initial begininitial begin B = 0;B = 0; A = 0;A = 0; C0 = 0;C0 = 0; endend

`endif`endif

What to Add?What to Add? Need to make simulation time passNeed to make simulation time pass Use # command for skipping timeUse # command for skipping time Example (note no semicolon after #50)Example (note no semicolon after #50)

initial initial

beginbegin

B = 0;B = 0;

#50 B = 1;#50 B = 1;

endend

ForFor Can use Can use forfor loop in initial statement block loop in initial statement block

initialinitial beginbegin for(i=0; i < 5; i = i + 1)for(i=0; i < 5; i = i + 1) beginbegin

#50 B = i;#50 B = i;endend

endend

IntegersIntegers Can declare for loop control variablesCan declare for loop control variables

Will not synthesize, as far as I knowWill not synthesize, as far as I know

integer i;integer i;

integer j;integer j;

Can copy to input regsCan copy to input regs There may be problems with negative valuesThere may be problems with negative values

There are alsoThere are also WhileWhile RepeatRepeat ForeverForever

TimescaleTimescale Need to tell simulator what time scale to useNeed to tell simulator what time scale to use Place at top of test fixturePlace at top of test fixture

`timescale 1ns/10ps`timescale 1ns/10ps

System TasksSystem Tasks Tasks for the simulatorTasks for the simulator $stop – end the simulation$stop – end the simulation $display – like C printf$display – like C printf $monitor – prints when arguments change $monitor – prints when arguments change

(example next)(example next) $time – Provides value of simulated time$time – Provides value of simulated time

MonitorMonitor// set up monitoring// set up monitoring

initialinitial

begin begin $monitor($time, " A=%b ,B=%b\n", A, B);$monitor($time, " A=%b ,B=%b\n", A, B);

endend

// These statements conduct the actual test// These statements conduct the actual test

initialinitialbeginbegin

Code...Code... endend

TodayToday Common functions – should know these Common functions – should know these

DecoderDecoder Priority encoderPriority encoder Multiplexer (mux)Multiplexer (mux) DemultiplexerDemultiplexer

A little more VerilogA little more Verilog Verilog test programsVerilog test programs

NextNext Sequential CircuitsSequential Circuits

Storing stateStoring state Sections 6-1, 6-2, 6-3Sections 6-1, 6-2, 6-3

We’ll put off the study of arithmetic circuitsWe’ll put off the study of arithmetic circuits Chapter 5Chapter 5

1 COMP541 Combinational Logic and Design Montek Singh Jan 30, 2007.

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