Post on 06-Apr-2018
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Objective
Introduction to the various steps involved in routing.
After completion of this program students will be familiar with theRouting flow,Routing optimization, and will be ready to do therouting for any design.
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Routing
Objective:
Create metal connections to all clock and signal pins.
Metal traces must meet physical DRC requirements.
Minimize the total wire length, the number of vias, or just completing allconnections without increasing the chip area.
Each net meets its timing budget.
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Design status at start of routing phase
Placement completed
CTS completed
Power and ground nets routed
Estimated congestion acceptable
Estimated timing - acceptable (~0 ns slack)
Estimated max cap/transition no violations
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nets
1 1
1
via
branch
trunk
tracks
pins
2 2
2
Terminologies
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Metal routing Tracks
pitchMinimumSpacing
Pitch = minimum width + minimum spacing
Terminologies
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Routing Types
Grid-lessGrid based
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G-Cell
The size of a GRC is equal to the height of the average standard cell.
GR determines whether each assigned GRC along a path has enough wiretracks for assigned nets through the edges of that GRC.
If there are not enough wire tracks ,GR reassigns metal layers or GRCsaccordingly.
global route
congestion area
G-Cells
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Routing Types
S
T
Maze Routing
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Channel Routing
A channel is the routing region bounded by two parallel rows ofterminals
Assume top and bottom boundary
Each terminal is assigned a number to indicate which net it belongs to 0 indicates : does not require an electrical connection
Routing Types
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Channel Routing
channel
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Routing Anatomy
Metal layer 1
Via
Top
view
3Dview
Metal layer 2
Metal layer 3
Note: Colours used
in this slide are not
standard
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Typical Routing Flow
Placement Info
CT routing
Global Routing
Track Assignment
Detail Route
Search And Repair
Back Annotation
STA
Timingcheck
Proceed to Tape out
P&RTool
Yes
No
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Routing Operation
Track Assign
Global Route
Detail Route
Search&Repair
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Routing Phases
Global Routing
Input : detailed placement
Determine channel routing foreach net
Minimize area (congestion) &
improve timing
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Grid-based routing system
Metal traces (routes) are built along, andcentre around routing tracks
Each metal layer has its own tracks andpreferred routing direction:
M1: Horizontal M2: Vertical, etc
The tracks and preferred routingdirections are defined in a "unitTile"cell in the standard
cell library
Track
Pitch(based on DRC)
Grid Point
M1
Trace
M2 unitTile
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Global Route
Global Route (GR) is the first step in routing.
GR gives more accurate parasitic and delay estimates compared to VR.
The global Route that is performed during routing will be used by thesubsequent Track Assign operation.
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global route
congestion area
G-Cells
Global Route
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Track Assignment
Track Assignment (TA):
Assigns each net to a specifictrack and lays down the actualmetal traces.
It also attempts to:
Make long, straight traces.
Reduces the number of vias.
It does not check or followphysical DRC rules.
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Detail Routing
Input channels and approximate routingfrom the global routing phase
Determine the exact route and layers foreach net
Objective: valid routing, minimize area(congestion), meet timing constraints
Additional objectives: minimum via,power
Routing Phases
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Detail Route
Detail Route SBoxes
MinSpacing
Thin&FatSpacing
NotchSpacing
Notch
Spacing
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Search & Repair
Search & Repair fixes remaining DRC violations through multiple loopsusing progressively larger S-box sizes
Astro works on the FRAM view, not the detailed transistor-level (CEL)view.
Astro's DRC rules are a subset of the completely technology DRC rules
loop1loop2
loop3loop4
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Astro Routing Flow
From Placement
Set Clock Common
Options
Synthesize the Clock
Tree (CTS)
Re-connect Scan
Chains
Enable propagated
Clocks
Post-CTS Placement
Optimization
Optimize Timing
Skew
Optimize Timing
(Useful Skew CTO)
Route Clock Nets
Route Signal Nets
Optimize
Trace Topology
Post Route Clock
Tree Optimization
DFM
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Options for Routing & Optimization
Options must be set prior to any routing and optimization steps
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Route Guide
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Route Clock Nets First
Skew and insertion delay targets are easier to meet if clock netsare routed firstThis command can also be used to route critical signals or buses
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Routing Signal Nets : Auto Route
Easy routing for design with:
No timing, max trans/cap violations
No congestion
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Route Signals Nets with Logic Optimization
Effort : Medium
Routing Phase : Global Route
Optimization Targets
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Route Signal Nets: track Assign Phase
Routing Phase : Track Assign
Effort : Medium
Optimization Target
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Route Signal Nets : Detail Route Phase
Routing Phase : Detail Route
Effort : MediumOptimization Target
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Explicit Search & Repair
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Wire parasitic for external
STA are provided via a .spef
file
The .spef file can be
generated from the PARA
view or the internal LPE of
Astro
Back Annotation
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Back Annotation
This is how to dump the
SPEF for your current
database.
Output file name
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Netlist Output
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Back Up
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Channel Routing
Upper boundaryUpper boundary
Lower boundaryLower boundary
TracksTracks
TerminalsTerminalsViaVia
TrunksTrunks BranchesBranches
DoglegDogleg
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Post-route CTO
Minor clock skew and/or timing violations may have been
introduced by previous routing and optimization stepsUse Post Route CTO to fix these violations
Post Route CTO
ECO Route
Skew+
timing
OK?
No
Yes
All nets routed
Route ClockNets
Route SignalNets
Optimize TraceTopology
PostRouteCTO
Search&Repair
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Redundant Via
Metal2
Metal3 Via
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s 1
1
1
22
22
23
3 3
3
3
3
4
4
4
44
4
5
5
5
5
55
5
5t
Maze Routing
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Where STA fits in ASIC flow?
synthesis
DFT
Formal Verification
STA
Designconstraints
DRC,LVS
ExtractedParasitic
Back annotation
P&R tool
Timingcheck
Timing
check
.lib
No
YesNo
Yes
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Routing Regions