Vhdl code and project report of arithmetic and logic unit

transcript

PROJECT REPORT

“DIGITAL CALCULATOR”

“ARITHMETIC AND LOGIC UNIT”

In recognition to the partial fulfillment of DSD Practical [ENP301]

Submitted by

SARANG WANKHEDE[79]

V SEM,SEC A

NIKHIL SAHU [78]

V SEM,SEC A

KUNAL SAHA [81]

V SEM,SEC A

Under the guidance of

Prof. Pankaj Joshi

Dept. of Electronics Engineering, RCOEM

Shri Ramdeobaba College of Engineering and Management,Nagpur (An autonomous College of Rashtrasant Tukadoji Maharaj Nagpur University)

Department of Electronics Engineering

Year 2014-2015

Shri Ramdeobaba College of Engineering and Management,Nagpur (An autonomous College of Rashtrasant Tukadoji Maharaj Nagpur University)

Certificate

This is to certify that the project titled

“DIGITAL CALCULATOR”

has been Successfully completed by the following students under the guidance of Prof.

PANKAJ JOSHI in recognition to the partial fulfillment of the requirements for the Digital

System Design ENP-301 course work of Bachelor of Electronics Engineering during

academic year 2014-2015.

Students Name Roll No. Section Name Signature

SARANG WANKHEDE 79 A

NIKHIL SAHU 78 A

KUNAL SAHA 81 A

Prof. Pankaj Joshi (Project Guide)

Shri Ramdeobaba College of Engineering and Management,Nagpur

(An autonomous College of Rashtrasant Tukadoji Maharaj Nagpur University)

DSD Practical [ ENP 301] Evaluation Sheet

Internal Examiner External Examiner

itectu

79 SARANG WANKHEDE

78 NIKHIL SAHU

81 KUNAL SAHA

ABSTRACT

This is the technical report for our ENP-301 Project —Digital Calculator.

This project is software implemented. We modeled the system in VHDL

(Very-high-speed integrated circuit Hardware Description Language).

DIGITAL CALULATOR is a basically a 8 bit-ALU which performs

various arithmetic and logical operations like addition, subtraction,

multiplication , division, AND , OR , NAND ,EX-OR, etc.

ACKNOWLEDGEMENT

We feel great pleasure in submitting this report on the project “Digital

Calculator”. We would like to take this opportunity to express our gratitude to

our project guide, Prof.Pankaj Joshi for his support and constant

encouragement along with his expert guidance that helped us to complete the

project successfully. His everlasting patience and whole hearted inspiration

guided us on the right path to achieve what we have achieved today.

We are also thanking full to sub-ordinates staff that offered us their help and

stood by us.

In the end we would like to express our thanks to our friends and fellow who

helped us in many ways and encouraged us.

PROJECTEES:

SARANG WANKHEDE

NIKHIL SAHU

KUNAL SAHA

CONTENTS

Chapter 1 Introduction

Chapter 2 Motivation

Chapter 3 Working principle

Chapter 4 VHDL Code

Chapter 5 Results

Chapter 6 Applications

Chapter 7 Conclusion

Chapter 8 References

Chapter 9 Softcopy

INTRODUCTION

CHAPTER 1

INTRODUCTION

The main objective of project is to design and verify different operations of

Arithmetic and Logical Unit (ALU). We have designed an 8 bit ALU which

accepts two 8 bits numbers and the code corresponding to the operation which it

has to perform from the user. The ALU performs the desired operation and

generates the result accordingly. The different operations that we dealt with, are

arithmetical, logical and relational. Arithmetic operations include arithmetic

addition, subtraction, multiplication and division. Logical operations include

AND, OR, NAND, XOR, NOT and NOR. These take two binary inputs and

result in output logically operated. The operations like the greater than, less

than, equal to, exponential etc are also included. To implement ALU, the

coding was written in VHDL . The waveforms were obtained successfully.

After the coding was done, the synthesis of the code was performed using

Xilinx-ISE. Synthesis translates VHDL code into netlist (a textual description).

Thereafter, the simulation was done to verify the synthesized code.

MOTIVATION

Chapter 2

Motivation

In this project, our motive was to design a digital calculator which is a

8-bit ALU. An arithmetic logic unit (ALU) is a digital circuit that

performs arithmetic and logical operations. The ALU is a fundamental

building block of the central processing unit (CPU) of a computer, and

even the simplest microprocessors contain one for purposes such as

maintaining timers

WORKING PRINCIPLE

Chapter 3

Working

The arithmetic and logic unit simply performs operations on the data

given at input C & input D according to select input given by the user.

SR.NO SELECT INPUT OPERATIONS

1. 0000 SAME (Y<=C)

2. 0001 0010

ADD C,D

3. 0011

SUB C,D

4. 0101 0110

MULTIPLY C,D

5. 0111

DIVISION C,D

6. 1001 AND

7. 1010 OR

8. 1011 NOT C

9. 1100 EX-OR C,D

10 1101 EX-NOR C,D

11. 1110 NAND C,D

12. 1111 NOR C,D

The following is our design .diagram

VHDL CODE

VHDL CODE FOR DIGITAL CALCULATOR FULL ADDER

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity full_adder is Port ( A : in STD_LOGIC;

B : in STD_LOGIC; CINN : in STD_LOGIC; SUM : out STD_LOGIC;

CARRY : out STD_LOGIC); end full_adder;

architecture Behavioral of full_adder is

SUM <= a xor b xor cINN; carry <= (a and (b or cINN)) or (b and cINN);

end Behavioral;

FULL SUBTRACTOR

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

entity full_subtractor is Port ( a : in STD_LOGIC;

b : in STD_LOGIC; c : in STD_LOGIC;

sum : out STD_LOGIC; carry : out STD_LOGIC); end full_subtractor;

architecture Behavioral of full_subtractor is

begin sum<= a xor b xor c ;

carry<= ((not a) and b ) or ( b and c ) or ( (not a) and c) ;

end Behavioral; SAME

use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity same is Port ( x : in STD_LOGIC_VECTOR (7 downto 0);

z : out STD_LOGIC_VECTOR (7 downto 0)); end same;

architecture Behavioral of same is

begin z <= x;

end Behavioral;

BYTE ADDER

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

entity adder is Port ( a : in STD_LOGIC_VECTOR (07 downto 0);

b : in STD_LOGIC_VECTOR (07 downto 0); cin : in STD_LOGIC; s : out STD_LOGIC_VECTOR (07 downto 0);

cout : out STD_LOGIC_VECTOR (07 downto 0)); end adder;

architecture Behavioral of adder is signal i : std_logic_vector(7 downto 0);

component full_adder is Port ( A : in STD_LOGIC; B : in STD_LOGIC;

CINN : in STD_LOGIC; SUM : out STD_LOGIC;

CARRY : out STD_LOGIC); end component ; begin

FA0 : full_adder port map (a(0), b(0), cin , s(0), i(0));

FA1 : full_adder port map (a(1), b(1), i(0) , s(1), i(1)); FA2 : full_adder port map (a(2), b(2), i(1) , s(2), i(2));

FA3 : full_adder port map (a(3), b(3), i(2) , s(3), i(3)); FA4 : full_adder port map (a(4), b(4), i(3) , s(4), i(4));

FA5 : full_adder port map (a(5), b(5), i(4) , s(5), i(5)); FA6 : full_adder port map (a(6), b(6), i(5) , s(6), i(6)); FA7 : full_adder port map (a(7), b(7), i(6) , s(7), i(7));

cout(0)<= i(7) ;

cout(1)<= '0' ; cout(2)<= '0' ; cout(3)<= '0' ;

cout(4)<= '0' ; cout(5)<= '0' ;

cout(6)<= '0' ; cout(7)<= '0' ; end Behavioral;

BYTE SUBTRACTOR

entity subtractor is

Port ( a : in STD_LOGIC_VECTOR (07 downto 0); b : in STD_LOGIC_VECTOR (07 downto 0);

cin : in STD_LOGIC; cout : out STD_LOGIC_VECTOR (07 downto 0); s : out STD_LOGIC_VECTOR (07 downto 0));

end subtractor;

architecture Behavioral of subtractor is signal i : std_logic_vector(7 downto 0);

component full_subtractor is Port ( a : in STD_LOGIC; b : in STD_LOGIC;

c : in STD_LOGIC; sum : out STD_LOGIC;

carry : out STD_LOGIC); end component ; begin

FA0 : full_subtractor port map (a(0), b(0), cin , s(0), i(0));

FA1 : full_subtractor port map (a(1), b(1), i(0) , s(1), i(1)); FA2 : full_subtractor port map (a(2), b(2), i(1) , s(2), i(2));

FA3 : full_subtractor port map (a(3), b(3), i(2) , s(3), i(3)); FA4 : full_subtractor port map (a(4), b(4), i(3) , s(4), i(4));

FA5 : full_subtractor port map (a(5), b(5), i(4) , s(5), i(5)); FA6 : full_subtractor port map (a(6), b(6), i(5) , s(6), i(6)); FA7 : full_subtractor port map (a(7), b(7), i(6) , s(7), i(7));

cout(0)<= i(7) ;

cout(1)<= '0' ; cout(2)<= '0' ; cout(3)<= '0' ;

cout(4)<= '0' ; cout(5)<= '0' ;

cout(6)<= '0' ; cout(7)<= '0' ;

end Behavioral;

MULTIPLIER

library IEEE;

entity multiplier8bit is Port ( x : in STD_LOGIC_VECTOR (7 downto 0);

y : in STD_LOGIC_VECTOR (7 downto 0); q : out STD_LOGIC_VECTOR (7 downto 0); P : out STD_LOGIC_VECTOR (7 downto 0) );

end multiplier8bit;

architecture Behavioral of multiplier8bit is

type PRODUCT is array(0 to 7,0 to 7)of std_logic; signal XY:PRODUCT; signal

C10,C11,C12,C13,C20,C21,C22,C23,C30,C31,C32,C33,C34,C41,C42,C43,C44,C45,C51,C52,C53,C54,C55,C56,C61,C62,C63,C64,C65,C66,C67,C71,C72,C73,C74,C75,C76,C77,C81

,C82,C83,C84,C85,C86,C87,C91,C92,C93,C94,C95,C101,C102,C103,C104,C111,C112,C113,C121,C122,C123:std_logic;

signal S11,S21,S22,S31,S32,S33,S41,S42,S43,S44,S51,S52,S53,S54,S55,S61,S62,S63,S64,S65,S6

6,S71,S72,S73,S74,S75,S76,S81,S82,S83,S84,S85,S91,S92,S93,S94,S101,S102,S103,S111,S112,S121:std_logic;

component full_adder Port ( A : in STD_LOGIC;

B : in STD_LOGIC; CINN : in STD_LOGIC;

sum : out STD_LOGIC; carry : out STD_LOGIC); end component;

* begin

GEN1: for i in 0 to 7 generate GEN2: for j in 0 to 7 generate GEN3: XY(i,j) <= X(i) and Y(j);

end generate; end generate;

FA0 : full_adder port map(XY(1,0), '0', XY(0,1), P(1), C10); FA1 : full_adder port map(XY(2,0),XY(1,1),'0',S11,C11);

FA2 : full_adder port map(XY(0,2),S11,C10,P(2),C12); FA3 : full_adder port map(XY(3,0),XY(2,1),C12,S21,C21);

FA4 : full_adder port map(XY(1,2),XY(0,3),C11,S22,C22); FA5 : full_adder port map(S21,S22,'0',P(3),C23); FA6 : full_adder port map(XY(4,0),XY(3,1),C21,S31,C31);

FA7 : full_adder port map(XY(2,2),XY(1,3),C22,S32,C32); FA8 : full_adder port map(S31,S32,C23,S33,C33);

FA9 : full_adder port map(XY(0,4),S33,'0',P(4),C34); FA10 : full_adder port map(XY(5,0),XY(4,1),C31,S41,C41); FA11: full_adder port map(XY(3,2),XY(2,3),C32,S42,C42);

FA12: full_adder port map(XY(1,4),XY(0,5),C33,S43,C43); FA13: full_adder port map(S41,S42,C34,S44,C44);

FA14: full_adder port map(S43,S44,'0',P(5),C45); FA15: full_adder port map(XY(6,0),XY(5,1),C41,S51,C51); FA16: full_adder port map(XY(4,2),XY(3,3),C42,S52,C52);

FA17: full_adder port map(XY(2,4),XY(1,5),C43,S53,C53); FA18: full_adder port map(XY(0,6),S51,C44,S54,C54);

FA19: full_adder port map(S52,S53,C45,S55,C55); FA20: full_adder port map(S54,S55,'0',P(6),C56); FA21: full_adder port map(XY(7,0),XY(6,1),C51,S61,C61);

FA22: full_adder port map(XY(5,2),XY(4,3),C52,S62,C62); FA23: full_adder port map(XY(3,4),XY(2,5),C53,S63,C63);

FA24: full_adder port map(XY(1,6),XY(0,7),C54,S64,C64); FA25: full_adder port map(S61,S62,C55,S65,C65); FA26: full_adder port map(S63,S64,C56,S66,C66);

FA27: full_adder port map(S65,S66,'0',P(7),C67);

FA30: full_adder port map(XY(3,5),XY(2,6),C63,S73,C73); FA31 : full_adder port map(XY(1,7),S71,C64,S74,C74);

FA32: full_adder port map(S72,S73,C65,S75,C75); FA33: full_adder port map(S74,S75,C66,S76,C76); FA34: full_adder port map(S76,'0',C67,q(0),C77);

FA37: full_adder port map(XY(3,6),XY(2,7),C73,S83,C83); FA38: full_adder port map(S81,C74,C75,S84,C84); FA39: full_adder port map(S82,S83,C76,S85,C85);

FA40: full_adder port map(S84,S85,C77,q(1),C86); FA41: full_adder port map(XY(7,3),XY(6,4),C81,S91,C91);

FA42: full_adder port map(XY(5,5),XY(4,6),C82,S92,C92); FA43: full_adder port map(XY(3,7),S91,C83,S93,C93); FA44: full_adder port map(S92,S93,C84,S94,C94);

FA45: full_adder port map(S94,C85,C86,q(2),C95); FA46: full_adder port map(XY(7,4),XY(6,5),C91,S101,C101);

FA47: full_adder port map(XY(5,6),XY(4,7),C92,S102,C102); FA48: full_adder port map(S101,C93,C94,S103,C103); FA49: full_adder port map(S102,S103,C95,q(3),C104);

FA50: full_adder port map(XY(7,5),XY(6,6),C101,S111,C111); FA51: full_adder port map(XY(5,7),S111,C102,S112,C112);

FA52: full_adder port map(S112,C103,C104,q(4),C113); FA53: full_adder port map(XY(7,6),C111,C112,S121,C121); FA54: full_adder port map(XY(6,7),S121,C113,q(5),C122);

FA55: full_adder port map(XY(7,7),C121,C122,q(6),q(7));

P(0) <= XY(0,0);

end Behavioral;

DIVIDER

entity divider8 is Port ( Ain : in STD_LOGIC_VECTOR (07 downto 0); Bin : in STD_LOGIC_VECTOR (07 downto 0);

Q : out STD_LOGIC_VECTOR (07 downto 0);

R : out STD_LOGIC_VECTOR (07 downto 0)); end divider8;

architecture Behavioral of divider8 is

begin proc1 : process(Ain , Bin) variable Atemp : std_logic_vector (7 downto 0);

variable count : std_logic_vector (7 downto 0) ;

begin if( Ain < Bin)then

count :="00000000"; Atemp := Ain ;

elsif ( Ain = Bin ) then count :="00000001"; Atemp :="00000000";

elsif ( Ain > Bin )then count := "00000001" ;

Atemp := Ain-Bin ; --wait for 0 ns;

while (Atemp >= Bin) loop if(Atemp >= Bin)then

Atemp := Atemp-Bin ; count := count + 1 ; end if;

end loop ;

end if ; Q <= count ; R <= Atemp ;

--wait on Ain, Bin ;

end process proc1; end Behavioral;

AND GATE

entity and_gate is Port ( a : in STD_LOGIC_VECTOR (07 downto 0);

b : in STD_LOGIC_VECTOR (07 downto 0);

y : out STD_LOGIC_VECTOR (07 downto 0)); end and_gate;

architecture Behavioral of and_gate is

begin y <= a and b;

end Behavioral;

OR GATE

library IEEE;

entity or_gate is Port ( a : in STD_LOGIC_VECTOR (07 downto 0);

b : in STD_LOGIC_VECTOR (07 downto 0); y : out STD_LOGIC_VECTOR (07 downto 0)); end or_gate;

architecture Behavioral of or_gate is

begin y <=a or b ;

end Behavioral;

NOT GATE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity not_gate is

Port ( y : in STD_LOGIC_VECTOR (07 downto 0); z : out STD_LOGIC_VECTOR (07 downto 0)); end not_gate;

architecture Behavioral of not_gate is

begin z <= not y;

end Behavioral;

EX-OR GATE

library IEEE;

use IEEE.STD_LOGIC_UNSIGNED.ALL; entity exor is

y : out STD_LOGIC_VECTOR (07 downto 0)); end exor;

architecture Behavioral of exor is

begin y <= a xor b;

end Behavioral;

EX-NOR GATE

entity exnor is Port ( a : in STD_LOGIC_VECTOR (07 downto 0);

b : in STD_LOGIC_VECTOR (07 downto 0); y : out STD_LOGIC_VECTOR (07 downto 0)); end exnor;

architecture Behavioral of exnor is

begin y <= a xnor b;

end Behavioral;

NAND GATE

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity nand_gate is

Port ( a : in STD_LOGIC_VECTOR (07 downto 0); b : in STD_LOGIC_VECTOR (07 downto 0); y : out STD_LOGIC_VECTOR (07 downto 0));

end nand_gate;

architecture Behavioral of nand_gate is begin

y <= a nand b;

end Behavioral;

NOR GATE

entity nor_gate is

end nor_gate;

architecture Behavioral of nor_gate is begin

y <= a nor b; end Behavioral;

MUX 16: 1

use IEEE.STD_LOGIC_UNSIGNED.ALL; entity mux is

Port ( a : in STD_LOGIC_VECTOR (7 downto 0); b : in STD_LOGIC_VECTOR (7 downto 0); e : in STD_LOGIC_VECTOR (7 downto 0);

f : in STD_LOGIC_VECTOR (7 downto 0);

g : in STD_LOGIC_VECTOR (7 downto 0); h : in STD_LOGIC_VECTOR (7 downto 0);

i : in STD_LOGIC_VECTOR (7 downto 0); j : in STD_LOGIC_VECTOR (7 downto 0);

k : in STD_LOGIC_VECTOR (7 downto 0); l : in STD_LOGIC_VECTOR (7 downto 0); m : in STD_LOGIC_VECTOR (7 downto 0);

n : in STD_LOGIC_VECTOR (7 downto 0); o : in STD_LOGIC_VECTOR (7 downto 0);

p : in STD_LOGIC_VECTOR (7 downto 0); q : in STD_LOGIC_VECTOR (7 downto 0); r : in STD_LOGIC_VECTOR (7 downto 0);

s : in STD_LOGIC_VECTOR (3 downto 0); y : out STD_LOGIC_vector(7 downto 0));

end mux; architecture Behavioral of mux is

process (s) begin case s is

when "0000" => y <= a; when "0001" => y <= b;

when "0010" => y <= e; when "0011" => y <= f; when "0100" => y <= g;

when "0101" => y <= h; when "0110" => y <= i;

when "0111" => y <= j; when "1000" => y <= k; when "1001" => y <= l;

when "1010" => y <= m; when "1011" => y <= n;

when "1100" => y <= o; when "1101" => y <= p; when "1110" => y <= q;

when others => y <= r; end case;

end process; end Behavioral;

MAIN PROGRAM library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

entity DIGITAL_CALCULATOR is

Port ( c : in STD_LOGIC_VECTOR (07 downto 0); d : in STD_LOGIC_VECTOR (07 downto 0);

cin : in STD_LOGIC; sel : in STD_LOGIC_VECTOR (03 downto 0); y : out STD_LOGIC_VECTOR (07 downto 0));

end DIGITAL_CALCULATOR;

architecture Behavioral of DIGITAL_CALCULATOR is component same is Port ( x : in STD_LOGIC_VECTOR (7 downto 0);

z : out STD_LOGIC_VECTOR (7 downto 0)); end component;

component adder is

cin : in STD_LOGIC; cout : out STD_LOGIC_VECTOR (07 downto 0); s : out STD_LOGIC_VECTOR (07 downto 0));

end component ;

component subtractor is Port ( a : in STD_LOGIC_VECTOR (07 downto 0); b : in STD_LOGIC_VECTOR (07 downto 0);

cin : in STD_LOGIC; cout : out STD_LOGIC_VECTOR (07 downto 0);

s : out STD_LOGIC_VECTOR (07 downto 0)); end component ;

component not_gate is Port ( y : in STD_LOGIC_VECTOR (07 downto 0); z : out STD_LOGIC_VECTOR (07 downto 0));

end component;

component and_gate is Port ( a : in STD_LOGIC_VECTOR (07 downto 0); b : in STD_LOGIC_VECTOR (07 downto 0);

y : out STD_LOGIC_VECTOR (07 downto 0)); end component;

component or_gate is Port ( a : in STD_LOGIC_VECTOR (07 downto 0);

component nand_gate is

end component;

component divider8 is Port ( Ain : in STD_LOGIC_VECTOR (07 downto 0); Bin : in STD_LOGIC_VECTOR (07 downto 0);

Q : out STD_LOGIC_VECTOR (07 downto 0); R : out STD_LOGIC_VECTOR (07 downto 0));

end component; component multiplier8bit is

Port ( x : in STD_LOGIC_VECTOR (07 downto 0); y : in STD_LOGIC_VECTOR (07 downto 0);

q : out STD_LOGIC_VECTOR (07 downto 0); P : out STD_LOGIC_VECTOR (07 downto 0)); end component;

component nor_gate is Port ( a : in STD_LOGIC_VECTOR (07 downto 0); b : in STD_LOGIC_VECTOR (07 downto 0);

component exor is

component exnor is

end component;

component mux is Port ( a : in STD_LOGIC_VECTOR (7 downto 0);

e : in STD_LOGIC_VECTOR (7 downto 0);

f : in STD_LOGIC_VECTOR (7 downto 0); g : in STD_LOGIC_VECTOR (7 downto 0);

h : in STD_LOGIC_VECTOR (7 downto 0); i : in STD_LOGIC_VECTOR (7 downto 0);

j : in STD_LOGIC_VECTOR (7 downto 0); k : in STD_LOGIC_VECTOR (7 downto 0); l : in STD_LOGIC_VECTOR (7 downto 0);

m : in STD_LOGIC_VECTOR (7 downto 0); n : in STD_LOGIC_VECTOR (7 downto 0);

o : in STD_LOGIC_VECTOR (7 downto 0); p : in STD_LOGIC_VECTOR (7 downto 0); q : in STD_LOGIC_VECTOR (7 downto 0);

r : in STD_LOGIC_VECTOR (7 downto 0); s : in STD_LOGIC_VECTOR (3 downto 0);

--x : in STD_LOGIC_VECTOR (7 downto 0); y : out STD_LOGIC_vector(7 downto 0));

end component;

signal a1: STD_LOGIC_VECTOR (7 downto 0);

signal b1 : STD_LOGIC_VECTOR (7 downto 0);

signal e1 : STD_LOGIC_VECTOR (7 downto 0);

signal f1 : STD_LOGIC_VECTOR (7 downto 0); signal g1 : STD_LOGIC_VECTOR (7 downto 0);

signal h1 : STD_LOGIC_VECTOR (7 downto 0);

signal i1 : STD_LOGIC_VECTOR (7 downto 0);

signal j1 : STD_LOGIC_VECTOR (7 downto 0);

signal k1 : STD_LOGIC_VECTOR (7 downto 0); signal l1 : STD_LOGIC_VECTOR (7 downto 0);

signal m1 : STD_LOGIC_VECTOR (7 downto 0);

signal n1 : STD_LOGIC_VECTOR (7 downto 0);

signal o1 : STD_LOGIC_VECTOR (7 downto 0);

signal p1 : STD_LOGIC_VECTOR (7 downto 0); signal q1 : STD_LOGIC_VECTOR (7 downto 0);

signal r1 : STD_LOGIC_VECTOR (7 downto 0); --signal x1 : STD_LOGIC_VECTOR (7 downto 0);

begin z1: same port map(c,a1); a2: adder port map(c,d,cin,b1,e1);

a3: subtractor port map(c,d,cin,f1,g1); a4: multiplier8bit port map(c,d,h1,i1);

a5: divider8 port map(c,d,j1,k1); a6: and_gate port map(c,d,l1); a7: or_gate port map(c,d,m1);

a8: not_gate port map(c,n1); a10: exor port map(c,d,o1);

a11: exnor port map(c,d,p1); a12: nand_gate port map(c,d,q1); a13: nor_gate port map(c,d,r1);

a14: mux port map(a1,b1,e1,f1,g1,h1,i1,j1,k1,l1,m1,n1,o1,p1,q1,r1,sel,y);

end Behavioral; TEST BENCH

LIBRARY ieee; USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL;

ENTITY alu_tb11_vhd IS END alu_tb11_vhd;

ARCHITECTURE behavior OF alu_tb11_vhd IS

-- Component Declaration for the Unit Under Test (UUT) COMPONENT DIGITAL_CALCULATOR

PORT( c : IN std_logic_vector(7 downto 0); d : IN std_logic_vector(7 downto 0);

cin : IN std_logic; sel : IN std_logic_vector(3 downto 0);

y : OUT std_logic_vector(7 downto 0) ); END COMPONENT;

--Inputs

SIGNAL cin : std_logic := '0'; SIGNAL c : std_logic_vector(7 downto 0) := (others=>'0'); SIGNAL d : std_logic_vector(7 downto 0) := (others=>'0');

SIGNAL sel : std_logic_vector(3 downto 0) := (others=>'0');

--Outputs

SIGNAL y : std_logic_vector(7 downto 0);

-- Instantiate the Unit Under Test (UUT) uut: DIGITAL_CALCULATOR PORT MAP(

c => c, d => d, cin => cin,

sel => sel, y => y

); tb : PROCESS

BEGIN --wait for 20 ns;

c<="11111111"; d<="11111111"; cin<='0';

-- wait for 01 ns; sel<="0000";

wait for 20 ns; sel<="0001"; wait for 40 ns;

sel<="0010"; wait for 40 ns;

sel<="0011"; wait for 40 ns; sel<="0100";

wait for 40 ns; sel<="0101";

sel<="1000"; wait for 40 ns; sel<="1001";

sel<="1100";

--wait; -- will wait forever END PROCESS;

SEND ;

RESULT

6.1 Project Properties

Sr. No. Name Specification

1. Family Automotive CoolRunner2

2. Device Automatic xa2c000

3. Top-level Source Type HDL

4. Synthesis tool XST (Verilog)

5. Simulator ISE Simulator (Verilog)

6. Preferred Language Verilog

6.2 RTL Schematic

6.3 Waveform

APPLICATIONS

ALU is used digital electronics .

ALU is used to perform arithmetic and logical operations.

ALU is fundamental building block of the central processing unit .

ALU is also used in Microprocessors and Microcontroller .

ALU is also used in Calculators.

CONCLUSION

In this project, we obtained more experience with designing a

code using VHDL and how to program a FPGA. Moreover, we

learn more fundamental principles of designing digital systems.

In summary, this project is a good software hardware co-design

practice.

REFERENCES

Books:

Text Books

1. Fundamentals of Digital Logic with VHDL design ; Stephen Brown,

Zvonko Vranesic ;TMH.

2. VHDL Primer ; J Bhasker ; Pearson Education.

3. VHDL-a Design Oriented Approach; S. S. Limaye;

1. Digital System Design Using VHDL ; Charles H. Roth; Thomson.

2. VHDL Synthesis Primer; J Bhasker; Prentice Hall.

3. VHDL Modular Design and Synthesis of Cores and System ;

Zainalabedin Navabi; McGraw Hill Professional.

Websites :

http://www.xilinx.com

http://www.wikipedia.org

SOFTCOPY