1 ERD 2007 ITRS Spring Conference – LImperial Palace Hotel – Annecy, France – 25 April, 2007...

1 ERD 2007 ITRS Spring Conference – L’Imperial Palace Hotel – Annecy, France – 25 April, 2007

DRAFT – Work in Progress – NOT FOR PUBLICATION

ITRS Spring Public Conference

Emerging Research Devices

Annecy, FranceL’Imperial Palace Hotel

April 25, 2007

Jim Hutchby – SRC



Hiroyugi Akinaga AIST Tetsuya Asai Hokkaido U. Yuji Awano Fujitsu George Bourianoff Intel/SRC Joe Brewer U. Florida John Carruthers PSU Ralph Cavin SRC U-In Chung Samsung Philippe Coronel ST Me Erik DeBenedictis SNL Simon Deleonibus LETI Kristin De Meyer IMEC Mike Forshaw UC London Christian Gamrat CEA Mike Garner Intel Shigenori Hayashi Matsushita Toshiro Hiramoto U. Tokyo Dan Herr SRC Matsuo Hidaka ISTEK Jim Hutchby SRC Kohei Itoh Keio U. Yasuo Inoue Renesas Tech Seiichiro Kawamura Selete Hiroshi Kotaki Sharp Nety Krishna AMAT Zoran Krivokapic AMD

Phil Kuekes HPLou Lome IDA Hiroshi Mizuta Tokyo Tech Murali Muralidhar Freescale Fumiyuki Nihei NEC Wei-Xin Ni NDL Tak Ning IBM Lothar Risch Infineon Dave Roberts Air Products Kaushal Singh AMAT Kentaro Shibahara Hiroshima U. Thomas Skotnicki ST Me Satoshi Sugahara Tokyo Tech Shin-ichi Takagi U. Tokyo Luan Tran Micron Ken Uchida Toshiba Yasuo Wada Waseda U. Rainer Waser RWTH A Philip Wong Stanford U. Kojiro Yagami Sony In-Seok Yeo Samsung Makoto Yoshimi SOITEC In-K Yoo SAIT Peter Zeitzoff Freescale Yuegang Zhang Intel Victor Zhirnov SRC

ITRS Emerging Research Devices Working Group



Tetsuya Asai Hokkaido U. Ralph Cavin SRC George Bourianoff Intel Erik DeBenedictis SNL Michael Frank AMD Dan Hammerstrom PSU Rick Kiehl U. Minn.

Phil Kuekes HP Lou Lome NASA/JPL Sadas Shankar Intel Rainer Waser Aachen U. Franz Widdershoven NXP David Yeh SRC/TI Victor Zhirnov SRC

ITRS Emerging Research Architectures Working

Group



Emerging Research DevicesOrganization & Component Tasks (2007)

Emerging Research Devices

EmergingLogic and Memory

Devices

EmergingArchitectures

EmergingMaterials

Create a New Chapter in 2007


DRAFT – Work in Progress – NOT FOR PUBLICATIONyear

Beyond CMOS

Elements

ERD-WG in Japan

Existing technologies

New technologies

Evolution of Extended CMOS



Nano-floating Gate Memory

Engineered tunnel barrier

Memory

Ferroelectric FET Memory

Insulator Resistance

Change Memory

Polymer Memory

Molecular Memories

Cell Elements 1T 1T 1T 1T1R or 1R 1T1R or 1R 1T1R or 1R

Device Types

1 Nanocrystal 2 Direct tunneling

Graded insulator

FET with FE gate insulator

1 M-I-M 2 Solid Electrolyte 3 FE tunneling 4 FE Schottky diode 5 FE-I-FE

M-I-M(nc)-I-M

Bi-stable switch

2005 ITRS ERD Emerging Research Memory Devices

Transfer to

PIDS



2007 ITRS ERD Capacitance-based Memory Technologies

Engineered tunnel barrier

Memory

Ferroelectric FET Memory

Storage Mechanism

Charge on floating gate

Remnant polarization on a ferroelectric gate

dielectric

Cell Elements 1T 1T

Device TypesGraded

insulatorFET with FE gate insulator



2007 ITRS ERD Resistance-based Memory Technologies

Nanomechanical memory

Fuse/Antifuse Memory

Ionic Memory Electron Injection Memory

PolymerMemory

Molecular Memories

Storage Mechanism

electrostatically-controlled

bi-stable mechanical

switch

Multiple mechanisms

Ion transport in solids

Multiple mechanisms

Not known

Not known

Cell Elements

1T1R or 1R 1T1R or 1R 1T1R or 1R 1T1R or 1R1T1R or

1R1T1R or

1R

Device Types

CNT bridgeCNT cantileverSi cantilever Nanoparticle

M -I-M e.g. Pt/NiO/Pt

1) Solid Electrolyte 2) RedOx reaction

1) Charge trapping2) Mott transition3) FE Barrier effects

M-I-M (nc)-I-M

Bi-stable switch

New to ERD Memory Table



Device

FET [B] 1D structures Resonant

Tunneling Devices SET Molecular

Ferromagnetic logic

Spin transistor

Types Si CMOS

CNT FET

NW FET

NW hetero-structures

Crossbar nanostructure

RTD-FET

RTT SET

Crossbar latch

Molecular transistor

Molecular QCA

Moving domain wall

M: QCA Spin transistor

Supported Architectures Conventional Conventional

and Cross-bar Conventional

and CNN CNN

Cross-bar and QCA

CNN Reconfigure

logic and QCA

Conventional

2005 ITRS ERD Emerging Research Logic Devices



Logic Device Technologies

(Potential)

Scalability [A] Performance

[B]

Energy Efficiency

[C] Gain [D2]

Operational Reliability

[E]

Room Temp

Operation [F] ***

CMOS Technological Compatibility

[G]**

CMOS Architectural Compatibility

[H]*

1D Structures (CNTs & NWs) 2.4 2.5 2.3 2.3 2.1 2.8 2.3 2.8

Resonant Tunneling Devices

1.5 2.2 2.1 1.7 1.7 2.5 2.0 2.0

SETs 1.9 1.5 2.6 1.4 1.2 1.9 2.1 2.1

Molecular Devices 1.6 1.8 2.2 1.5 1.6 2.3 1.7 1.8

Ferromagnetic Devices 1.4 1.3 1.9 1.5 2.0 2.5 1.7 1.7

Spin Transistor 2.2 1.3 2.4 1.2 1.2 2.4 1.5 1.7

Critical EvaluationLogic

For each Technology Entry (e.g. 1D Structures, sum horizontally over the 8 CriteriaMax Sum = 24Min Sum = 8

> 20

>18 - 20 < 16

>16 - 18



Logic Device Conclusions

Continued analysis of alternative technology entries likely will continue to yield the same result: Nothing beats MOSFETs overall for performing

Boolean logic operations at comparable risk levels

Certain functions, e.g. image recognition (associative processing), may be more efficiently done in networks of non-linear devices rather than Boolean logic gates



Supplementing CMOS

General Purpose Processor

Basis of Existing Assessments of Logic Devices

A possible ultimate evolution of on-chip architectures is Asynchronous Heterogeneous Multi-Core with Hierarchical Processors Organization

MF(n) – application-specific processor implementing a specific macro-function

(may need specialized devices)

General Purpose

Processor

MF1 MF2 MF3 MF4

MF5

MF6

MF7MF10

MF11

MF9 MF8

MF12



New focus of Logic Section Consider new logic technologies that supplement

CMOS to provide enhanced hardware capability and can be optimally executed with alternative devices

Determine appropriate metric and compare to Si on the specialized application

Determine if proposed application contains a standard set of “macro-functions”

Understand the performance of the device in terms of its non-linear characteristics

Think in terms of heterogeneous co-processors integrated with traditional CPU



Direction of 2007 chapter

Retain present table that evaluates technology entries (TEs) against CMOS devices for Boolean logic

Include a second table (new) that evaluates TEs against CMOS for special purpose “macro-functions” e.g. vision processingThink of macro functions being implemented in special

purpose co-processorsRevise and broaden the Architecture Section to address

possible macro functionsConsider inclusion of new TEs based on enhanced

functionalities in new operations



Device

FET [B] 1D structures Resonant

Tunneling Devices SET Molecular

Ferromagnetic logic

Spin transistor

Types Si CMOS

CNT FET

NW FET

NW hetero-structures

Crossbar nanostructure

RTD-FET

RTT SET

Crossbar latch

Molecular transistor

Molecular QCA

Moving domain wall

M: QCA Spin transistor

Supported Architectures Conventional Conventional

and Cross-bar Conventional

and CNN CNN

Cross-bar and QCA

CNN Reconfigure

logic and QCA

Conventional

2005 ITRS ERD Emerging Research Logic Devices

Sub-CategorizeMolecular and Spin



Sub-categories for Spin and molecular devices

SpinDomain wall manipulationFerromagnetic phase change (nano-domains)Spin transport modulationSpin torque transferIndividual and or collective spin manipulation

Molecular devicesCrossbar coupling elementsMolecular logic elements and interconnectsIntra molecular logic elements



Potential Supplemental Applications Image recognition Speech recognition DSP (cross correlation) Data Mining Optimization Physical simulation Sensory data processing (biological, physical) Image creation Cryptographic analysis

Can we define a Universal Set of Basic Macrofunctions?



Proposed New Focus of Architecture Section

Possible MacrofunctionsRecognition

– Examine a static data array for a specified feature set and compare to a template

Mining– Finding sets of patterns in a specified pattern stream

Synthesis– Making predictions based on stored pattern streams

Consider device level architectures that optimally organize alternative non-linear devices to supplement CMOS to

provide enhanced hardware capability

Emerging Research Architectures

CMOL – ‘Molecule on CMOS’ architectureCNN – Cellular Nonlinear NetworkAMP – Associative Memory Processor

GPP – General Purpose ProcessorFG-MOS – Floating Gate MOS devicesSET – single electron transistor

Architecture ImplementationComputational

ElementsNetwork Application

Research Activity

Homogeneous Many-Core

Symmetric cores CMOSIrregular/

FixedSynthesis/GPP

Heterogeneous

Asymmetric cores

CMOSIrregular/

FixedSynthesis/GPP

CMOLCMOS+Molecular

SwitchesIrregular/

FixedSynthesis/GPP

Molecular Cross-bar

Molecular SwitchesRegular/Flexible

Synthesis/GPP

Check-pointCMOS+

Ferromagnetic logicIrregular/

FixedSynthesis/GPP

Morphic

CNN CMOS+SensorsRegular/Flexible

Recognition/Vision

AMP FG-FET, SETIrregular/

FixedRecognition/Vision

Bio-inspiredMFDT,

Spin-gain transistorMixed

Recognition Mining Synthesis

MFTD – multiferroic tunnel diode



MessagesScope: Broaden scope to encourage emerging technologies both to

supplement CMOS as well as eventually to invent the new “switch”.Materials Section: Spin out a new cross-cut chapter on Emerging

Research Materials.Memory Section: Will add NEMS mechanical memory to section.

– Divide Emerging Memory Tables into Resistive and Capacitive subcategories– Update section in 2007.

Logic Section: Considering reformulation of Logic Device Section to encourage high potential, but high risk approaches while maintaining Technology Entry evaluation function. – Create subcategories for key Technology Entries (e.g. Spin &

Molecular logic).– Re-considering status of candidate Technology Entries.– Re-structuring Logic Section via Emerging Logic Workshop in

September.Architecture Section: Revise to focus on encouraging research to

explore optimal organization of emerging non-linear devices to efficiently realize macro-functions to supplement the CMOS platform technology.

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