15-447 Computer Architecture Fall 2008 ©

September 17th, 2008

Majd F. Sakr

msakr@qatar.cmu.edu

www.qatar.cmu.edu/~msakr/15447-f08/

CS-447– Computer Architecture

M,W 2-3:50pm

Lecture 10Datapath & Control

15-447 Computer Architecture Fall 2008 ©

Lecture Objectives

°Learn what a datapath is, and how does it provide the required functions.

°Appreciate why different implementation strategies affects the clock rate and CPI of a machine.

°Understand how the ISA determines many aspects of the hardware implementation.

15-447 Computer Architecture Fall 2008 ©

The Big Picture of a Computer System

Datapath Control

Processor

Main Memory

Input /

Output

15-447 Computer Architecture Fall 2008 ©

Focusing on CPU & Memory

Register File

ALU

Datapath

IR

PC

CPU Memory

Data

AddressControl

Unit

15-447 Computer Architecture Fall 2008 ©

The Datapath

A load / store machine (RISC), register – register where access to memory is only done by load & store operations.

Source 1

Register File

ALU

Source 2

Destination

Result

Control

: (Register File)

15-447 Computer Architecture Fall 2008 ©

Register File Design

# Bits / Register = 8 => 8 MUXs

# Registers = 4 => 4 to 1 each MUX

4->1 MUX

control

4->1 MUX

4->1 MUX

s1_bus s2_busReg A Reg B

Reg C Reg D

15-447 Computer Architecture Fall 2008 ©

A0 A1 A2 A3 C0 C1 C2 C3

MUX4 -> 1

A0B0C0D0

MUX4 -> 1

A1B1C1D1

MUX4 -> 1

A2B2C2D2

MUX4 -> 1

A2B2C2D2

B0 B1 B2 B3

MUX4 -> 1

A0B0C0D0

MUX4 -> 1

A1B1C1D1

MUX4 -> 1

A2B2C2D2

MUX4 -> 1

A2B2C2D2

D0 D1 D2 D3

S0 S1 S2 S3s0 s1 s2 s3

Register File: 4 registers, 4 bits / register

Control bits Control bits

15-447 Computer Architecture Fall 2008 ©

The Datapath

The Result of the operation performed in the ALU needs to be stored in a register.

Source 1

Register File

ALU

Source 2

Destination

Result

Control

15-447 Computer Architecture Fall 2008 ©

Destination: 2 registers / 3-bits per register

DeMux3DeMux2DeMux1

Register 1 Register 2

Control

Result from ALU to Destination Bus

15-447 Computer Architecture Fall 2008 ©

Quiz°Draw your design of a register file:

• Three registers, each is 2-bits wide

• Two source buses, one destination bus

°How many & what size:• Muxes did you use?

• Demuxes did you use?

°Total number of control lines?

15-447 Computer Architecture Fall 2008 ©

The Datapath

A load / store machine (RISC), register – register where access to memory is only done by load & store operations.

Source 1

Register File

ALU

Source 2

Destination

Result

Control

: (ALU)

15-447 Computer Architecture Fall 2008 ©

Simple ALU Design

control

s1_bus

dest_bus

Add/Sub

s2_bus

Shift/Logic

16 to 8 MUX

15-447 Computer Architecture Fall 2008 ©

How about the Control?

Register File

ALU

Datapath

IR

PC

CPU Memory

Data

AddressControl

Unit

15-447 Computer Architecture Fall 2008 ©

The Control Unit

Control Logic

15-447 Computer Architecture Fall 2008 ©

A simple device

Build a custom controllerfor a vending machine.

We could use a generalpurpose processor, butwe might save moneywith a custom controller.

Take coins, give drinks

15-447 Computer Architecture Fall 2008 ©

Input and Output

Inputs:

10 drink selectors

coin trigger

refund button

Outputs:

10 drink release latches

Coin refund latch

10 pressure sensors

15-447 Computer Architecture Fall 2008 ©

Operation of Machine

Accepts quarters only

Once we get the money, they can select a drink.

If they want a refund,release any coins inserted

All drinks are $0.75

No free drinks!

No stealing money!

15-447 Computer Architecture Fall 2008 ©

Building the controller°Finite State

• Remember how many coins have been put in the machine and what inputs are acceptable

°Read-Only Memory (ROM)• Define the outputs and state transitions

°Custom combinational circuits• Reduce the size (and therefore cost) of the controller

15-447 Computer Architecture Fall 2008 ©

Finite State Machines°A Finite State Machine (FSM) consists of:

K states: S = {s1, s2, … ,sk}, s1 is initial state

N inputs: I = {i1, i2, … ,in}

M outputs: O = {o1, o2, … ,om}

Transition function T(S,I) mapping each current state and input to next state

Output Function P(S) [or P(S,I)] specifies output

15-447 Computer Architecture Fall 2008 ©

Two common state machines

°Moore machine

output function based on current state only

°Mealy machine

output function based on current state and current input

see P&H page B-35

15-447 Computer Architecture Fall 2008 ©

FSM for vending machine

0 coins 1 coin

3 coins 2 coins

Coin trigger

Refund button

Drink Select

Ran out of specific drink selection

15-447 Computer Architecture Fall 2008 ©

FSM for addition in Load/Store Architecture

Fetch Decode

Store result ALU Execute

Store result in R1

Send signal to ALU to perform addition

Fetch Instruction (Add R1, R2) Registers R1 and R2

Fetch next instruction

15-447 Computer Architecture Fall 2008 ©

D Q

Implementing FSM

D Q Current state

Implementtransitionfunctions

(using a ROM andcombinational circuits)

InputsOutputs

Next state

2-bit state

15-447 Computer Architecture Fall 2008 ©

The Control Unit When Add is Exechting

Control Logic

15-447 Computer Architecture Fall 2008 ©

The Control Unit When Add is Exechting

Control Logic

Instruction

The control Turns on

the requiredlines. In theCase of add,Ex: ALU OP,ALU source,

Etc.

15-447 Computer Architecture Fall 2008 ©

ROMs and PROMs

° Read Only Memory• Array of memory values that are constant

• Non-volatile

° Programmable Read Only Memory• Array of memory values that can be written exactly

once (destructive writes)

° You can use ROMs to implement FSM transition functions

• ROM inputs: ROM address ; current state + primary inputs

• ROM outputs: ROM data ; next state + primary outputs