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2005 Packaging Roadmap 2005 Packaging Roadmap Overview Overview

Juergen Wolf, Fraunhofer IZMJoe Adams, Skyworks

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NEMIOptoelectronic

s TWG

NEMIOptoelectronic

s TWG

Optoelectronics and Optical Storage

Interconnect Substrates—

Ceramic

InterconnectSubstrates—

Organic

Magnetic and Optical Storage

Supply ChainManagement

Displays

Semiconductors

NEMI Roadmap

NEMIProduct Life-

Cycle Information

ManagementTWG

NEMIProduct Life-

Cycle Information

ManagementTWG

NEMIMass Data

Storage TWG

NEMIMass Data

Storage TWG

NEMI / IPCInterconnect

TWG

NEMI / IPCInterconnect

TWG

NEMI / SIAPackaging

TWG

NEMI / SIAPackaging

TWG

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Semiconductor Technology Roadmap Semiconductor Technology Roadmap Jisso Technology RoadmapJisso Technology Roadmap

ITRSITRS vs.vs. JJTRJJTR

Jisso(� � )

JJTR

PKG Electronics proucts

PWB Materials

Assy M/C

Environ-metal

TestInter-connect

Component

YEDesign

TESTPI,FI

Inter-connect

Litho

Device

FEP

ES&HM&S

JEITASIRIJSeleteSTARCASETJSPMI

SEAJJPCAJIEPEDA������

METITRS/STRJ

Des ign/Simm.

ITRSITRS vs.vs. JJTRJJTR

Jisso(� � )

JJTR

PKG Electronics proucts

PWB Materials

Assy M/C

Environ-metal

TestInter-connect

Component

YEDesign

TESTPI,FI

Inter-connect

Litho

Device

FEP

ES&HM&S

JEITASIRIJSeleteSTARCASETJSPMI

SEAJJPCAJIEPEDA������

METITRS/STRJ

Des ign/Simm.

ITRS : International Technology Roadmap for SemiconductorsJJTRC: Japan Jisso Technology Roadmap Council

Source: JJTR2005

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Assembly and Packaging RoadmapAssembly and Packaging RoadmapAssembly and Packaging Roadmap

• Packaging has become the limiting element in system cost and performance

• The Assembly and packaging role is expanding to include system level integration functions.

• As traditional Moore’s law scaling become more difficult innovation in assembly and packaging can take up the slack.

Source: ITRS

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Consumer Market ImperativesConsumer Market Imperatives…………..

PowerPower

WeightWeight

SizeSize

Functionality & Reliability

Cost

5

New Market Driver

Size SmallLarge

Den

sity

High

Low

Ubiquitous Equipment

Automotive Electronics

Digital AV Equipment

Digital Video Comcorder

Portable AV Equipment

Flat Panel Display

Notebook PC

Digital Still Camera

High Density Portable

Mobile Digital AV

Home Digital AV

Cellular

Set Top Box

Size SmallLarge

Den

sity

High

Low

Ubiquitous Equipment

Automotive Electronics

Digital AV Equipment

Digital Video Comcorder

Portable AV Equipment

Flat Panel Display

Notebook PC

Digital Still Camera

High Density Portable

Mobile Digital AV

Home Digital AV

Cellular

Set Top Box

Source: JJTR2005

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Major Packaging Industry TrendsMajor Packaging Industry Trends

• Volume drivers have shifted to consumer electronics • Wafer level packaging technologies is taking off • Chip Scale Packages are beginning to replace older

leadframe technologies due to cost, size, and performance advantages

• System In Package has become a mainstream technology

• The contract assembly and test business has started to consolidate driven by a more competitive environment

• The EMS and Assembly and Test overlaps are increasing • Improvements in cost are not keeping pace with pricing

pressure

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Shifts In Packaging TechnologyShifts In Packaging Technology

World Wide Semiconductor Package Volume

0

20

40

60

80

100

120

140

160

180

2003 2004 2005 2006 2007 2008

Billio

ns

DCAWLPQFPSO SIPBGAQFNDIP/SOT

Source: Electronic Trends Publications and Prismark

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Wafer Level PackagingWafer Level Packaging

Redistribution CSP

Au

AuSn

PbSn

SnAg

BumpingLarge wafer size

Low costLead free solder

Fine pitchThin interconnects

WL – IPD-CSP WL-CSP (Memory)

8.3 x 8.5 mm²

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WL - Optical Applications

Ball Grid Array on the backside with Silicon Via Contacts

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Thinned Wafers / DieThinned Wafers / Die

(a) Rolled Wafer

1010µµm Wafer Thicknessm Wafer Thickness

(b) Light Transparency

Source: Shinko Electric Industry

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Industry Challenges in the Next Five YearsIndustry Challenges in the Next Five Years

• Tools and methodologies to address chip and package co-design Mixed signal co-design and simulation (SI, Power, EMI)For transient and localized hot spots - simulation of thermal mechanical

stresses, thermal performance and current density in solder bumps • Close the Gap between chip and substrate interconnect density

Increased wireability and dimensional control at low cost Higher temperature stability and lower moisture absorptionTCE and Modulas better matched to low K flip chip requirements

• Impact of Cu/low k on PackagingDirect wire bond and UBM/bump to Cu to reduce cost Lower TCE and modulus substrates to reduce die level stress in flip chip Lower strength in low k which creates a weaker mechanical structure

• Wafer Level PackagingI/O pitch between 250um - 400um less than 100 I/O Solder joint reliability and cleaning processes for low stand-offWafer thinning and handling technologiesCompact ESD structures

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Package Technology RequirementsPackage Technology Requirements

Year of Production 2004 2005 2006 2007 2008 2009

Low-cost, hand-held and memory 0.30–.53 .27–.50 .26–.48 .25–.45 .23–.43 .22–.41Cost-performance .71–1.24 .67–1.17 .64–1.11 .61–1.05 .58–1.00 .55–.96High-performance 1.88 1.78 1.69 1.61 1.52 1.45Harsh 0.32–2.88 0.29–2.60 0.26–2.33 0.25–2.11 0.23–2.00 0.22–1.90

Low-cost 100 100 100 100 100 100Cost-performance 140 140 140 140 140 140High-performance 310 310 310 310 310 310Harsh 100 100 100 100 100 100

Low-cost (Watts) [5] 2.7 2.8 3 3 3 3Cost-performance 0.6 0.65 0.7 0.74 0.79 0.83High-performance 0.51 0.54 0.58 0.61 0.64 0.64Harsh 0.16 0.16 0.18 0.18 0.2 0.2

Low-cost 122–500 134–550 144–600 160–660 180–720 180–800Cost-performance 500–1600 550–1760 550–1936 600–2140 600–2400 660–2800High-performance 3000 3400 3800 4000 4400 4600Harsh 500 550 600 660 720 780

Cost per Pin Minimum for Contract Assembly [1,2] (Cents/Pin)

Chip Size (mm 2 ) [3]

Maximum Power (Watts/mm 2 ) [4]

Package Pincount Maximum [6][7]

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Package Technology RequirementsPackage Technology Requirements

Minimum Overall Package Profile (mm) 2004 2005 2006 2007 2008 2009Low-cost 0.5 0.5 0.5 0.5 0.5 0.5Cost-performance 0.8 0.8 0.8 0.8 0.65 0.65High-performance N/A N/A N/A N/A N/A N/AHarsh 0.8 0.8 0.8 0.8 0.8 0.8

Low-cost 552/5200 607/3865 668/4251 735/4676 800/5000 830/5150Cost-performance 3990 5170 5630 6740 — —High-performance 3990 5170 5630 6740 — —Harsh 80 88 96 106 116.6 128.26

Low-cost 100 100 100 100 100 100Cost-performance (for multi-drop nets) 533 600 667 733 800 800High-performance (for differential-pair point-to-point nets)

2500 3125 3906 4883 6103 7629

Harsh 80 88 96 106 106 115

Performance: On-Chip (MHz)[8]

Performance: Chip-to-Board for Peripheral Buses (MHz) [9]

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Die to Package Interconnect RequirementsDie to Package Interconnect RequirementsYear of Production 2004 2005 2006 2007 2008 2009 2010 2012 2013 2015 2016 2018Wire bond pitch - ball 40 35 35 30 30 25 25 25 25 25 25 25Wire bond pitch -wedge 30 30 25 20 25 20 20 20 20 20 20 20TAB 35 30 30 25 25 25 20 20 20 15 15 15Flip chip area array* 150 130 130 120 110 100 90 90 90 80 80 70Peripheral flip chip Stud Bump 60 40 40 30 30 20 20 20 20 15 15 15Note: Validation for 100 um pitch required

Package I/O PitchesPackage I/O PitchesBGA Solder Ball Pitch (mm) 2004 2005 2006 2007 2008 2009 2010 2012 2013 2015 2016 2018Low-cost and hand-held 0.8 0.65 0.65 0.65 0.65 0.65 0.5 0.5 0.5 0.5 0.5 0.5Cost-performance 0.8 0.65 0.65 0.65 0.65 0.65 0.5 0.5 0.5 0.5 0.5 0.5High-performance 1 1 0.8 0.8 0.8 0.8 0.65 0.65 0.5 0.5 0.5 0.5Harsh 0.8 0.8 0.8 0.65 0.65 0.65 0.65 0.5 0.5 0.5 0.5 0.5Chip Scale Package Pitch 0.4 0.3 0.3 0.2 0.2 0.2 0.2 0.15 0.15 0.15 0.1 0.1

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Definition for SystemDefinition for System--inin--PackagePackage

“System in Package is characterized by any combinationof more than one active electronic component

of different functionality plus optionally passives and other devices like MEMS or optical components assembled

preferred into a single standard packagethat provides multiple functions

associated with a system or sub-system.”

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SoC vs. System in PackageSoC vs. System in Package

Cos

t / fu

nctio

n tim

e to

mar

ket

System on Chip

SiP and 3D PackagingMEMS

Bio-InterfacePower supply

System complexity

Source: Fraunhofer IZM

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Systems Integration in the Cellular Phone

Tx�Rx Circuit•Smaller & lower power consumption of analog circuit•Decrease of # of mounted components

Camera Circuit•Smaller•Lower power consumption•One unit of lens and control circuit

DSP�CPU�BB•Dual CPU: Transmission /Application

Memory Circuit•Memory area for downloaded software•Higher memory capacity

Outer Interface Circuit•Bluetooth, USB interface

•MP3, GPS interface•Memory Card interface

LCD Circuit•Larger display, Color display•Lower power consumption•Higher resolution

Plug In Memory Card•Smaller, thinner

•Higher memory capacity

Power Supply Circuit

•Smaller Size

Embedded Antenna•Smaller�Stability of signal•Influence on the human body

Source: H.Ueda�JEITA

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SiP in the Cellular PhoneSiP in the Cellular Phone

Source: T. Sakurai, University of Tokyo

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SiP SiP –– Stacked Die Stacked Die

Die thickness : 60 umSubstrate (BT) thickness : 130 umSolder ball Stand-off : 50 um

Substrate Base Substrate Base SiPSiP ( up to 7/ 8 die)( up to 7/ 8 die)

Die thickness : 60 umSubstrate (BT) thickness : 130 umSolder ball Stand-off : 50 um

Substrate Base Substrate Base SiPSiP ( up to 7/ 8 die)( up to 7/ 8 die)

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SiP CategoriesSiP Categories

Side by SidePlacement

StackedStructure

EmbeddedStructure

stacked die

PoP

+ passive components

PiP

Substrate:organic laminate, ceramic, glas, silicon, leadframeChip Interconnection:wire bond and/or flip chip

chip to chip / wafer

flip chip, face to facethrough siliconWL 3D stackwafer to wafer (W2W)

Chip / Component Configuration

Chip in PCB / polymer single layermulti-layer 3D stack

WL thin chip integration single layer

integrated into the substratediscrete (CSP, SMD)

wire bond, WB +FC

stacked functional layers

Technology

Source: ITRS

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SiP – Integrated Active and Passive Devices (IPAD™)SiP SiP –– Integrated Active and Passive Devices (IPADIntegrated Active and Passive Devices (IPAD™™))

Heat dissipation, Shielding, Mechanical protection …

MEMS, Opto,etc

IC’s BigPassives Discretes

Bumping ? Wiring ? Soldering ? Stacking ?

IPADTM

High density RLCC > 100 nF/mm²

L > 100 nH

ConductiveVias

RedistributionInsulated

zone

RLCC<35 nF/mm²

L < 10 nH

Source: ST Microelectronics,

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System In Package RoadmapSystem In Package Roadmap

Year of Production 2004 2005 2006 2007 2008 2009 2010 2012 2013 2015 2016 2018

Digital networks- max I/O 2600 2900 3000 3200 3500 3500 3500 3500 3500 3500 3500 3500

RF products - max I/O 150 200 200 200 200 200 200 200 200 200 200 200

Max number of stack die 6 7 8 8 8 8 8 8 8 8 8 8

Max number die in Module 10 12 12 12 12 12 12 12 12 12 12 12

Minimum Component size in. 0201 0201 01005 01005 01005 01005 01005 01005 01005 01005 01005 01005

Die Pad pitch - wirebond 40 35 35 30 30 25 25 25 25 25 25 25

Die pad pitch - flipchip 150 130 130 120 110 100 90 90 80 80 70 70Embedded Passives in Laminate L L CL CL CL CL CL CL CL CL CL CLEmbedded Passives in Ceramic R, L, C R, L, C R, L, C R, L, C R, L, C R, L, C R, L, C R, L, C R, L, C R, L, C R, L, C R, L, C

MSL Level 2a 2 2 2 2 2 2 2 2 2 2 2

Mx Reflow temp C 260 260 260 260 260 260 260 260 260 260 260 260

System In Package Requirements

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0.00

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

2.25

2.50

2.75

3.00

RF Cell

ular

Digital

WLAN/Blueto

othPower

Supply

Automotive

Imag

e/Disp

layOptoele

ctronics

Other

SiP

Uni

ts (B

illio

ns)

2003

2007

Handsets51%

Satellite15%

Other4%

Infrastructure30%

Projected growth for SiP in key applications markets Projected growth for SiP in key applications markets 20032003--20072007

Sources: Prismark .

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ConclusionsConclusions

• The industry growth will be driven by consumer and machine to machine based applications going forward

• SIP and WLP technologies will be a key element of this growth and are shifting the industry research focus

• To improve R&D return and effectiveness the industry needs to increase collaboration through partnerships and shared R&D

• Emerging devices will required a new set of packaging technologies that allow devices to interact with the environment instead of being protected from it