2009 ITRS Emerging Research Devices Working Group Face-to-Face Meeting

Work in Progress --- Not for Publication1 ERD WG 12/06/08 & 12/14/08

2009 ITRS Emerging Research Devices

Working Group

Face-to-Face Meeting

Jim Hutchby - FacilitatingSan Francisco Hilton & Towers Hotel

Franciscan A RoomSan Francisco, CA

Sunday Dec 14, 20088:00 a.m. – 5:30 p.m.


2009 ITRS Emerging Research Devices

Working Group

Face-to-Face Meeting

U-In Chung & Jim Hutchby - FacilitatingCOEX InterContinental Hotel

Room Moderato ISeoul, Korea

Saturday Dec 6, 20089:00 – 17:30


Hiroyugi Akinaga AIST Tetsuya Asai Hokkaido U. Yuji Awano Fujitsu George Bourianoff Intel Michel Brillouet CEA/LETI Joe Brewer U. Florida John Carruthers PSU Ralph Cavin SRC U-In Chung Samsung Byung Jin Cho KAIST Sung Woong Chung Hynix Shamik Das Mitre Erik DeBenedictis SNL Simon Deleonibus LETI Kristin De Meyer IMEC Michael Frank AMD Christian Gamrat CEA Mike Garner Intel Dan Hammerstrom PSU Wilfried Haensch IBM Tsuyoshi Hasegawa NIMS Shigenori Hayashi Matsushita Dan Herr SRC Toshiro Hiramoto U. Tokyo Matsuo Hidaka ISTEK Jim Hutchby SRC Adrian Ionescu ETH Kohei Itoh Keio U. Kiyoshi Kawabata Renesas Tech Seiichiro Kawamura Selete Rick Kiehl U. Minn Suhwan Kim Seoul Nation U. Hyoungjoon Kim Samsung

Atsuhiro Kinoshita Toshiba Dae-Hong Ko Yonsei U. Hiroshi Kotaki Sharp Atsuhiro Kinoshita Toshiba Atsuhiro Kinoshita Toshiba Franz Kreupl Qimonda Nety Krishna AMAT Zoran Krivokapic AMD Phil Kuekes HP Jong-Ho Lee Kyungpook Nation U. Lou Lome IDA Hiroshi Mizuta U. Southampton Murali Muraldihar Freescale Fumiyuki Nihei NEC Ferdinand Peper NICT Yaw Obeng NIST Dave Roberts Air Products Kaushal Singh AMAT Sadas Shankar Intel Satoshi Sugahara Tokyo Tech Shin-ichi Takagi U. Tokyo Ken Uchida Toshiba Yasuo Wada Toyo U. Rainer Waser RWTH A Franz Widdershoven NXP Jeff Welser NRI/IBM Philip Wong Stanford U. Kojiro Yagami Sony David Yeh SRC/TI In-Seok Yeo Samsung In-K Yoo SAIT Peter Zeitzoff Freescale Yuegang Zhang LLLab Victor Zhirnov SRC

Emerging Research Devices Working Group


Emerging Research Devices Working Group Dec. 6th Seoul FxF Meeting Objectives

Meet with Korean ERD Working Group (Morning) Discuss International Collaboration Processes in 2009 ERD-Korean WG Inputs

2007 Chapter Review – any Issues? 2009 Scope and Content of Chapter Other topics?

Meet with ERM (Afternoon) Discuss ERM/ERD Interfaces & Collaboration in 2009 Review Proposed Materials & Device Topics for 2009 Discuss III-V and Ge Channel Replacement Materials? Discuss new Potential Solutions section on “Carbon-based Nanoelectronics” Devices in ERD-PIDs transition table - any entries limited by materials?


Emerging Research Devices Working Group Dec. 6nd Seoul FxF Meeting – Morning Agenda

9:00 Welcome and Introductions Drs. U-In Chung &

J. Hutchby

9:15 Organization of Korean ERD & Dr. U-In ChungProposals from each part

9:20 ERD Logic part Prof. Jong-Ho Lee

9:50 ERD Memory part Dr. In-Seok Yeo

10:20 Break

10:50 ERD Architecture part Prof. Soo-Hwan Kim

11:20 Emerging Research Materials Prof. Dae-Hong Ko

12:00 Lunch


ERD/ERM Working Groups Joint Meeting Dec. 6th Seoul FxF Meeting – Afternoon Agenda

13:15 Review Arch’ture Approaches & Issues TBA13:45 Review Memory Device Issues TBA/V. Zhirnov

14:30 Review Logic Device Issues G. Bourianoff15:15 Break 15:30 Review/summarize ERM Workshops M. Garner

♦ Workshops♦ ERM Tables

16:30 Review Carbon-based Nanoelectronic M. Garner materials issues

17:00 Review proposed interaction with ERD M. Garner and Working Group J. Hutchby

17:30 Adjourn


Review Feedback on 2007 ERD Chapter Review ERD Chapter Organization for 2009

Leadership Mission and Scope Deliverables, Timeline and Events Chapter page count and page allocation Operating Process and Meetings Technology Entries Inclusion Criteria

Broadly inclusive Maturity Metric (current publications)

Kick off 2009 ITRS ERD Chapter Preparation Dec. 14th San Francisco FxF Meeting Objectives


Review ERD Chapter Content for 2009 Major Technical Sections

Architectures Logic Devices

Selected Emerging Technologies Compliment or Extend CMOS Beyond CMOS

Potential Solutions Memory Devices

Selected Emerging Technologies Selected Potential Solutions

Critical Review and Guiding Principle Sections Critical Review

Selected Memory Devices Selected Logic Devices

Guiding Principles Review ERD Decisions & Action Items for 2009

Kick off 2009 ITRS ERD Chapter Preparation Dec. 14th San Francisco FxF Meeting Objectives


7:30 Continental Breakfast 8:00 Introductions 8:10 Review meeting objectives and agenda J. Hutchby 8:20 Review ERD Organization for 2009 J. Hutchby

Leadership Mission/Charter and Scope Deliverables, Timeline, and Events Chapter Page Count and Page Allocation Operating Process and Meetings

9:00 Review status of ERD J. Hutchby Chapter Status & Organization 2007 ERD Chapter Feedback (12/07) Decisions for 2009

10:00 Break

Kick off 2009 ITRS ERD Chapter Preparation Dec. 14th San Francisco FxF Meeting Agenda


10:15 Review ERD Workshops and DiscussStatus of Materials, Devices & Architectures

10:15 Materials M. Garner11:00 Memory Devices V. Zhirnov

12:15 Lunch (Continue Discussion)12:45 Logic Devices G.

Bourianoff Complement or extend CMOS Beyond CMOS

2:15 Architectures R. Cavin 3:15 Break 3:30 Discuss Critical Review & Guiding Principle Sections

3:30 Critical Review J HutchbyMemory DevicesLogic Devices

4:30 Guiding Principles J. Hutchby 5:00 Wrap up, Review Decisions and Actions Required J. Hutchby 5:30 Adjourn

Kick off 2009 ITRS ERD Chapter Preparation Dec. 14th San Francisco FxF Meeting Agenda


Mission/Charter of ERD ChapterOn behalf of the 2009 ITRS, develop an Emerging

Research Devices chapter to -- Critically assess suitability and maturity of novel

approaches/technologies for Information Processing technology intended to complement or extend ultimate CMOS

Identify the most promising approach(es) to Information Processing technology to be implemented by 2022

To offer substantive input and guidance to – Global research community Relevant government agencies Technology managers Suppliers


Scope of ERD Chapter

Integrated emerging research memory, logic and new architecture technologies enabled by supporting -- Materials and process technologies Modeling and simulation Metrologies

Technology Entries will be selected based on level of published research activity, credibility and progress Should show significant maturity in research domain Further adoption limited by research issues


Scope of ERD Chapter Criteria for Including Technology Entries

Research Devices and Architectures – Published by 2 or more groups in archival literature and

peer reviewed conferences, or Published extensively by 1 group in archival literature

and peer reviewed conferences


Scope of ERD Chapter Fundamental Requirements for CMOS Extension

Information Processing Technologies

Provides a valuable macro function more efficiently than CMOS

Energy restorative process (e.g. gain)Functionally interfaceable with CMOSAt or above room temperature operationMinimum energy per functional operationMinimum, scalable cost per function


Scope of ERD Chapter Fundamental Requirements for Beyond CMOS

Information Processing Technology Entries

Information processing throughput orders of magnitude beyond ultimately scaled CMOS

Energy restorative process (e.g. gain)Functionally compatible with CMOSAt or above room temperature operationReduced energy per functional operationReduced, scalable cost per function


Proposed 2009 ERD Working Group OrganizationERD Function Leader

Chapter Chair – North America Hutchby Chapter Co-chair – Europe TBD Chapter Co-chair – Japan ERD Hiramoto Chapter Co-chair – Korea ERD Chung Memory Zhirnov Logic Bourianoff Architecture Cavin Editorial Team Hutchby, Bourianoff, Cavin,

Chung, Garner/Herr, Hiramoto, Zhirnov

ITRS Liaisons– PIDS Ng, Hutchby– FEP Herr– Modeling & Simulation Shankar– Materials Shankar– Metrology Herr– Design Yeh/Bourianoff– More than Moore Brillouet


2009 ITRS/ERD Major Deliverables and Timeline

ERD Chapter due August 21, 2009Major Tasks and Time Line Outlines for Memory, Logic, Architecture, Mat’l March 18 Technology Requirements Tables April 6 Guiding Principles Section June 1 Draft Text Completed

Memory, Logic, Architecture, Material July 6 Functional Organization & Critical Review July 20 Scope, Difficult Challenges, etc. July 27 Chapter Completed August 21 Chapter Frozen Sept. 15

Major Face-to-Face Meetings in 2009 ITRS/ERD Meeting near Brussels, Belgium March 18 ITRS/ERD Meeting at Semicon West (SF, CA) July 12 ITRS/ERD Meeting near Hsinchu, Taiwan Nov. 30


2008 ERD/ERM Workshops

Workshop topic Date Location Meeting Specific technology entries

Emerging Research Memory Devices

April 2 2008

Bonn, Germany

ITRS Spring meeting

- Performance analysis for the various types of memories - Magnetic Race-Track Memory - Nanowire Phase-Change Memory - Polymer/Macromolecular Memory

Emerging Research Architectures

July 10-11 2008

San Francisco, CA, USA

Semicon West

- Chip Multiprocessors - Memory Architectures - Morphic Computational Architectures -Turing-Heisenberg Rapprochement

Maturity Eval for selected ‘Beyond CMO'S’ Technologies

July12-13, 2008

San Francisco, CA, USA

Evaluate 7 ERD Logic technologies for their readiness for accelerated development

Emerging Research Logic Devices

Sept. 22 2008

Tokyo, Japan

SSDM

- Nonlinear response functions - Devices for “functional diversification”? - Optimum circuit architectures associated with

novel devices

Emerging Research Materials

Nov. 10 2008

Austin, TX, USA

MMM*

Materials for Spintronic Devices - Energetics - Transitions - Time scales - Interactions with external fields

Emerging Research Materials

March 2009

Tokyo, Japan Strongly Correlated Electron Materials

* 53rd Magnetism and Magnetic Materials Conference

Done

Done

Done

Done

Done


Draft ERD Chapter Outline Scope (1 page) Difficult Challenges (1) Taxonomy Chart (1) Devices

Memory Devices (15) Logic Devices (15)

Architectures (8) Critical Assessment (6) Fundamental Guiding Principles (3) Total Pages (50)

DRAFT


Feedback on 2007 ERD Chapter Overall Comments

Increase involvement of international members – strengthen ties between US – EU – Asia. Requires good balance of representing members from these three regions.

Mission of ERD is not clear cut to universities – clearly state the mission in the introduction.

Need more detailed discussion of key messages and issues between ERD and ERM

To what extent and how does ERD/ERM deal with More than Moore? Need a metric to gauge the potential of each Technology Entry to be

disruptive. Is a Technology Entry being limited by Fundamental Limits or a

technologically limited research gap? ERD needs to maintain a dialog with the Systems Drivers Chapter Should ERD continue to include a failing Technology Entry?


Feedback on 2007 ERD ChapterEmerging Research Memory Devices

♦ Transfers Engineered Tunnel Barrier Memory to PIDS and FEP Keep the Ferroelectric FET Memory Technology in ERD Include STT RAM as a new entry. Given progress, should we include

STT RAM in a new Potential Solution Table for Memory Technologies?♦ Other comments

Re-combine the capacitive and resistive memory tables Discuss other materials (in addition to Pt/NiO/Pt) for Fuse/Anti-fuse

Memory Try to elucidate fundamental limits of Memory Devices Add a new row to memory table to include Storage Capacity Address Memory Architecture, perhaps in the Architecture Section Why do all the memory technology entries have for “Best Projected

Write Cycles” a value of 3E16 ? Include scaling projections for all Memory Technology Entries The Memory Group is preparing a single reference document containing

scaling projections and citations


Feedback on 2007 ERD ChapterEmerging Research Logic Devices (1/3)

♦ Transfers proposed III-V Alternate Channel Materials to PIDS/FEP and Low Dimensional Materials to PIDS/FEP Move Molecular Devices to the Transition Table. Include Band-to-Band Tunneling Device category in Table 1. Move RTD out of Table 2 to Transition Table

♦ Other comments The comprehensive review with references is important Like having two tables to represent the traditional, digital Boolean device

applications and the new table to represent new, perhaps analog, applications of emerging research devices.

Include chart entitled “Evolution of Extended CMOS” from Japan ERD The best demonstrated parameters are obtained from different devices. Is

it possible to obtain them simultaneously on one device? We should include a note to this effect.

Define “Switching Speed” and “Circuit Speed”



♦ Other comments Discuss “Spin Gain Transistor” and “Spin Torque Transistor” in text.

“Single Spin device” is not in the table Should we constrain Logic Technology by availability of Memory Tech? Should use term “high mobility/high velocity” instead of “high mobility” Improve linkages to the Architecture Section and to the System Drivers

Chapter. Increase emphasis on Table 2 while maintaining Table 1. Place a

stronger emphasis on non-linear response functions. Think about how to amend Table 1 to differentiate “Beyond CMOS” devices.

Separate Spin FETs from Spin State Devices (Spin transport without charge transport) and evaluate as separate categories.

Divide Table 1 into 2 tables – one for CMOS extension and the other for Beyond CMOS?

Include Spin Wave Bus in Table 1?



♦ Other comments Keep SETs in Table 2, Alternative Information Processing Technologies Change Multiferroic Tunnel Junction Devices to Multiferroic Switching

Device and keep in Table 2.


Feedback on 2007 ERD ChapterEmerging Research Architectures

♦ Transfers proposed Should we continue the “Homogeneous Multicore Section

♦ Other comments Morphic Architectures might include: Associative Memory Processor;

Cellular Nonlinear Networks; and Neuromorphic LSIs for collision avoid.

Should Emerging Memory Architectures be addressed in this Section? Recommend evaluation of integrating energy sources, storage memory,

low-power sensors, and computational engines Consider using biological concepts for new architectures to obtain high

energy efficiency. Consider integration of biological elements


Feedback on 2007 ERD ChapterCritique Section for Memory &Logic Tech Entries♦ Comments

Important section to survey technology trend of emerging research devices Standard Deviation is very helpful How and why were the Evaluation Criteria chosen? Need much more discussion of the data. How can we critically review Architectural approaches? Should we try? Should we use different colors because our use of red, white and yellow has

a different meaning than the use of these colors in other chapters of the ITRS.

We need to sure our Critique Section analysis is consistent with the text for the Technology Entries, e.g., we need to be sure the highs and lows in the Critique are addressed as strengths and research gaps in the text sections.


Feedback on 2007 ERD ChapterScope, Difficult Challenges, Taxonomy & Guiding Principles

♦ Scope: In general the Scope is very good. However, the statement “…, CMOS certainly will provide a platform processing technology for sometime beyond the end of dimensional scaling, exploiting the notion that the ultimately scaled MOSFET is a nearly ideal electronic charge-based device” is a rather strong statement. Is it too strong? Should we say something about the technology “cost” in the Scope?

♦ Difficult Challenges: The Difficult Challenges are very good.♦ Guiding Principles

The five original Guiding Principles are very good. The sixth Guiding Principle related to “Architecture” needs clarification as

to whether it only applies to “Beyond CMOS” or to both “Beyond CMOS” and CMOS integrated with Beyond CMOS devices? That is do we address: (1) New architectures with conventional devices and/or (2) New architectures with beyond CMOS devices on CMOS infrastructure?.


Decisions for 2009 Chapter

♦ Memory– Include device structural aspects of the new NW PCRAM in ERD with a summary

of the materials issues. Include more materials information in ERM on this topic.

– Include the Spin Torque Transfer MRAM in ERD/ERM.

– Decide whether or not to include the “Magnetic Domain” or “Racetrack Memory” in ERD. We need to focus on P applications.

– We will keep nanomechanical memory in ERD Memory Table.

– Move the Ferroelectric Effects Tunneling Barrier Memory from the Electronic Effects Memory category to the Memory Transition Table

– Leave “Redox type” memories in the ERD. These are different than ionic cation migration effects memory.

– By categorizing using a physics-based system, a given material that exhibits 2 or more effects will be listed in each category.


Decisions for 2009 Chapter♦ Logic

– ERD/ERM recommends carbon-based nanoelectronics to include CNT, graphene for more resources and roadmapping for IRC as part of promising technologies for 5-10 years demonstration horizon

– Carbon-based nanoelectronics will be included in the 2009 ERD chapter via a two new Potential Solutions tables – for materials and for device issues.

– Seven potential technologies were considered:1. Carbon-based Nanoelectronics2. Collective spin3. Spin torque transfer4. Atomic and electrochemical metal5. CMOL/FPNI6. Single Electron Transistor7. NEMS


Comments 9/23/08• Does this include wires, vias, pkg technology, etc. – no

• For emphasis on Carbon-based NE Mike will connect w/ ESH Jim Jewett

• ERM Table of Applications & Proposed Structure – What is infrastructure mean?

– Equipment issue is important.

• Potential Solution Chart– Don’t tie down the time frame too rigidly

– Label chart by material or device structure

– Label as More Moore and Beyond CMOS

– Can we have a memory driver as we have a logic driver?

– Entries


Action Items (1/2)1. Consider to include in the 2009 ERD Chapter the new chart entitled

“Evolution of Extended CMOS” contributed by ERD Japan.Bourianoff In Process

2. Strengthen ties between US-EU-Asia. Requires good balance of representing members from three regions

Hutchby In Process

3. The best demonstrated parameters are obtained from different devices. Is it possible to obtain them simultaneously on one device? We should include a note to this effect.

Bourianoff, Zhirnov

4. Extend the Mission of ERD to include additional Research Vectors proposed by the Japan ERD WG. These are Numbers 1 – 4 listed in Item No. 1 above.

Bourianoff

5. Consider moving to PIDS in 2009: 1) III-V Alternate Channel Materials, and 2) Low Dimensional Materials. Discuss this with PIDS. (This discussion has begun.)

Bourianoff In Process

6. Make the mission of ERD clear. Make it more Globally justified. Hutchby

7. Organize an ERD Working Group in Korea In U. Chung In Process


Action Items (2/2)8. Bob Doering argued that the Critical Evaluation Chart gives the

wrong message;a.We need to re-think this chartb.This chart assigns a different meaning to red than is used by all the other ITRS chapters. The other chapters use red to highlight a major research gap.c.We should point the directions into which “critical path” research should be directed.

We need a way to distinguish a Fundamental Limit versus the Maturity of the Technology Entry

Hutchby

9. Need a dialog with the Design and Systems Drivers ITWG to address synergy between the two chapters.

Hutchby, Bourianoff, Yeh

In Process

10. Discuss/decide upon expanding scope to include Sensors, Actuators, and Power Sources to encompass More than Moore or Functional Diversification

Hutchby and Brillouet

11. Discuss other materials (in addition to NiO) for Fuse/Anti-fuse Memory Tech

Zhirnov & Garner

12. Plan Memory FXF Meeting in Germany for April 2, 2008. Include Memory Expert Panel.

Zhirnov Done

13. Write paper/proposal for NSF Funding for workshops. Hutchby/Zhirnov Done

14. Include Akinaga-san in Memory Working Group Zhirnov Done


Critical Review on Critical Assessment

1. Changes in Critical Assessment(2007<->2005)

2. Short Comments

F. Nihey (NEC)


2.31.92.61.41.62.41.52.3Molecular Memory

2.52.32.91.62.22.31.52.1Polymer Memory

2.82.62.81.92.22.02.52.5Insulator Resistance Change Memory

3.02.63.02.02.22.52.31.9Ferroelectric FET Memory

3.02.82.82.42.32.32.32.2Engineered Tunnel Barrier Memory

3.02.72.72.22.52.52.52.5Nano Floating Gate Memory

CMOS Architectural Compatibilit

y[H]*

CMOS Technologica

l Compatibilit

y[G]**

Operate Temp [F] ***

Operational

Reliability[E]

OFF/ON “1”/”0”

Ratio [D1]

Energy Efficien

cy[C]

Performance [B]

Scalability [A]

Memory Device Technologies(Potential)


2.52.32.91.62.22.31.52.1Polymer Memory

2.82.62.81.92.22.02.52.5Insulator Resistance Change Memory


3.02.82.82.42.32.32.32.2Engineered Tunnel Barrier Memory

3.02.72.72.22.52.52.52.5Nano Floating Gate Memory

CMOS Architectural Compatibilit

y[H]*

CMOS Technologica

l Compatibilit

y[G]**

Operate Temp [F] ***

Operational

Reliability[E]

OFF/ON “1”/”0”

Ratio [D1]

Energy Efficien

cy[C]

Performance [B]

Scalability [A]

Memory Device Technologies(Potential)

2.52.12.51.72.12.42.02.6


2.31.92.21.41.82.11.82.1Macromolecular Memory


Ionic Memory

CMOS Architectural Compatibility

CMOS Technological Compatibility

Operate Temperature

Operational Reliability

Off/On ratio

Energy Efficiency

PerformanceScalability

2.52.12.51.72.12.42.02.6


2.31.92.21.41.82.11.82.1Macromolecular Memory


Ionic Memory



Operate Temperature


Off/On ratio

Energy Efficiency


3

2

1

3

2

1

3

2

1

3

2

1

2.52.72.72.22.02.22.32.4

2.42.32.42.02.12.32.22.3Electron Injection Memory

2.22.22.91.92.52.41.91.7Nano Mechanical Memory

2.52.72.81.82.22.01.92.6Fuse/Anti-fuse Memory

Engineered Tunnel Barrier Memory



Operate Temperature


Off/On ratio

Energy Efficiency


2.52.72.72.22.02.22.32.4

2.42.32.42.02.12.32.22.3Electron Injection Memory

2.22.22.91.92.52.41.91.7Nano Mechanical Memory

2.52.72.81.82.22.01.92.6Fuse/Anti-fuse Memory




Operate Temperature


Off/On ratio

Energy Efficiency


3

2

1

3

2

1

3

2

1

3

2

1

ERD - Critical Assessment - Memory

2005 Edition

2007 Edition

Molecular

MolecularPolymer

Insulator Resistance ChangeFerroelectric FET

Engineered Tunnel BarrierNano Floating Gate

Engineered Tunnel Barrier

Fuse/Anti-Fuse

Nano Mechanical

Electron Injection

Ionic

Ferroelectric FET

Macromolecular


ERD – Critical Assessment - Logic

2005 Edition

2007 Edition

Engineered Tunnel Barrier

1.71.52.41.21.22.41.32.2Spin Transistor

1.71.72.52.01.51.91.31.4Ferromagnetic Devices

1.81.72.31.61.52.21.81.6Molecular Devices

2.12.11.91.21.42.61.51.9SETs

2.02.02.51.71.72.12.21.5Resonant Tunneling Devices

2.82.32.82.12.32.32.52.41D Structures (CNTs & NWs)

CMOS Architec

tural Compati

bility[H]*

CMOS Technologica

l Compatibilit

y[G]**

Room Temp

Operation

[F] ***


[E]Gain [D2]

Energy Efficiency

[C]

Performance [B]

Scalability [A]Logic DeviceTechnologies(Potential)

1.71.52.41.21.22.41.32.2Spin Transistor

1.71.72.52.01.51.91.31.4Ferromagnetic Devices


2.12.11.91.21.42.61.51.9SETs

2.02.02.51.71.72.12.21.5Resonant Tunneling Devices

2.82.32.82.12.32.32.52.41D Structures (CNTs & NWs)

CMOS Architec

tural Compati

bility[H]*

CMOS Technologica

l Compatibilit

y[G]**

Room Temp

Operation

[F] ***


[E]Gain [D2]

Energy Efficiency

[C]

Performance [B]

Scalability [A]Logic DeviceTechnologies(Potential)

2.31.82.52.02.32.52.22.4


1.51.61.41.31.22.31.12.4Single Electron Transistors

2.51.82.31.92.42.32.92.0Channel Replacement Materials

1D Structure


CMOS TechnologicalCompatibility

Operate Temperature


GainEnergy Efficiency


2.31.82.52.02.32.52.22.4


1.51.61.41.31.22.31.12.4Single Electron Transistors

2.51.82.31.92.42.32.92.0Channel Replacement Materials

1D Structure



Operate Temperature




3

2

1

3

2

1

3

2

1

3

2

1

1.31.22.12.01.51.71.31.2

1.31.31.31.41.72.31.41.7Spin Transistor

Ferromagnetic Devices



Operate Temperature




1.31.22.12.01.51.71.31.2

1.31.31.31.41.72.31.41.7Spin Transistor




Operate Temperature




3

2

1

3

2

1

1D Structure

1D Structure

Channel Replacement Mat.

Resonant TunnelingSingle Electron Tunneling

Single Electron Tunneling

Molecular

Ferromagnetic

Spin

MolecularFerromagnetic

Spin


Scalability Performance

Energy Efficiency

On/Off Ratio



Operational Temperature


3

2

1



Energy Efficiency

On/Off Ratio





3

2

1


2005 2007

Energy Efficiency

2


On/Off Ratio





3

1

Ferroelectric FET Memory

Energy Efficiency

2


On/Off Ratio





3

1


2005 2007

2


On/Off Ratio





3

1

Macromolecular Memory

2


On/Off Ratio





3

1


2005 2007

2


Energy Efficiency

On/Off Ratio





3

1

Molecular Memory

2


Energy Efficiency

On/Off Ratio





3

1

Molecular Memory

2005 2007

Evaluation - Memory


2


Energy Efficiency

Gain





3

1

1D Structure

2


Energy Efficiency

Gain





3

1

1D Structure

2005 2007

1

2


Energy Efficiency

Gain





3

Single Electron TransistorsCMOS Architectural Compatibility

1

2


Energy Efficiency

Gain





3

Single Electron TransistorsCMOS Architectural Compatibility


2


Energy Efficiency

Gain




3

1

Molecular Devices


2


Energy Efficiency

Gain




3

1

Molecular Devices

2005 2007

2005 2007

Evaluation – Logic (1/2)


1

2


Energy Efficiency

Gain





3


1

2


Energy Efficiency

Gain





3


2


Energy Efficiency

Gain





3

1

Spin Transistor

2


Energy Efficiency

Gain





3

1

Spin Transistor

Evaluation – Logic (2/2)


Critical review: memory

• How can be improved? Something missing? Other comments?

• Suggestions:– for each memory candidate, include very short comments

(arguments!) on the high-scored and low-scored features: main advantages versus open issues (when possible quantify comments).

– when applicable, for each memory candidate, short comment about level of concrete demonstration and/or prospects for NV, SRAM, DRAM

– identify contributors.


Critical Review: overview• Team: Jim Hutchby et al, Reviewer: Adrian M. Ionescu• Goals:

assess each Technology Entry (TE) for Memory & Logic compare/benchmark with/against:

- Si CMOS logic- memory technology to displace

provide the ERD community with and funding agencies with ERD WG collective view of the overall (long term) potential of each TE


Scalability PerformanceEnergy Efficiency

Off/On ratio


Operate Temperature




2.4 2.3 2.2 2.0 2.2 2.7 2.7 2.5

Fuse/Anti-fuse Memory 2.6 1.9 2.0 2.2 1.8 2.8 2.7 2.5

Nano Mechanical Memory

1.7 1.9 2.4 2.5 1.9 2.9 2.2 2.2

Electron Injection Memory

2.3 2.2 2.3 2.1 2.0 2.4 2.3 2.4

3

2

1

3

2

1

3

2

1

3

2

1

Critical Review – Memory (1/2)> 20

>18 - 20 < 16

>16 - 18


Scalability PerformanceEnergy Efficiency

Off/On ratio


Operate Temperature



Ionic Memory 2.6 2.0 2.4 2.1 1.7 2.5 2.1 2.5


1.8 2.0 1.9 2.1 1.7 2.6 2.3 2.3


2.1 1.8 2.1 1.8 1.4 2.2 1.9 2.3

Molecular Memory 2.4 1.7 2.4 1.4 1.3 2.2 1.8 1.9

3

2

1

3

2

1

3

2

1

3

2

1

Critical Review – Memory (2/2)> 20

>18 - 20 < 16

>16 - 18

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2009 ITRS Emerging Research Devices Working Group Face-to-Face Meeting

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