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A HIGH DATA TRANSFER RATE FREQUENCY SHIFT KEYING

DEMODULATOR CH IP FOR THE WIRELESS BIOMEDICAL IMPLANTS

Mavsam Ghovanloo

nd

Khalil Najafi

Center fo r Wireless Integrated M icrosystems

University

of

Michigan, 1301 Beal Ave.,

nn

Arbor, Michigan 48109-2122, USA

Tel: (734) 763-6650, Fax: (734) 763-9324, maysamgh@ engin.umich.edu

ABSTRACT

This paper describes a high-rate frequency shift keying

(FSK) data transfer protocol and demodulator circuit for

wirelessly operating biomedical implants in need of data transfer

rates above IMbitiSec. The demodulator circuit receives the

serial data bit stream from an

FSK

carrier signal in 2-2OMHz

range, which is used

to

power the implant through inductive

coupling. The circuitry has been des ime d and fabricated in the

University of Michig ans single m etal, dual-poly 3-LIm CM OS

process and has been tested fully functional.

1.

INTRODUCTION

Wireless operation is required for must of the biomedical

implantable circuits and many other emerging MEMS

applications to improve safety and enable stand-alone operation

for an unlimited time period. Many of these devices are powered

by inductive coupling in the centimeter range distance over the

skin

barrier. Tne most convenient way

to

transfer data to these

devices is

to

combine it with the electromagnetic power carrier

signal. Some

of

the biomedical implants, particularly those w ho

are interfacing with the central nervous system like cochlear

implants, need

to

transfer large amount of data for real-time

signal processing and high quality sound perception. The visual

implant is another example, which needs even higher data rates

for transferring images with minimum reasonable resolution.

Therefore, a high data transfer rate interface circuitry that can

establish an efficient wireless link between the implant and the

external units is highly needed.

I DigitalSigna

So far, the amplitude shifl keying (ASK) data modulation

technique has been commonly used in the biomedical implants

because of its fairly simple modulation .an d demodulation

circu itry However this method faces major limitations for high

bandwidth data transfer. Therefore, a novel high-rate data

transfer protocol and demodulator circuit has been proposed

based on the frequency shift keying (FSK) data modulation

technique for wirelessly operating the University of Michigan

micromachined

3D

stimulating microprobes [ I ] shown in Fig.

I

which are targeted at a 1024-site wireless stimulating

microsystem for visual and auditory prosthesis.

The FSK

is

one of the most useful modulation techniques

for digital communication, which simply means sending binary

data with two frequencies and f,, representing digital

and

respectively. The resultant modulated signal can he regarded

as the sum oft wo amplitude modulated AM) ignals of different

carrier frequencies as

shown

in Fig. 2a:

/ ( 1 ) = ~ ~ ( t ) s i n ( 2 ~ ~ ~ + 8 ) + ~ ~ ( t ) s i n ( 2 ~ ~ ~ + ~ )

1)

n the frequency domain, the signal power is centered

at

two

carrier frequencies,fo and f,, as shown in

Fig. 2b.

Since/o(tj and

f , r) can have the same amplitude, an excellent characteristic of

the

FSK

modulation for wireless biomedical implants, which

should be powered as well as communicated with the same

electromagnetic field is that the transmitted power is always

constant at its maximum level irrespective of an df i or the data

contents:

Fig.

1 3D

probe array of 25 6 stimulating sites.

0-7803-7523-8/02/ I7.00 02002 lEEE

(b)

Frequency Domain

Fig.1 Frequency shifl keying in time and frequency domains.

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mailto:maysamgh@,engin.umich.edumailto:maysamgh@,engin.umich.edu

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This is a major advantage over the amplitude shift keyed (ASK)

signals where data bits can alter power transfer efficiency

parricularly when the modulation index is high as in suspended

carrier m odulation [2].

Another difference between the FSK and ASK is that in the

ASK data transmission; the receiver tank circuit frequency

response should have a very high quality factor

Q),

entered at

the carrier frequency to get enough amplitude variation for data

detection. However, in the FSK data transmissio n, the pass band

should be centered between fa and fi with a low Q to

pass

enough

power of both carrier frequencies. This is an advantage for the

FSK technique because in the biomedical implants application,

the quality factor of the receiver coil is generally low particularly

when the implant receiver coil is integrated and its high

resistivity is un avoidab le [3].

Synch ronization of the rec eiver with the transmitter is easier

though in the ASK systems . Because the receiver internal clock

signal can be directly derived by stepping down the constant

transmitter carrier frequency

[4 5].

However, in the FSK data

transfer, the internal clock with constant frequency should be

derived from a comb ination of the two carrier frequencies

vn

nd

6

ased on the data transfer protocol or synchronization

patterns.

2.

THE FSK DATA TR ANSFER

PROTOCOL

The data rate in digital communication,

so

called FSK rate,

is hundreds oftime s slower than f, or/,. This cannot he the case

if we want to surpass IMbiVSec baud rate in the wireless

biomedical imp lants where the carrier frequency is limited to tens

of MHz because of the incremental tissue loss and risk of tissue

damag e at higher frequencies. For this kind of applications,

every dozen of carrier cycles should transfer at least one

or

even

more bits of data. Therefore a new method was devised for the

FSK data transfer with the F S K rate as high as i ith o wice as

f .

In this method, the digital bit

I

is transmitted by a single

cycle of the carrier/, and the digital bit

0

s transmitted by two

cycles of the carrier

o

as shown in Fig. 2a. This leads

to

a

consistent data transfer rate of

f i

bits/Sec. The transmine r

frequency switches at a

small

fraction of a cycle and only at zero

crossings. Obviou sly, any odd number of consecutive fa cycles

in this protocol is an indication of data transfer error.

3. DIFERRENTIAL

FSK

DEMODULATOR

The data detection technique used here for the FSK

demodulation is based on measuring the period of each received

carrier cycle. If the period is higher than a certain value, a digital

bit is detected and otherwise a digital s received. A

simple method for time measurement is charging a capacitor with

a constant current source and monitoring its voltage. Charging

and discharging of this capacitor should be synchronized with the

FSK carrier signal. If the capacitor voltage is higher than a

certain value, a digital 1 hit is detected and otherwise a digital

s

received. This comparison can be done in two ways:

I - Fully differential FSK demodulator (FDFSK): Charging two

unequal capacitors with different currents and compare their

voltages with a hysteresis co mparator as shown in Fig. 3a. This

t

f ,

h

a)

PDFSK

t

( b) R D m K

Fig.

3 The FSK data detection tech niques: (a) Fully Differential

FSK (b) Reference d Differential FS K.

is like comparing two capacitive timers with different time

constants.

2- Referenced differential FSK demodulator (RDFSK):

Generating a reference voltage and comparing

i t

with a charging

capacitor voltage as shown in Fig.3b .

The FDFSK method is more robust against process

variations in expense

of

more power consumption. To

experiment and compare both methods, we desigmd a circuit

based

on

the RDFSK method in the AMI 1Spm

CMOS

process

through the M O S S foundry. Another pro totE e chip was

designed based on the FDFSK method, which is the main focus

of this paper and implemented

in

the UofM 3pm

CMOS process

as shown in Fig.

4.

Fig.

5

shows

a

simplified schematic diagram of the FDFSK

demodulator. Both current sources and switches are controlled

by the input clock sign al (CK.), which

is

directlyrecovered from

the FSK carrier by the clock recovery block. The clock recovery

circuit is a cross-coupled differential pair, which is directly

connected to the receiver coil and turns the sinusoidal FSK

carrier signal into a similar square waveform. When CK,, is low,

SL

and

SH

switches are open and

SLC

and SHCare closed.

Therefore, the current sources

lL

and

I

linearly charge CL nd CH

up to

VL

and

VH

respectively. Durin g a digital

I

long cycle,

Fig. 4

The FDFSK prototype chip and its floor plan

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Fig.

5

The FDFSK

data

detector simplified schematic diagram.

VLI and VH I re twice as

V,O

and

VHO

hen a digital

short

cycle is being received because in our FSK protocol in Fig. 2, T I

is twice as

To. A

hesteresis comparator compares capacitor

voltages. The hysteresis window width,

Why,,,

s set somewhere

between VH,-V L,,and HO-VLO.herefore, the comparator output

switches to highduring a digital 1 long cycle but not during a

d i s t a l

shoti cycle.

SL

and

SH

switches discharge the

capacitors in a fraction of the FSK 2 half cycle, when CK, is

high; meanwhile

SU

and SHC witches open to reduce power

consum ption. CK, also resets the hysteresis compa rator to

prepare it for dktecting the type of the next cycle.

The output of the FDFSK data detector circuit

is

only a

pulse, which discriminates between

long

and short FSK carrier

cycles, so it cannot be directly regarded as the received data bit

stream. These pulses are fed into a digital block along with CK,

to

generate the serial data output (VOUT) and a constant

frequency output clock ( C L J. Fig.6 shows the schematic

diagram of the digital block.

On

every rising edge of the CK,, a

2-bit shift register shifts

in

the data-detector block output. Every

2

successive short cycles should be regarded

as

a

bit o

DOUT and every single long cycle indicates a bit. Any odd

number of short cycles is an indication of error according to the

FSK protocoland activates

the

error output signal. To generate a

constant frequency clock, a

T

flip-flop indicates the number of

successive zeros and another T flip-flop toggles an every long

CKj. cycle or two successive short CK,, cycles.

4. SIMULATION AND MEASUREMENT

RESULTS

To

check the performance of the FDFS K demodulator, post-

layout simulation was performed with choosing an djo

to

be

2.5MH z and 5MHz respectively. Th e data hit stream of

error

vout

c k o u t

Fig.

6

The FDFSK digital block schematic diagram.

n nsUx 1

(b)

Fig. 7 Th e FDFSK data detector simulated waveforms.

001001

110101

changes to 000010000111001001 when it is

encoded to the FSK data transfer protocol.

To

test the error

detection circuitry two single zeros are added before the

2 h

and

I S h

bits and finally a bit stream of0000100001 IQlOOlO Ql is

fed into the FDFSK demodulator CK, input. Fig. 7a shows the

resulting simulation waveforms. From top

to

bottom, trace-I

shows the FSK detector output pulses, which indicate

long

period

pulses (2.5MHz ) of the bottom trace, CK,. Th e inserted error

bits have been detected at t=3.2ks and t=5ps and shown on the

3rd trace.

I le

constant frequency clock (CL,,) and data

(VOUT) outpu ts are shown on the 4Ihand 5h races respectively.

Both rising and falling edges of the

CG.

indicate received data

bits

o

VOUT, which shows the original bit stream of

0010011lO101 without any errors. Fig. 7b shows CH and CL

capacitor voltages

in

a scaled portion of the simulation

waveforms.

The data detector, clock regenerator, and digital blocks were

tested both individually and together as an FSK data demodulator

chip.

All

of these circuits were functioning as expected from the

simulations up

to

IOOKbitisec, which was the highest FSK

modulation rate of our signal generator. Fig.

8

shows some of

the measured waveforms, whilefi andfo are set equal

to

l M H z

and 2MH z respectively. The lower trace in all sections is the

regenerated clock input (CK,). The upper traces in Fig.

8a

and

8b are CL and

CH

capacitor voltages respectively. Fig. 8c shows

the FSK data detector output pulses which discriminates between

IM Hz and 2MHz carrier cycles. The final demodulated data bit

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stream at IOOKbitkec is shown in Fig. 8d. Tab le summarizes

some of the specifications of the FDFSK dem odulator chip.

5.

CONCLUSION

We have developed a high-rate FSK data transfer protocol

and demodulator circuit for wirelessly operating the University

Supp ly voltage

Fig.8

The prototype FD FSK measured waveforms withf i and

o equal 10

lMH z and 2M Hz respectively. (a) Larger capacitor,

CL, voltage, (b) Sm aller capacitor, CH , voltage, (c) T he

FSK

data detector output, (d) The FSK demo dulated da ta output

5 v

TABLE

1

SPECIFICATIONS OF THE FDFSK DEMODULATOR CHIP

Process technology Uofh4 CM O S 3 ~ m

D ie s iz e I 2 m m x 2 m m

I,

and I I 2OuA and 33uA I

7.

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Hetke,

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