IEEE Standards Medallion 2013 Award - Dec 2013 For vision, leadership and exceptional dedication in enabling IEEE standards to lower costs for the electronics industry
Is every solution (or IEEE standard) going to be popular? -Customer safety? -Efficient?
Disclaimer:
Panel sessions are designed to create Debate. The moderator instructs panelists to take positions to help stimulate debate. Any of the views here are not necessarily that of CJ Clark or Intellitech Corporation. Nothing should be implied.
3
SysReset
IC1
BOUNDARY REGISTER
TAP
INIT-DATA REGISTER
IR & Decode & Muxing
User Defined Chain(s)
DACADC
0
1
0
1
On-chipReset via
TAP
PRBS
Swing
CMMV
UniqueECID
AC/DC
MemoryBIST
PLL
Volt.Mon
Protocol
LogicBIST
10
USBRegister Segmentation and
Power domain controlDC
Input
1149.1 is IJTAG - always has been - Access to on-chip IP via TAP (and via Tcl) has been around since 1990s
Not just about "Boundary Scan" IEEE 1149.1-2013 now brings Hierarchical descriptions of on-chip IP Hierarchical operational language for On-chip IP ("instruments") Access via TAP, system clocks, CE,VDD Synergy with IEEE 1500 and IEEE 1801 - re-use popular IEEE 1500 structures - TDRs can cross power domains with SEGSEL and MUX control Local Instrument resets, assertions, Custom mappings ( TSV-2-Register)
5
Describe Interface to IP w/o TAP Description is "packaged" in compliant IEEE 1149.1-2013 package file Describe just interface + mnemonics Machine readable
Attribute REGISTER_MNEMONICS of SERPRBS : package is "OnGroup (ON (1), OFF (0))," & "PatGroup ( PRBS31(1), PRBS23 (2), PRBS7(3) );" Attribute REGISTER_FIELDS of SERPRBS : package is "PRBS [5] ( "& "(Loopback [1] IS (4) DEFAULT(OnGroup(ON))), " & "(Pattern [2] IS (3,2) DEFAULT(PatGroup(PRBS7)) ), " & "(Run [1] IS (1) SAFE(OnGroup(OFF)) ), " & "(ForceError [1] IS (0)) DEFAULT(OnGroup(OFF)));"
PRBS Generator
Loopback
Pattern
Run ForceError
PRBS - Pseudo-Random Bitstream Sequence
6
Procedural Description Language - new vectorless re-targetable language for describing IP operation
iWrite Loopback ON iWrite Pattern PRBS23 iWrite Run ON iWrite ForceError OFF iApply
PRBS Generator
Loopback
Pattern
Run ForceError
Format: <iWrite > <Register> <value or mnemonic>
Set data
Shift data
7
IO(48)
IO(47)
HSSI
iWrite Loopback ON
iWrite HSSI.IO(48).Loopback 1 Tool converts to:
iWrite U1.HSSI.IO(48).Loopback 1 Tool converts to:
PRBS Generator
PRBS Generator
PRBS Generator
Package SERPRBS
Package SERPRBS Package HSSI
Package SERPRBS Package HSSI IC BSDL
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PRBS Generator
Loopback
Pattern
Run ForceError
Tools read IP package file hierarchy And integrate with top level IC 1149.1-2013 <info tag> specifically provided for interactive operation of internal JTAG registers Any instance of any IP can be accessed within the IC hierarchy
9
IEEE Std. 1149.1-2013 lowers industry costs by enabling test re-use through all phases of the IC life-cycle
- Specifies best practices for Infrastructure IP test interfaces - Specifies rules for describing IP operation - Enables one description to be used in all test stages - Enables defect correlation between system failures and IC ATE Note: doesn’t require production IC test through TAP - Track Die via 1149.1-2013 Electronic Chip Identification
IP Designer
IC Designers
PCB Designers
Test Engineers
Closest to source Furthest
Total Industry Cost Savings
One 1149.1-2013 compliant IP gets leveraged across hundreds of engineers One 1149.1-2013 compliant IC may have hundreds or thousands of IP
OSAT Engineers
OSAT = Out Sourced Assembly & Test
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5 wire test interface
TSV/uBump
Reg_1500
SI SO WSC
Reg_1500
SI SO WSC
Reg_1500
SI SO WSC
3210
WSC:Shift_1500
Capture_1500Update_1500
Reset*TCK
SI
SO
Sel_WSP
Gating Gating Gating
Gate_WSPC UC U
C U
C UC U
C U0
1
open
core core core
“read
y_to
_sca
n”
Start_1500 End_1500
C UC UB
CA
WSC
SI SOReg_1500S
Gating
DIE2
DIE1
DIE3 DIE4
core
IEEE 1149.1-2013 and IEEE 1500 IEEE 1149.1-2013 expands IEEE 1500 Wrapper Serial Ports - - Segment 1500 wrapper serial ports across domains - Attribute REGISTER_ASSOCIATION enables TSV -to-register mapping - Supports BROADCAST to IEEE 1500 WSPs
IEEE 1149.1-2013 and IEEE 1801 Standardizes Test Data Register segmentation implemented by IEEE 1801 power intent. Both standards now use Tcl as the standard language. Standardizes the input and description of on-chip or off-chip power control
14
TCK
Bypa
ss
RingEnable Bit
TDI
IR
C/S
U
C/S C/S C/S
U U
0
1
C/S C/S
U
C/S C/S C/S C/S C/S
U
0
1
0
1
EXTE
ST/P
RELO
AD
Decode
C/S
S2CTRL
U
S1CTRL
VCC_IO
PWRController VDD_DIE2
SEGSEL DOMCTRL
SEGSEL
DOMAIN_EXTERNAL
DOMAINVCC_IO
VDD_
DIE2
Q
QSET
CLR
D
B1 B3B2A4 A2 C1 C3
M1 N1 N3
Q QSET
CLR
D
SHIFT
TCK
TDI
1
0
0 1IR/DR
TAPRESET
TAP
TMS
QQSE
T
CLR
DST
DO
ECID
En/Dis*
TCK
STDI
TCK
C2
CORE
REG_1500SO
SI
M2 L1 L2 N2 M3
S2 D2
S1
CHRESET
CHRESET
CHRESET
FPP
1 0TMS
TMS StateBit
IEEE 1149.1-2013 discussed in P1838 Stacked Die
15
P1838 uses reset blocking concepts from 1149.1-2013 for TAPCONFIG register - not describable in P1687 ICL
16
New Memories HBM and HMC both 1149.1-2013 compliant
17
Hyper Memory Cube - Memory Mapped Registers - TAP access - Described in 1149.1-2013 BSDL
18
IEEE P1149.6-201x DC coupling, Vhyst, Vcm parameters in BSDL and PDL
attribute REGISTER_FIELDS of SerdesA : package is "init_data[5] ( "& -- TDI "(SEL [1] IS (4) DEFAULT(ONOFF(OFF) RESETVAL(ONOFF(OFF)) ), "& "(VCM [1] IS (3) DEFAULT(CMV(0V)) NOPI NOUPD ), "& "(WEN [1] IS (2) DEFAULT(ONOFF(OFF) RESETVAL(ONOFF(OFF)) ), "& "(SWING [2] IS (1 DOWNTO 0) DEFAULT(SWING(800mV)) NOPI NOUPD) "& " )";
# get_VCM returns a voltage. iProc get_VCM {} { # Note: the true value of the current VCM is only present # if SEL is set set common [iGet -si -mnem VCM] iApply # match the strings here with the case of the mnemonics if {$common == "0V"} { return "0" } else if {$common == "500mV" } { return "500" } else { puts "The common-mode voltage has never been set\n" return "ERROR"}}
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C/S C/S C/SC/S
RESET*
U
C/SC/SC/S
UD
RESET*
C/S
RESET*
SRAM_BIST_CONTROLLER
U
C/S C/SC/SC/SC/SC/SC/S
C/SC/SC/SC/SC/SC/S
C/SC/SC/SC/SC/SC/S
C/SC/SC/SC/SC/SC/S
C/SC/SC/SC/S
SI1 Clear-
ResultsResult
Addr[12]Result
Data[16] SO1
SI2
Busy
Mux
Sel
Mod
e[2]
Enab
le SO2 CPU Test
Mode[3]Fail
Pass
CPU TestEnableSh
iftD
R_2
Capt
ureD
R_2
Upd
ateD
RSta
te_2
Mod
e[1]
Mod
e[0]
TCK_
2
Shift
DR_
1Ca
ptur
eDR_
1U
pdat
eDRS
tate
_1TC
K_1
AD
DR(
12)
DA
TAIN
(16)
DA
TAO
UT(
16)
RD/W
R*
CS*
AD
DR(
12)
DA
TAIN
(16)
DA
TAO
UT(
16)
RD/W
R* CS*
SysC
lock
Pre-wrapping Silicon Instrument™ - Enables more efficient PDL and scan operations
Minimum Hardware Requirement: a) A P1687 interface shall have at least one port function
Can customers specify an IEEE standard in a contract that has few rules that are needed to achieve compliance?
"Having a vendor deliver a P1687 compliant ICs or IP is like a box of chocolates,
you never know what you're going to get."
- Forrest Gump
23
Everything is compliant, even IP designed 20 years ago!
24
Some Comparisons of 1149.1-2013 and P1687 1149.1-20013 P1687 Supports on-chip instruments via TAP Yes Yes Supports Hierarchical descriptions Yes Yes Variable scan chain lengths Yes Yes Hierarchical scan chain segmentation SEGSEL SIB race free by design Yes No Supports IEEE 1500, WIR and other Muxing Yes Yes Supports broadcast Yes Yes Addressable Instruments Yes Yes Local Resets 6+user Yes PDL0/PDL1/Tcl Yes Yes PDL0 - loop/if/then branching Yes No for ATE vector generation Support legacy devices (indirect addressing through random user defined logic) No Yes Plug and play IP Yes No Supports I/O (Voltage etc) configuration Yes No Supports power domains/ external power source Yes No Supports Instrument assertions Yes No checking/'constraints' Supports TSV mapping Yes No Instrument clock, power, reset requirements Yes No for diagnostics
P1687 value proposition Describe die TAP and I/O with 1149.1-2013 and P1149.6-201x BSDL and PDL
Describe ECID via BSDL and PDL Describe stuff on right in a new language called ICL rather than BSDL
26
Is pin access to instruments a good thing? - creates impediment for system level access to on-chip IP via TAP, clocks, power and reset
27
P1149.10 High Speed JTAG - Pin activation to an instrument is Going to be too slow and unsynch'd
• New HSTAP for SPI and Gigabit
SERDES • HSTAP described in BSDL attributes
• 1149.1-2013 PDL for init_setup • PEDDA decodes/encodes
Packets from ATE
• Multiple instruments accessed at the same time
• Multiple scan channels • I/O wrap segmented
• (like 1149.1)
P 1 1 4 9 . 1 0 _ E n a b l e
I n s t r u c t [ n : 0 ]
40 bit
40 bit
SI / SO / CSUK _ Boundary
SI / SO / CSUK _ DEVICE _ ID
SI / SO / CSUK _ Bypass
SI / SO / CSUK _ ECID
S I S O
SI / SO / CSUK _ CH 1
SI / SO / CSUK _ CH 2
CSUK _ Parallel
Packet Decoder / Encoder with Distribution Matrix
SI / SO / CSUK _ INIT _ DATA
SI _ PP [ 9 : 3 ]
SO _ PP [ 9 : 3 ]
T C K
B S _ M o d e [ 7 : 1 ] R e s e t *
BS _ Mode [ 7 : 1 ] ’ Reset’ *
System Clock
Mux And
Gating Logic
Packet Decode / Encode
PISO SIPO
Mux And
Gating Logic
PISO SIPO
Clock Control
+
-
S I P O
+ -
P I S O
Sipo Clk
Piso Clk
SI / SO / CSUK _ CLK _ Ctrl
28
Conclusion
IEEE 1149.1-2013 BSDL and PDL - Needed for Configuration of I/O - Needed for ECID - Supports TDR segmentation across power domains through domain control bit - supports IEEE 1500 architectures and segments 1500 WSPs for power domains IEEE 1149.1-2013 used by IEEE 1149.6-201x IEEE 1149.1-2013 used by IEEE P1149.10-201x Potentially used by P1838-201x
