ADVANCE PROGRAM

BCICTS 2020 IEEE BiCMOS and Compound

Semiconductor Integrated Circuits and Technology Symposium

A Virtual Event

November 16 - 19, 2020

.

SPONSORED BY

THE ELECTRON DEVICES SOCIETY OF THE INSTITUTE OF ELECTRICAL AND

ELECTRONIC ENGINEERS

IN COOPERATION WITH

THE IEEE SOLID - STATE CIRCUITS SOCIETY THE IEEE MICROWAVE THEORY &

TECHNIQUES SOCIETY

Conference Website: https://bcicts.org

2020 BCICTS SCHEDULE AT A GLANCE

SHORT COURSE

Video sessions for each short course presentation will be made available to registrants two weeks prior to conference start. A live Q&A session for each

short course has been scheduled during the conference period

Short Course 1

FinFET Technology Consideration for Circuit Design, Alvin Loke; NXP, San Diego, CA

Short Course 2

mm-Wave and RF Building Blocks for Next-Gen Wireless Systems in FinFET CMOS, Steven Callender, Intel, Hillsboro, OR

Short Course 3

High-Speed DACs for Millimeter-Wave Digital Arrays in FinFET CMOS, Boris Murmann, Stanford Univ., Palo Alto, CA, USA

PRIMER COURSE

Video session for the primer course will be made available to registrants on Saturday, November 14. A live Q&A session for the Primer course will occur

during the conference period

Primer Introduction to Si RFIC: A device and Circuit Perspective, Waleed Khalil, Ohio State University

Times listed are Pacific Standard Time

Monday - November 16

6:00AM -

6:15AM

Welcome and Announcements

6:15AM -

6:45AM

Plenary Session 1a Analog/Mixed-Signal Integrated Circuits for Quantum

Computing, Joseph Bardin, Google/University of Massachusetts

6:45AM -

7:00AM Question & Answers and Short Break

7:00AM -

7:30AM

Plenary Session 1b Fast pixel sensors for ionizing particles integrates in SiGe

BiCMOS, Lorenzo Paolozzi, University of Geneva

7:30AM -

7:45AM Question & Answers and Short Break

2:00PM -

2:30PM

Plenary Session 2a

The DARPA Millimeter-wave Digital Arrays (MIDAS) Program, Timothy Hancock, DARPA

2:30PM -

2:45PM Question & Answers and Short Break

2:45PM -

3:15PM

Plenary Session 2b

Trends in Imaging Radars Powered by Modern Silicon, Sherif

S. Ahmed, Stanford University

3:15PM -

3:30PM Question & Answers and Short Break

3:30PM -

4:30PM

1a. Compound Semiconductor mm-Wave & Near-THz ICs

1b. Advanced Compound Devices

Tuesday - November 17

6:00AM -

7:30AM

2a. Reconfigurable and Wideband Circuits

2b. Device Modeling for Emerging Applications

7:30AM

- 8:00AM

Short Course 1 Questions and Answers FinFET Technology Consideration for Circuit Design

8:00AM -

8:30AM Virtual Social Event

2:00PM -

3:20PM

3a. Silicon mm-W ICs for Communications & Radar

3b. HEMT Device Modeling and Simulation

3:20PM -

3:50PM Vendor Forum: Cadence

3:50PM -

4:20PM Optional Vendor Breakout

Wednesday - November 18

6:00AM -

7:30AM

4a. High-Speed Mixed Signal Circuits for Optical

Communication and Radar

4b. Bipolar Devices at Their Limits

7:30AM -

8:00AM

Short Course 2 Questions and Answers mm-Wave and RF Building Blocks for Next-Gen Wireless

Systems in FinFET CMOS

2:00PM -

3:20PM 5a. Advanced GaN Amplifiers 5b. Advanced Power Devices

3:30PM -

4:00PM Vendor Forum (VDI) / Optional Vendor Breakout

4:00PM -

4:30PM

Primer Course Questions and Answers Introduction to Si RFIC: A device and Circuit Perspective

4.30PM-- Virtual Social Event

Thursday - November 19

6:00AM -

7:20AM

6a. Late Breaking News 1

6b. Nonlinear Modeling of Compound Semiconductor

Devices

7:20AM -

7:50AM

Short Course 3 Questions and Answers High-Speed DACs for Millimeter-Wave Digital Arrays in FinFET

CMOS

2:00PM -

3:20PM 7a. Late Breaking News 2

7b. SiGe Technology Applications

3:30PM -

4:00PM Closing Session & Virtual Reception

Welcome from the BCICTS 2020 Chair

It is with great pleasure that we welcome you to participate in the 2020 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS). After 41 years of the Compound Semiconductor IC Symposium (CSICS), and 34 years of the Bipolar/BiCMOS Circuit and Technology Meeting (BCTM), the third meeting of this combined symposium will be held virtually from Monday November 16 to Thursday November 19.

The global COVID-19 pandemic has made 2020 an unprecedented

year to be sure. Certainly, a virtual BCICTS is a first. Yet, the ability to have a virtual conference exemplifies the tremendous contributions of engineers throughout the world. Many of the technical contributions of the BCICTS community make virtual meetings possible. Members of the technical community should feel satisfaction in their role to keep communications and interactions alive despite a global pandemic.

With the unprecedented backdrop of a virtual meeting, BCICTS will

continue the long history, from BCTM and CSICS, of international gatherings where distinguished experts present their latest results in bipolar, SiGe BiCMOS, and compound semiconductor circuits, devices, and technology. There are no other events in the world where you can see leading edge bipolar/BiCMOS devices and technology, 5G ICs, GaN HPAs, InP THz PAs, optical CMOS/SiGe transceivers, GaN HEMT power devices, and advances in compact modeling, all presented together.

This third BCICTS includes presentations from worldwide submissions on all aspects of the technology. Topics span process technology, device advances, TCAD modeling, compact modeling to IC design and testing, high-volume manufacturing, and system applications. BCICTS will also feature the very latest results in RF/microwave, millimeter-wave, THz, analog mixed signal, and optoelectronic integrated circuits. In the virtual format, we will provide not only the technical proceedings, but also, for a limited time after the conference, we will post the presentation materials and recordings of the presentations. Authors will be on hand for live Q&A sessions after the presentation of each session.

This year, BCICTS offers an on-line access to topical short course

on FinFET device, circuit, and ADC system design. Taught by leading experts, the short course is intended for both technologists and IC designers who seek a comprehensive understanding of the latest industry trends and techniques.

We also offer a more basic primer course on BiCMOS device and

circuit design. The primer course is intended to be a tutorial which introduces RFIC design from device technology and circuit design perspectives.

As a complement to the technical program, the symposium includes

on-line social events that allow participants to interact. These events include virtual break out rooms where attendees can meet new colleagues and visit with long-time friends.

We would like to thank the many dedicated volunteers on the

BCICTS Committee, and the generous support of the IEEE Electron Devices, Microwave Theory and Techniques, and Solid-State Circuits Societies. Finally, we look forward to interacting with all participants to continue the traditions of technical excellence and create new traditions with this virtual conference! Bruce Green Symposium Chair, NXP Semiconductors

BCICTS 2020 REGISTRATION

Click here to register https://bcicts.org Advance registration deadline is Friday, October 23, 2020. Registration Fees: MAIN MEETING (November 16-19) Please contact cs@cshawevents.com for more details.

(1) Conference Registration Cost in US Dollars (includes conference program, electronic proceedings, networking breakouts in addition to the vendor forum)

Notes: *All fees are denominated in US$ *Full Registration for the conference Includes: proceedings and access to video presentations. *Short Course Registration includes short course notes and access to video presentations *Primer course registration includes: primer course notes and access to video presentations Refund/Cancellation Policy: All requests for refund/cancellation must be received in writing at least 10 days prior to the conference start date for a full refund on or before November 1, 2020. Any requests thereafter will not be entitled to a refund. Cancellations will incur a $50 USD administration fee. Please submit cancellation requests via email (cs@cshawevents).

IEEE Member Advanced

Registration Before 11/01

Non Member

Student Member

Conference $275 $375 $100

Conference plus short

course $450 $550 $200

Conference plus

primer (only)

$375 $475 $200

Conference plus short course and

primer

$550 $650 $300

ADDITIONAL INFORMATION ADMISSION All interested persons are welcome to register and attend the BCICTS; you do not have to be an IEEE member. REGISTRATION Complete registration information is contained in the on the conference’s web page (https://bcicts.org) Please use the website to register. The advanced registration deadline is October 23, 2020. All conference activities are included in the registration fees as well as an electronic copy of the BCICTS 2020 Proceedings. OTHER CONFERENCE SOCIAL EVENTS Several events have been arranged to promote informal social interactions among conference participants. TUTORIAL / SURVEY TALKS Tutorial talks given by invited experts are intended to give a broad overview of a given subject with a critical review of technology and applications. They are twice the length of the usual contributed talk with longer abstracts in the Proceedings.

MEMBERS OF THE PRESS: Members of the press can contact Catherine Shaw (cs@cshawevents) for additional information. RECRUITING Intensive recruiting undermines the purposes for which the BCICTS was established, and is contrary to IEEE policy. BEST STUDENT PAPER AND BEST PAPER AWARDS BCICTS offers a Best Paper Award. The BCICTS Best Paper Award recognizes and promotes high quality contributions to scholarly research among professionals who author and present papers at the conference. All papers submitted in non-student category are eligible for consideration for the Best Paper Award. The BCICTS Best Student Paper Award recognizes and promotes outstanding research led by students. To be eligible for consideration for the Best Student Paper Award, the following criteria have to be met: 1) the student must have carried out a substantial part of the research reported in the paper, 2) the student must be the first author and must present the paper at the conference, 3) the paper must be identified as a student paper during submission of the paper; and 4) the paper identified as a student paper in submission, but not presented by the student will be disqualified for Best Student Paper Award competition. In this scenario, the paper will be moved to non - student category for Best Paper Award competition automatically. Eligible papers are evaluated by the Best Paper Award Committee and the notifications will be sent out after the conference. The winners of the awards will be recognized with a $500 check and a plaque at next year's BCICTS conference. FURTHER INFORMATION BCICTS is sponsored by the IEEE Electron Devices Society (EDS) in co - operation with the IEEE Solid - State Circuits Society (SSCS) and the IEEE Microwave Theory & Techniques Society (MTT).

BCICTS 2020 Short Course and Schedule Online Content

Discussion Topic: High-Speed Mixed-Signal and RF Circuit Design in FinFET Technologiesies Speakers:

o Alvin Loke (NXP) o Steven Callender (Intel) o Boris Murmann (Stanford Universtiy)

Chairs/Co-Chair Michael Schröter / Yuriy Greshishchev

Course Overview Renowned experts from academia and industry will share their views on high-speed mixed-signal and RF circuit design in FinFET Technologies

Abstracts and Speaker Bios: Technology Considerations for Circuit Design Instructor: Alvin Loke (NXP) CMOS scaling maintains economic relevance with monolithic 5nm SoCs just released into the consumer marketplace and 3nm in early stages of product development. Modest feature size reduction and technology innovations optimized for logic and SRAM scaling continue to offer compelling node-to-node power, performance, area, and cost benefits. In this tutorial, we start with a brief history of transistor evolution to motivate the migration from planar to the fully depleted FinFET. We will summarize the key process technology elements that have enabled the FinFET CMOS nodes, highlighting the resulting device technology characteristics and the impact of challenges, such as more significant parasitics and layout-dependent effects, on design. To address the growing effort required for physical design closure, we cover design strategies including density-friendly layout, continuous active area layout, and template-based analog cells. We conclude with a discussion of what remains in finFET development and a peak at transistor architectures on the horizon. Alvin Loke recently joined NXP Semiconductors as a Technical Director in San Diego, having worked on CMOS nodes spanning from 180nm to 2nm at Agilent, Advanced Micro Devices, Qualcomm, and TSMC. He received a B.A.Sc. degree in engineering physics with highest honors from the University of British Columbia, and M.S. and Ph.D. degrees in electrical engineering from Stanford University. Upon graduating, he spent several years in CMOS process integration. Since 2001, he has worked on analog/mixed-signal design (focusing on a variety of wireline links), design/model/technology interface, and analog design methodologies. He has been an active volunteer in the IEEE Solid-State Circuits Society (SSCS) since 2003, having served as Distinguished Lecturer, Custom Integrated Circuits Conference (CICC) Committee Member, Denver Chapter Chair, and Guest Editor for Journal of Solid-State Circuits and Solid-State Circuits Letters. He currently serves as an SSCS AdCom Member, Webinar Chair, San Diego Chapter Chair as well as a VLSI Symposia Committee Member. Alvin has authored over 50 publications (including the CICC 2018 Best Paper) and 28 US patents.

Millimeter-Wave and RF Building Blocks for Next-Gen Wireless Systems in FinFET CMOS Instructor: Steven Callender (Intel) Next-generation communication systems such as WiFi-6 and mm-wave for 5G have placed stringent requirements on process performance, system integration, and cost. While deeply-scaled CMOS has continued to provide a cost advantage, thanks to Moore’s law, it is not always clear if the performance of these deeply-scaled nodes can meet the requirements of the next-gen RF/mm-wave systems. In this short course, we will show that FinFET CMOS indeed has the capability to deliver the required performance while also providing the improved integration and lower cost offered by scaling. The challenges faced when designing in these deeply-scaled nodes will be discussed along with a review of some design techniques and methodologies that help uncover the optimal RF/mm-wave performance of the process. Demonstration of the effectiveness of these techniques will be provided in the context of E-Band LNA, PA, and fully-integrated phased-array designs in Intel’s 22FFL process, all of which are state-of-art E-Band designs in a FinFET CMOS process. Lastly, the role that design-technology co-optimization (DTCO) can play in further enhancing

performance of these deeply-scaled nodes will also be discussed.

Steven Callender (M’060) was born in Brooklyn, NY. He received the B.S. degree in Electrical Engineering from Columbia University, New York, NY, in 2008, and the M.S. and Ph.D. degrees in Electrical Engineering from UC Berkeley, Berkeley, CA, in 2010 and 2015, respectively. In 2015, he joined Intel Labs as a Research Scientist focusing on the development of next generation wireless systems. His research interests include RF/mm-wave circuits and wideband mixed-signal systems.

Dr. Callender is the co-recipient of the ISSCC 2010 Jack Kilby Outstanding Student Paper and ISSCC 2019 Lewis Winner Outstanding Paper awards. He was also the recipient of the Robert Noyce Memorial Fellowship in Microelectronics, 2012, the ADI Outstanding Student Designer Award, 2013, the William L. Everitt Student Award from Columbia University, 2008, and the UC Berkeley EECS Chair’s Excellence Award, 2008.

High-Speed DACs for Millimeter-Wave Digital Arrays in FinFET CMOS Instructor: Boris Murmann (Stanford Universtiy) Digital-to-analog converters (DACs) are crucial building blocks in modern communication systems like wireline transceivers and digital mm-wave phased arrays. These applications drive steady increases in bandwidth, channel count, as well as integration density, favoring solutions that are compatible with the latest CMOS technology. This tutorial reviews the challenges associated with the design of wideband DACs in FinFET CMOS. It begins by discussing the popular current steering topology and its implementation challenges. Next, it considers an alternative topology that consists mainly of inverters and sub-femtofarad capacitors to improve compatibility with FinFET CMOS. In contrast to its current steering counterpart, this switched capacitor (SC) architecture separates the functions of level generation, pulse timing, and output power delivery. Lastly, we present a corresponding 28-GS/s 8-bit proof-of-concept SC DAC prototype. It achieves IM3 < –45.6 dBc across the first Nyquist zone while occupying only 0.03 mm2 in 16 nm FinFET CMOS. Boris Murmann is a Professor of Electrical Engineering at Stanford University. He joined Stanford in 2004 after completing his Ph.D. degree in electrical engineering at the University of California, Berkeley in 2003. From 1994 to 1997, he was with Neutron Microelectronics, Germany, where he developed low-power and smart-power ASICs in automotive CMOS technology. Since 2004, he has worked as a consultant with numerous Silicon Valley companies. Dr. Murmann’s research interests are in mixed-signal integrated circuit design, with special emphasis on sensor interfaces, data converters and custom circuits for embedded machine learning. In 2008, he was a co-recipient of the Best Student Paper Award at the VLSI Circuits Symposium and a recipient of the Best Invited Paper Award at the IEEE Custom Integrated Circuits Conference (CICC). He received the Agilent Early Career Professor Award in 2009 and the Friedrich Wilhelm Bessel Research Award in 2012. He has served as an Associate Editor of the IEEE Journal of Solid-State Circuits, an AdCom member and Distinguished Lecturer of the IEEE Solid-State Circuits Society, as well as the Data Converter Subcommittee Chair and the Technical Program Chair of the IEEE International Solid-State Circuits Conference (ISSCC). He is the founding faculty co-director of the Stanford SystemX Alliance and the faculty director of Stanford's System Prototyping Facility (SPF). He is a Fellow of the IEEE.

BCICTS 2020 Primer Course Online Content

Discussion Topic: Introduction to Si RFIC: A device and Circuit Perspective Speaker:

o Prof. Waleed Khalil (The Ohio State Universit)

Chair Simon Wood

Course Overview Renowned experts from industry teach present more tutorial and fundamental instruction for those new to the field or wanting a refresher. This will include a device and circuit perspective for Si RFIC.

Introduction to Si RFIC: A device and Circuit Perspective Instructor: Prof. Waleed Khalil (The Ohio State Universit) This course, intended for device, circuits, and systems professionals, provides a distinctive RF device and circuits’ perspective that integrates both conceptual and practical skills. The primer first hour will be dedicated to nanometer CMOS device analysis, reviewing key operation and noise aspects in short channel CMOS, while also providing some background on emerging devices, such as SOI and FinFET technologies, and RF passives. This will provide the attendees with the fundamental basis to build on for the remainder of the course. In the second part of the primer, the focus will be on diverse design aspects of different RF circuit blocks. In this part, the course will cover key RF blocks: LNAs, Mixers and VCOs, where the attendees will be exposed to a variety of different circuit topologies. A detailed step-by-step design example for each of the blocks, drawn from various wireless standards (e.g. Cellular, WiFi,.), will also be reviewed to conclude the presentation of each block Dr. Waleed Khalil leads a multidisciplinary research team in digital intensive RF and mm-wave circuits and systems, high performance clocking circuits, GHz data converters, heterogeneous integration and hardware security. He is currently serving as an Associate Professor at the ECE department and the ElectroScience Lab, The Ohio State University. Prior to joining OSU in 2009, he spent 16 years at Intel Corporation where he held various positions in wireless and wireline communication groups. While at Intel, he established Intel's first analog device modeling methodology for mixed signal circuit design and also contributed to the development of Intel's first RF process technology. His research group at OSU has received numerous awards from government agencies as well as from leading defense and commercial industry partners. He is the recipient of OSU’s College of Engineering Lumley Research Award in 2019 and Fred H. Pumphrey's Distinguished Teacher Award in 2018. His research group has received several paper awards, among them TSMC’s outstanding research award and the best paper awards in the Wireless Innovation forum, Phase Array Symposium, Compound Semiconductor IC conference and Government Microcircuit Applications & Critical Technology (GOMACTech) Conference. He authored 16 issued and several other pending patents, over 100 journal and conference papers and three books/book chapters. He is a senior member of IEEE and also served as the general chair for the 2020 RFIC Symposium and as an Associate Editor for the Journal of Solid State Circuits.

INTRODUCTORY REMARKS AND PLENARY

WELCOME AND ANNOUNCEMENTS 6:00 - 6:15 PM – Plenary Room

BRUCE GREEN Chair

PLENARY 1

Monday 6:00 AM – Plenary Virtual room Session Chair: Bruce Green, NXP Co-chair: Craig Steinbeiser, Qorvo

6:15 AM - 6:45 AM - Analog /Mixed-Signal circuits for Quantum Computing Joseph C. Bardin Google CA, and University Massachusetts Amherst MA

6:45 PM - 6:55 AM Q&A 7:00 AM - 7:30 AM - Fast pixel sensors for ionizing particles integrated in SiGe BiCMOS Lorenzo Paolozzi, Giuseppe Iacobucci, Pierpaolo Valerio Department of nuclear and particle physics, University of Geneva, Switzerland

7:30 AM - 7:40 AM Q&A

PLENARY 2

Monday 2:00 PM – Plenary virtual room Session Chair: Bruce Green, NXP Co-chair: Craig Steinbeiser, Qorvo

2:00 PM - 2:30 PM - The DARPA Millimeter Wave Digital Arrays (MIDAS) Program Timothy M. Hancock1, Steven Gross1, James McSpadden2, Lawrence Kushner2, Jason Milne2, Jon Hacker3, Ryan Walsh4, Craig Hornbuckle5, Charles Campbell6, Kevin Kobayashi6 1Microsystems Technology Office (MTO), Defense Advanced Research Projects Agency (DARPA) 2Raytheon Technologies 3Teledyne Scientific 4Northrop Grumman Corporation 5Jariet Technologies 6Qorvo

2:30 PM - 2:40 PM Q&A 2:45 AM - 3:15 PM - Trends in Imaging Radars Powered by Modern Silicon Sherif S. Ahmed Adjunct Professor, Stanford University

3:15 AM - 3:25 AM Q&A

Conference Program

1a. Compound Semiconductor mm-Wave & Near-THz ICs Monday 3.30pm – Virtual Room A Session Chair: Nils Pohl, Nokia – Ruhr-University Bochum Co-Chair: Harris Moyer, HRL Laboratories

1a.1 3:30-3:50 PM – 18-44 GHz K/Ka-band Robust-35.5dBm Reconfigurable 90nm GaN HEMT LNA Kevin W. Kobayashi1, Vipan Kumar2, Charles Campbell2, Shuoqi Chen2, Yu Cao2 1Qorvo Inc, Torrance, CA, USA 2Qorvo Inc, Richardson, TX, USA

1a.2 3:50-4:10 PM – An over 220-GHz-Bandwidth Distributed Active Power Combiner in 250-nm InP DHBT Teruo Jyo, Munehiko Nagatani, Minoru Ida, Miwa Mutoh, Hitoshi Wakita, Naoki Terao, Hideyuki Nosaka NTT Device Technology Labs., Japan

1a.3 4:10-4:30 PM – 230–305 GHz, > 10-dBm-Output-Power Wideband Power Amplifier Using Low-Q Neutralization Technique in 60-nm InP-HEMT Technology Hiroshi Hamada, Takuya Tsutsumi, Adam Pander, Masahito Nakamura, Go Itami, Hideaki Matsuzaki, Hiroki Sugiyama, Hideyuki Nosaka NTT Device Technology Labs., Japan

1b. Advanced Compound Devices Monday 3:30 PM – Virtual Room B Session Chair: Patrick Fay, University Notre Dame Co-Chair: Carl Dohrman, ST Research

1b.1 (Invited) 3:30-4:10 PM – Materials and Device Engineering for High-Performance Gallium Oxide Devices Zhanbo Xia1, Nidhin Kurien Kalarickal1, Siddharth Rajan1,2 1Department of Electrical and Computer Engineering, The Ohio State University, Columbus, OH 2Department of Materials Science and Engineering, The Ohio State University, Columbus, OH

1b.2 4:10-4:30 PM – Monolithically Integrated GaN+CMOS Logic Circuits Design and Electro-Thermal Analysis for High-Voltage Applications Pilsoon Choi1,2, Bugra Kanargi2, Kenneth E. Lee2, Chirn-Chye Boon3, Evelyn Wang1,2, Chuan Seng Tan2,3 Dimitri A. Antoniadis1,2, and Eugene A. Fitzgerald1,2 1Massachusetts Institute of Technology, Cambridge, MA 2Singapore-MIT Alliance for Research & Technology, Singapore, 138602 3Nanyang Technological University, Singapore, 639798

2a. Reconfigurable and Wideband Circuits Tuesday 6:00 AM – Virtual Room A Session Chair: Steve Huettner, Nuvotronics Co-Chair: Michael Litchfield, BAE Systems, Inc.

2a.1 6:00-6:20 AM – Design of a wideband, 4 – 42.5 GHz Low Noise Amplifier in 0.25 μm GaAs pHEMT Technology M. Sakalas, P. Sakalas Baltic Institute of Advanced Technology, Vilnius, Lithuania

2a.2 6:20-6:40 AM – A 20-33 GHz Direct-Conversion Transmitter in 45-nm SOI CMOS Tiantong Ren, Sandeep Hari, Brian A. Floyd

North Carolina State University, Raleigh, NC

2a.3 6:40-7:00 AM – A New Wideband, Low Insertion Loss SiGe Digital Step Attenuator Clifford D. Cheon, Moon-Kyu Cho, Sunil G. Rao, Adilson S. Cardoso, Jeffrey D. Connor, John D. Cressler Georgia Institute of Technology, Atlanta, GA

2a.4 (Invited) 7:00-7:30 AM – Broadband Reconfigurable Transceivers in SiGe Gregory M. Flewelling

BAE Systems, Inc., Merrimack, NH

2b. Device Modeling for Emerging Applications Tuesday 6:00 AM – Virtual Room B Session Chair: Sadayuki Yoshitomi, Kioxia Co-Chair: Pete Zampardi, Qorvo

2b.1 (Invited) 6:00-6:30 AM – Device Scaling roadmap and its implications for Logic and Analog platform Alessio Spessot1, Bertrand Parvais1,2, Amita Rawat1, Kenichi Miyaguchi1, Pieter Weckx1, Doyoung Jang1, Julien Ryckaert1 1IMEC, Kapeldreef 75, 3001 Belgium 2Vrije Universiteit Brussel, Department ETRO, VUB, Belgium

2b.2 6:30-6:50 AM – Compact Modeling of SiGe HBTs for Design ofCryogenic Control and Readout Circuits for Quantum Computing Hanbin Ying1, Sunil G. Rao1, Milad Frounchi1, Markus Müller2, Xiaodi Jin2, Michael Schröter2, John D. Cressler1

1Georgia Institute of Technology, Atlanta, USA 2Technische Universität Dresden, Dresden, Germany

2b.3 6:50-7:10 AM – Modeling the temperature dependence of sheet resistances in SiGe:C HBTs from 4.3 to 423 K Xiaodi Jin, Christoph Weimer, Yaxin Zhang and Michael Schröter Technische Universität Dresden, Dresden, Germany

2b.4 7:10-7:30 AM – HICUM/L2: Extensions over the last decade Michael Schröter1, Andreas Pawlak2, Anindya Mukherjee1, Didier Celi3, Mario Krattenmacher1

1Technische Universität Dresden, Dresden, Germany 2Infineon AG, Neubiberg, Germany 3STMicroelectronics, Crolles, France

7:30 AM - 8:00 AM Short Course 1 Q & A: FinFET

Technology Consideration for Circuit Design, Alvin Loke; NXP, San Diego, CA 8:00 AM - 8:30 AM Virtual Social Event

3a. Silicon mm-Wave ICs for Communication & Radar Tuesday 2.00 PM – Virtual Room A Session Chair: Shahriar Shahramian, Nokia – Bell Labs Co-Chair: Wibo Van Noort, Texas Instruments

3a.1 2:00-2:20 PM – A 10 mW LNA with Temperature Compensation for 24 GHz Radar Applications in SiGe BiCMOS Vadim Issakov1,2, Andreas Werthof1 1Infineon Technologies AG, Am Campeon, Neubiberg, Germany

2Otto-von-Guericke University, Universitasplatz, Magdeburg, Germany

3a.2 (Student) 2:20-2:40 PM – A Fully Integrated 20-500-GHz Coherent Detector with 2-Hz Frequency Resolution Mostafa Hosseini, Aydin Babakhani Department of ECE, University of California, Los Angeles, CA, USA

3a.3 (Student) 2:40-3:00 PM – A 28-37 GHz Triple-Stage Transformer-Coupled SiGe LNA with 2.5 dB Minimum NF for Low Power Wideband Phased Array Receivers Abdulrahman A. Alhamed, Gabriel M. Rebeiz University of California, San Diego, La Jolla, CA, USA

3a.4 (Student) 3:00-3:20 PM – Design of an 18‒50 GHz SiGe HBT Cascode Non-uniform Distributed Power Amplifier Seokchul Lee1, Inchan Ju1,3, Yunyi Gong1, Adilson S. Cardoso2, Jeffrey D. Connor2, Moon-Kyu Cho1, John D. Cressler1 1School of Electrical and Computer Engineering, Georgia Tech,

Atlanta, GA, USA 2Georgia Tech Research Institute, Atlanta, GA, USA 3Qualcomm Atheros, Inc., San Jose, CA, USA

3b. HEMT Device Modeling and Simulation Tuesday 2:00 PM – Virtual Room B Session Chair: Paul Tasker, Cardiff University Co-Chair: Subrata Halder, Qorvo

3b.1 (Invited) 2:00-2:40 PM – Current Collapse and Kink Effect in GaN RF HEMTs: The Key Role of the Epitaxial Buffer Michael J. Uren, Martin Kuball

University of Bristol, Bristol, UK

3b.2 2:40-3:00 PM – SLC-ASM-HEMT: An Accurate Compact Model for SLCFET RF Switch Sourabh Khandelwal1, Brain Novak2, Jordan Merkel2, Ken Nagamatsu2, Justin Parke2, Mark Yu2, Patrick Shea2, Robert Howell2

1University of South Florida, Tampa, Florida, USA 2Northrop Grumman Mission Systems, Linthicum, Maryland, USA

3b.3 3:00-3:20 AM – Using Channel Physical Relationships in pHEMT Modeling Yingying Yang, Xiao-Ping Li, Cristian Cismaru, Ravi Ramanathan Skyworks Solutions, Inc., Newbury Park, California, USA

3:20 PM - 3:50 PM Vendor Forum 3:50 PM - 4:20 PM Optional Vendor Breakouts

4a. High-Speed Mixed-Signa Circuits for Optical Communication and Radar Wednesday 6.00 AM – Virtual Room A Session Chair: Johann Christoph Scheytt, University of Paderborn Co-Chair: Koichi Murata, Renesas

4a.1 (Invited) 6:00-6:30 AM – Photonic-Electronic Ultra-Broadband Signal Processing: Concepts, Devices, and Applications Christian Koos Institute of Photonics and Quantum Electronics, Karlsruhe, Germany

4a.2 6:30-6:50 AM – A 120 GS/s 2:1 Analog Multiplexer with High Linearity in SiGe-BiCMOS Technology Michael Collisi, Michael Möller Saarland University, Saarbrűcken, Germany

4a.3 6:50-7:10 AM – 128-GS/s 1-to-4 SiGe Analog Demultiplexer with 36-GHz Bandwidth for 6-bit Data Converters Philipp Thomas, Tobias Tannert, Markus Grözing, and Manfred Berroth University of Stuttgart, Stuttgart, Germany

4a.4 7:10-7:30 AM – A 117 GHz Dual-Modulus Prescaler With Inductive Peaking for a Programmable Frequency Divider L. Polzin1, M. van Delden1, N. Pohl2, K. Aufinger3 and T.

Musch1 1Institute of Electronic Circuits, Ruhr University, Bochum, Germany

2Institute of Integrated Systems, Ruhr University Bochum, Germany

3Infineon Technologies AG, Neubiberg, Germany

4b. Bipolar Devices at Their Limits Wednesday 6:00 AM – Virtual Room B Session Chair: Kai Kwok, Skyworks Co-Chair: Vibhor Jain, GlobalFoundries

4b.1 (Student) 6:00-6:20 AM – Impact of large-signal operation on DC operating point of Horizontal Current Bipolar Transistor Željko Osrečki, Josip Žilak, Marko Koričić, and Tomislav Suligoj Department of Electronics, University of Zagreb, Croatia

4b.2 (Student) 6:20-6:40 AM – Circuit-Level Safe-Operating-Area of a High-Speed SiGe BiCMOS Wireline Driver Arya Moradinia1, Rafael P. Martinez2, Jeffrey W. Teng1, Nelson Sepulveda-Ramos1, Harrison Lee1, and John D. Cressler1 1 School of Electrical and Computer Engineering, Georgia Tech, Atlanta, GA 30318 USA 2 Department of Electrical Engineering, Stanford University

4b.3 6:40-7:00 AM – Physics of Hot Carrier Degradation Under Saturation Mode Operation in SiGe HBTs Uppili S. Raghunathan1, Pui Yee1, Dave Brochu1, Vibhor Jain2, Harrison P. Lee3, John D. Cressler3, and Dimitris P. Ioannou4 1 GlobalFoundries, Essex Junction, VT 05452 USA 2 GlobalFoundries, Malta, VT 12020 USA 3 School of Electrical and Computer Engineering, Georgia Tech, Atlanta, GA 30332 USA 4 GlobalFoundries, Hopewell Junction, NY 12533 USA

4b.4 (Invited) 7:00-7:30 AM – Modeling and characterization of HBT limits Andries Scholten

NXP Semiconductors, Eindhoven, The Netherlands

7:30 AM - 8:00 AM Short Course 2 Q & A: mm-Wave and RF Building Blocks for Next-Gen Wireless Systems in FinFET CMOS, Steven Callender, Intel, Hillsboro, OR

5a. Advanced GaN Amplifiers Wednesday 2:00 PM – Virtual Room A Session Chair: Kazuya Yamamoto, Mitsubishi Electric Corporation Co-Chair: John Wood, Wolfspeed

5a.1 (Invited) 2:00-2:30 PM – Millimeter-Wave GaN SSPAs: Technology to Power 5G and the Future James Schellenberg

Quinstar Technology, Inc., Torrance, CA

5a.2 2:30-2:50 PM – Robust-5W Reconfigurable S/X-band GaN LNA using a 90nm T-gate GaN HEMT Technology

Kevin W. Kobayashi1, Vipan Kumar2, Charles Campbell2, Shuoqi Chen2, Yu Cao2, Jose Jimenez2 1Qorvo Inc., Torrance, CA 2Qorvo Inc., Richardson, TX

5a.3 2:50-3:10 PM – A Ku-band 70-W Class GaN Internally Matched High Power Amplifier with Wide Offset Frequencies of up to 400 MHz for Multi-Carrier Satellite Communications Takaaki Yoshioka1, Kenji Harauchi2, Takumi Sugitani1, Takashi Yamasaki1, Hiroaki Ichinohe1, Miyo Miyashita1, Kazuya Yamamoto1, Seiki Goto1 1High Frequency & Optical Device Works, Mitsubishi Electric Corporation, Japan 2Formerly, High Frequency & Optical Device Works, Mitsubishi Electric Corporation, Japan

5a.4 3:10-3:30 PM – A Wideband and High Efficiency Ka-band GaN Doherty Power Amplifier for 5G Communications Yutaro Yamaguchi, Keigo Nakatani, Shintaro Shinjo

Mitsubishi Electric Corporation

5b. Advanced Compound Devices Wednesday 2:00 PM – Virtual Room B Session Chair: Parrish Ralston, Northrop Grumman Mission Systems Co-Chair: Bruce Kim, City College of New York

5b.1 (Student) 2:00-2:20 PM – RF Performance of GaN-Based Graded-Channel HEMTs Nivedhita Venkatesan1, Jeong Moon2, Joel Wong2, Bob Grabar2, Michael Antcliffe2, Peter Chen2, Erdum Arkun2, Isaac Khalaf 2, David Fanning2, and Patrick Fay1 1Dept. of Electrical Engineering, Univ. of Notre Dame, Notre Dame, Indiana 2HRL Laboratories LLC, Malibu, CA USA

5b.2 2:20-2:40 PM – Microwave Performance of Ferroelectric-Gated GaN HEMTs Chunlei Wu1, Jeffrey Smith1, Suman Datta1, Yu Cao2, Jinqiao Xie2, Ed Beam2, Patrick Fay1 1Department of Electrical Engineering, Univ. of Notre Dame, Notre Dame, Indiana 2Qorvo Inc., Richardson, TX

5b.3 2:40-3:00 PM – High Performance 150 mm RF GaN Technology with Low Memory Effects B. Green, K. Moore, S. Klingbeil, C.Rampley, P. Renaud, D. Burdeaux, D. Hill, C. Zhu, J. Wan, C. Gaw, F. Vanaverbeke, R. Embar NXP Semiconductors, Chandler, AZ

5b.4 (Invited) 3:00-3:30 PM – Ultra-high Speed InP/GaAsSb-based Type-II Double-heterojunction Bipolar Transistors and Transfer Technology onto SiC Substrate Yuta Shiratori1, Takuya Hoshi2, Hideaki Matsuzaki1 1NTT Device Technology Laboratories, NTT Corporation

3:30 PM - 4:00 PM Vendor Forum (VDI) / Optional Vendor Breakout 4:00 PM - 4:30 PM Primer Q & A 4:30 PM – 5.00PM Virtual Social Event

6a. Late News 1 Thursday 6:00 AM – Virtual Room A Session Chair: Breandán Ó hAnnaidh, Analog Devices Co-Chair: Sorin Voinigescu, University of Toronto

6a.1 6:00-6:20 AM – Ultra Broadband Low-Power 70 GHz Active Balun in 130-nm SiGe BiCMOS Aniello Franzese1, Mohamed H. Eissa1, Thomas Mausolf1, Dietmar Kissinger2, Renato Negra3, Andrea Malignaggi1 1IHP – Leibniz-Institut für innovative Mikroelektronik Frankfurt (Oder), Germany

2Institute of Electronic Devices and Circuits, Ulm University, Ulm, Germany

3Chair of High Frequency Electronics, RTWH Aachen, Aachen, Germany

6a.2 6:20-6:40 AM – A Highly-Efficient 120 GHz and 240 GHz Signal Source in A SiGe-Technology Florian Vogelsang1, David Starke1, Jonathan Wittemeier1, Holger Rückery2 and Nils Pohl1,3

1Institute of Integrated Systems, Ruhr-Universität Bochum, 44801 Bochum, Germany 2IHP - Leibniz-Institut für innovative Mikroelektronik, 15236 Frankfurt (Oder), Germany 3Fraunhofer Institute for High Frequency Physics and Radar Techniques, 53343 Wachtberg, Germany

6a.3 6:40-7:00 AM – A 24 GHz Sub-Harmonically Pumped Resistive Mixer in GaN HEMT Technology Yu Yan, Thanh Ngoc Thi Do, Dan Kuylenstierna Department of Microtechnology and Nanoscience Chalmers University of Technology Göteborg, Sweden

6a.4 7:00-7:20 AM – III-V Nanowire MOSFETs: RF-Properties and Applications Lars-Erik Wernersson Electrical and Information Technology Lund University Lund, Sweden

6b. Nonlinear Modeling of Compound Semiconductor Devices Thursday 6:00 AM – Virtual Room B Session Chair: Masaya Iwamoto, Keysight Technologies Co-Chair: Kevin Kim, NXP Semiconductors

6b.1 (Invited) 6:00-6:40 AM – Robust Extraction of Cardiff Model Parameters from Appropriately Tailored Measured Load-Pull Data Paul J Tasker

Cardiff University, Cardiff, Wales, UK

6b.2 6:40-7:00 AM – Reverse Intermodulation in Multi-Tone Array Transmitters Anton N. Atanasov1,2, Mark S. Oude Alink1, Frank E. van Vliet1,2

1Universitty of Twente, Netherlands 2TNO, Netherlands

6b.3 7:00-7:20 AM – Dependence of AM/PM Non-linearity on Source Field-plate in GaN HEMTs Sourabh Khandelwal1, Petra Hammes2, Marek Schmidt-Szalowski2, Amit Dikshit2, Menno Clerk2

1University of South Florida, Tampa, Florida, USA 2Ampleon, Nijmegen, Netherlands

7:20 AM - 7:50 AM Short Course 3 Q & A: High-Speed DACs for Millimeter-Wave Digital Arrays in FinFET CMOS, Boris Murmann, Stanford Univ., Palo Alto, CA, USA

7a. Late News 2 Thursday 2:00 PM – Virtual Room A Session Chair: Robert Howell Co-Chair: Jon Mooney, NGC

7a.1 2:00-2:20 PM – Configurable and Scalable High-Side or Low-Side Driver in BiCMOS with 20dBμV Emission at 88MHz S.N. Easwaran, S.V.Kashyap, D.Sreedharan, R.Hubbard, V.Devarajan, W.Ray

Texas Instruments Inc, 12500, TI BLVD, Dallas, Texas, USA

7a.2 2:20-2:40 PM – A High Efficiency 4-18 GHz GaN MMIC Power Amplifier based on 90nm T-gate GaN HEMT Technology Shuoqi Chen, Vipan Kumar, and Yu Cao Qorvo Inc, Richardson, TX, USA 75081

7a.3 2:40-3:00 PM – A 108-Gbps, 162-mW Cherry-Hooper Transimpedance Amplifier Luis A. Valenzuela, Aaron Maharry, Hector Andrade, Clint L. Schow, James F. Buckwalter University of California, Santa Barbara, USA

7b. SiGe Technology Applications Thursday 2:00 PM – Virtual Room B Session Chair: Jay John, NXP Semiconductors Co-Chair: Josef Boeck, Infineon Technologies AG

7b.1 (Invited) 2:00-2:40 PM – SiGe Microwave Phototransistors for Microwave-Photonics Applications Jean-Luc Polleux1, Francesco Peressutti1, Z.G.Tegegne1, M.Rosales1, J.M. Laheurte1, C.Algani 1, Carlos Viana 2

1 ESYCOM-CNRS, Université Gustave Eiffel, Noisy-le-Grand, France 2 ICON Photonics, SAS, Champs-sur-Marne, France

7b.2 (Invited) 2:40-3:20 PM – A Commercial Foundry Perspective of SiGe BiCMOS Process Technologies Edward Preisler

Tower Semiconductor, Newport Beach CA

3:30 PM - 4:30 PM Closing Session & Virtual Reception Thursday 3:30 PM – Social Room Session Chair: Bruce Green, NXP Co-chair: Craig Steinbeiser, Qorvo

Executive Committee Bruce Green NXP Semiconductors, Symposium Chair Craig Steinbeiser Qorvo, Technical Program Chair Simon Wood WolfSpeed, Technical Program Vice Chair Michael Schroter TU Dresden, Short Course Chair Steven Huettner Nuvotronics, Treasurer Rob Howell Northrup Grumman Mission Systems, Publicity Chair Doug Weiser Texas Instruments, Exhibition Chair Breandán Ó hAnnaidh Analog Devices, Publications Chair Jon Mooney Raytheon, Publications Co-Chair Shahriar Shahramian Nokia – Bell Labs, JSSC Guest Editor

Technical Program Committee

Analog, RF, and Microwave ICs Michael Roberg Qorvo, Chair Taylor Barton University of Colorado Boulder Jim Carroll Akash Systems Shuoqi Chen Qorvo Gayle Collins Obsidian Microwave, Chair Wei Kung Deng Richwave Sri Navaneeth Easwaran Texas Instruments Nabil El-Hinnawy TowerJazz Steven Huettner Nuvotronics Tomoya Kaneko NEC Corporation Bruce Kim City College of New York Mike Litchfield BAE Systems Jon Mooney Raytheon (Dallas, TX) Walter Nagy MACOM Arun Paidimarri IBM Tony Quach AFRL Thierry Taris University of Bordeaux Frank van Vliet TNO John Wood WolfSpeed Simon Wood WolfSpeed Jane Xu Skyworks Samet Zihir Renesas Electronics Kazuya Yamamoto Mitsubishi Electric Corporation

Compound Advanced Devices and Technologies

Parrish Ralston Northrup Grumman Mission Systems, Chair Ken Chu BAE SYSTEMS Sansaptak Dasgupta Intel Carl Dohrman Northrop Grumman Innovation Systems Patrick Fay University of Notre Dame Bruce Green NXP Semiconductors Rob Howell Northrup Grumman Mission Systems Hiroki Sugiyama NTT Device Technology Laboratories Hiroshi Yamamoto Sumitomo Electric Industries, Ltd. Akio Wakejima Nagoya Institute of Technology

Compound Semiconductor Modeling Masaya Iwamoto Keysight Technologies, Chair Mikael Garcia Analog Devices Subrata Halder Qorvo Kevin Kim NXP Semiconductors – RF Power Yueying Liu Wolfspeed Paul Tasker Cardiff University Yingying Yang Skyworks

Device Physics

Tomislav Suligoj University of Zagreb, Chair Martin Claus Infineion Guanghai Ding Analog Devices Vibhor Jain GLOBALFOUNDRIES Jonggook Kim Texas Instruments Kai Kwok Skyworks Jiahui Yuan SanDisk

High Speed Digital, Mixed-Signal, and Optoelectronic ICs Yuriy Greshishchev Ciena Corporation, Co-Chair Patrice Gamand XLIM, University Limoges, Co-Chair Kimia T. Ansari Huawei Koichi Murata NTT Munehiko Nagatani NTT Photonics Laboratories, NTT Corporation The' Linh Nguyen Finisar Corporation Johann-Christoph Scheytt University Paderborn Craig Steinbeiser Qorvo Thomas Toifl IBM Zurich Research Laboratory Sorin Voinigescu University of Toronto

mm-Wave and THz ICs

Shahriar Shahramian Nokia – Bell Labs, Co-Chair Nils Pohl Ruhr-University Bochum, Co-Chair Eric Bryerton Virginia Diodes Steven Gross Booz Allen Hamilton; SETA to DARPA/MTO Vadim Issakov Infineon Dietmar Kissinger Ulm University Wooram Lee IBM T.J Watson Research Center Alex Margomenos Infineon Technologies North America Miro Micovic Raytheon Harris Moyer HRL Laboratories William Peatman Qualcomm Technologies, Inc. Marc Rocchi OMMIC Frank van Vliet TNO Wibo Van Noort Texas Instruments Leonardo Vera Inphi Corp Hua Wang Georgia Tech Kazuya Yamamoto Mitsubishi Electric Corporation Bryan Yi-Cheng Wu Northrop Grumman Aerospace Systems

Silicon and Related Alloy Semiconductor Modeling

Sadayuki Yoshitomi Toshiba Corporation, Chair Breandán Ó hAnnaidh Analog Devices Andreas Pawlak Infineon Andrej Rumiantsev MPI Corporation Michael Schroter TU Dresden Jin Tang Texas Instruments Pete Zampardi Qorvo

Silicon and Related Alloy Semiconductor Processing

Jay John NXP Semiconductors, Chair Josef Boeck Infineon Pascal Chevalier STMicroelectronics Mattias Dahlstrom Texas Instruments Jack Pekarik GLOBALFOUNDRIES Holger Rucker IHP Microelectronics Todd Thibeault TowerJazz

Symposium Event Management Catherine Shaw C.Shaw, LLC John Hinch Omnipress Jessica Lotito IEEE Electron Devices Society Jim Skowrenski IEEE Electron Devices Society Sherry Russ Sills IEEE Meetings, Conferences and Events

CALL FOR PAPERS

2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and

Technology Symposium (BCICTS) INTEGRATED CIRCUITS and DEVICES in

December 5-8, 2021 Monterey, California USA, USA

INTEGRATED CIRCUITS and DEVICES in

GaAs, InP, GaN, SiGe, and other compound semiconductor and CMOS technologies

Sponsored by the IEEE Electron Devices Society, Technically co-sponsored by the Solid State Circuits Society and the Microwave

Theory & Techniques Society 2021 BCICTS Symposium

The 2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) is the IEEE-approved merger of the Bipolar/BiCMOS Circuits and Technology Meeting (BCTM) and the Compound Semiconductor IC Symposium (CSICS). BCICTS is the forum for developments in bipolar, BiCMOS, and com-pound semiconductor circuits, devices, and technology. Coverage includes all aspects of the technology, from materials, device fabrication, device phenomena, TCAD modeling, compact modeling, integrated circuit design, testing, and system applications. A wide range of integrated circuit technologies are covered including CMOS, bipolar and field-effect transistors realized in materials such as SiGe, GaAs, GaN, InP, SiC. The latest results in wireless, analog, RF, microwave, high-speed digital, mixed signal, optoelectronic, millimeter wave, and THz integrated circuits are embraced. Subject area groupings are: HIGH-SPEED DIGITAL, MIXED-SIGNAL, AND OPTOELECTRONIC ICs Mixed analog/digital ICs - Digital ICs - (high-speed) DACs and ADCs - Networking ICs, MUX/DEMUX, Clock and data recovery, Decision circuits, Equalizers - Optical data links, Laser and modulator drivers, optoelectronics and photonics ICs ANALOG, RF, AND MICROWAVE ICs Op amps - Voltage references and regulators - Integrated filters - Sensors and actuators - RF circuits and systems - Radio and transceiver subsystems - LNAs - AGCs - Mixers - Voltage controlled oscillators - Frequency synthesizers - Power amplifiers - RF switches - Noise and distortion suppression - RF Packaging - Integrated RF passives. Analog, RF, power conversion, High-voltage ICs - Biomedical electronics - Power Management ICs - Energy harvesting ICs - Motor controls - Analog subsystems within a VLSI chip - Packaging of high-performance ICs. mm-WAVE AND THZ ICs Millimeter - wave circuits and systems - THz circuits and systems. MM-Wave switches and amplifiers. Phased-array antenna circuits DEVICE PHYSICS: New device physics phenomena in Si, SiGe, SiC, GaN, MOS, and III-V HBTs and FETs - Device design issues and scaling limits - Hot electron effects and reliability physics - Transport and high field phenomena - Noise - Linearity/Distortion - Novel measurement techniques - Operation in extreme environments (low/high temperatures, radiation effects), and ESD phenomena. MODELING AND SIMULATION Improved silicon-based BJT and HBT models and physics-based modelling techniques - Improved III-V HBT and FET models and physics-based modelling techniques - Parameter extraction methods and test structures - High-frequency measurement, calibration and de-embedding techniques - RF and thermal simulation techniques - Modelling of passives, interconnect and packages - Statistical modelling - Device, process and circuit simulation - CAD/modelling of power devices - Packaging of power devices.

PROCESS AND DEVICE TECHNOLOGY Device and IC manufacturing processes, testing methodologies, & reliability - Integration of III-V devices on Si - High performance devices such as GaN power conversion devices - near-THz SiGe HBTs & InP HEMTs - Novel devices such as tunnel FETs (TFETs) - carbon nanotubes, MEMS, graphene & diamond transistors. Optoelectronic and photonic devices such as optical modulators, lasers, photodetectors, and Silicon Photonics - Thermal management technologies, thermal simulation - Advanced packaging of high-power devices and ICs. Advances in processes and device structures demonstrating high speed, low power, low noise, high current, high voltage, etc. BiCMOS processes - Advanced process techniques - Si and SiC homojunction bipolar/BiCMOS devices and SiGe heterojunction bipolar/BiCMOS devices - Manufacturing solutions related to Bipolar and BiCMOS yield improvements - Fabrication of high-performance passive components, sensors, and MEMs - Process technology related to discrete and integrated bipolar/BiCMOS power devices - IGBT, RF power devices. Wide bandgap bipolar devices (e.g., SiC) and related process technology - 3D Integration - Reliability and testing for IC manufacturing

IMPORTANT DATES Friday May 7, 2021 – Papers Due

Friday, June 25, 2021 – Decision E-mail Sent Friday, August 27, 2021 – Final Manuscript Due

Authors must submit a 4-page paper (including figures and other supporting material) of results not previously published or not already accepted by another conference. Papers will be selected on the basis of this submission. The paper must concisely and clearly state:

a) The purpose of the work b) What specific new results have been obtained c) How it advances the state-of-the-art or the industry d) References to prior state-of-the-art e) Sub-committee preference:

• Analog, RF, and Microwave ICs

• Device Physics

• High-Speed Digital, Mixed-Signal, & Optoelectronic ICs

• Modeling & Simulation

• mm-Wave and THz ICs

• Process & Device Technology Papers must include: title, author(s) name(s) and affiliation(s), corresponding authors’ postal and e-mail addresses, and telephone numbers. The committee will honor the authors’ committee preference but reserves the right to review the paper in other categories.

Company and governmental clearances must be obtained prior to submission of the abstract.

Accepted work may be used for publicity purposes. Portions of the abstracts may be quoted in articles publicizing the Symposium. Please note on the abstract if this is not acceptable.

Papers (PDF only) must be submitted electronically.

Authors will be informed of a decision by June 25, 2021. Authors of accepted papers are required to submit a final 4-page camera-ready PDF by August 27, 2021 for inclusion in the Symposium Digest.

Further questions on abstract submission may be addressed to the Symposium Technical Program Co-Chairs:

Bruce Green Craig Steinbeiser NXP Qorvo Ph: +1 480-413-4620 Ph: +1 972-994-4534 bruce.green@nxp.com Craig.Steinbeiser@Qorvo.com

Symposium information, including abstract submission instructions and a link to the abstract submission system is available on the BCICTS website at: http://www.bcicts.org