BiCMOS Integrated Circuit Design with Analog, Digital, and Smart Power Applications
Edited by
M. I. Elmasry Professor of Electrical and Computer Engineering
University of Waterloo
IEEE PRESS
A Selected Reprint Volume IEEE Solid-State Circuits Council, Sponsor
The Institute of Electrical and Electronics Engineers, Inc., New York
Contents
Preface xi Acknowledgments xiii
Analysis and Design of BiCMOS Integrated Circuits 1
Section 1.1 Introduction 3
1.1 Introduction to BiCMOS Integrated Circuits: A Tutorial 3 M. I. Elmasry
1.2 BiCMOS-Has the Promise Been Fulfilled? 15 A. R. Alvarez (IEDM, 1991)
1.3 High-Speed BiCMOS Technology with a Buried Twin 19 Well Structure T. Ikeda, A. Watanabe, Y. Nishio, I. Masuda, N. Tamba, M. Odaka, and K. Ogiue (IEEE Transactions on Electron Devices, June 1987)
1.4 Perspective on BiCMOS VLSIs 25 M. Kubo, I. Masuda, K. Miyata, and K. Ogiue (IEEE Journal of Solid-State Circuits, February 1988)
Section 1.2 Processing Technologies 32
1.5 Overview of BiCMOS Device and Process Integration (invited paper) 32 R. H. Havemann and R. H. Eklund
1.6 The Design and Characterization of Nonoverlapping Super 41 Self-Aligned BiCMOS Technology T. Y. Chiu, G. M. Chin, M. Y. Lau, R. C. Hanson, M. D. Morris, K. F. Lee, M. T. Y. Liu, A. M. Voschenkov, R. G. Swartz, V. D. Archer III, S. N. Finegan and M. D. Feuer (IEEE Transactions on Electron Devices, January 1991)
1.7 A High Performance 0.5-^m BiCMOS Technology for Fast 50 4-Mb SRAMs J. D. Hayden, T. C. Mele, A. H. Perera, D. Burnett, F. W. Walczyk, C. S. Lage, F. K. Baker, M. Woo, W. Paulson, M. Lien, Y.-C. See, D. Denning, and S. J. Cosentino (IEEE Transactions on Electron Devices, July 1992)
1.8 3.3V BINMOS Technology Using NPN Transistors Without 59 Buried Layers A. Shida, M. Kagamihara, M. Komatsu, K. Kumagai, and M. Hirata (IEDM, 1991)
1.9 A 0.4-micron Fully Complimentary BiCMOS Technology for 63 Advanced Logic and Microprocessor Applications S.W. Sun, P. G. Y. Tsui, B. M. Somero, J. Klein, F. Pintchovski, J. R. Yeargain, and B. Pappert (IEDM, 1991)
Section 1.3 Circuit Analysis and Techniques 67
1.10 Analysis and Optimization of BiCMOS Digital Circuit 67 Structures S. H. K. Embabi, A. Bellaouar, and M. I. Elmasry (IEEE Journal of Solid-State Circuits, April 1991)
1.11 A 1.5-V Full-Swing BiCMOS Logic Circuit 71 M. Hiraki, K. Yano, M. Minami, K. Sato, N. Matsuzaki, A. Watanabe, T. Nishida, K. Sasaki, and K. Seki (IEEE Journal of Solid-State Circuits, November 1992)
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Contents
1.12 Merged CMOS-Bipolar Current Switch Logic (MCSL) 77 W. Heimsch, B. Hoffmann, R. Krebs, E. G. Müllner, B. Pfäffel, and K. Ziemann (IEEE Journal of Solid-State Circuits, October 1989)
1.13 Multiemitter BiCMOS CML Circuits 82 M. Elrabaa and M. I. Elmasry (IEEE Journal of Solid-State Circuits, March 1992)
1.14 Quasi-Complementary BiCMOS for Sub-3-V Digital Circuits 87 K. Yano, M. Hiraki, S. Shukuri, Y. Onose, M. Hirao, N. Ohki, T. Nishida, K. Seki, and K. Shimohigashi (IEEE Journal of Solid-State Circuits, November 1991)
1.15 Merged BiCMOS Logic to Extend the CMOS/BiCMOS 98 Performance Crossover Below 2.5 V Supply R. B. Ritts, P. A. Raje, J. D. Plummer, K. C. Saraswat, and K. M. Cham (IEEE Journal of Solid-State Circuits, November 1991)
1.16 A New Methodology for Design of BiCMOS Gates and 106 Comparison with CMOS P. A. Raje, K. C. Saraswat, and K. M. Cham (IEEE Trans-actions on Electron Devices, February 1992)
1.17 Optimal Usage of CMOS Within a BiCMOS Technology 114 L. Wissel and E. L. Gould (IEEE Journal of Solid-State Circuits, March 1992
1.18 Design and Optimization of Buffer Chains and Logic Circuits 120 in a BiCMOS Environment M. S. Elrabaa and M. I. Elmasry (IEEE Journal of Solid-State Circuits, May 1992)
1.19 Accurate Delay Models for Digital BiCMOS 129 P. A. Raje, K. C. Saraswat, and K. M. Cham (IEEE Transactions on Electron Devices, June 1992)
1.20 Delay Analysis of BiNMOS Driver Including High 138 Current Transients J.-S. Yuan (IEEE Transactions on Electron Devices, March 1992)
1.21 An Analytical Model for the Determination of the Transient 144 Response of CML and ECL Gates M. Y. Ghannam, R. R Mertens, and R. J. Van Overstraeten (IEEE Transactions on Electron Devices, January 1990)
1.22 Fault Characterization, Testing Considerations and Design for 155 Testability of BiCMOS Logic Circuits A. E. Salama and M. I. Elmasry (IEEE Journal of Solid-State Circuits, June 1992)
Section 1.4 Scaling and Performance Limits 159
1.23 Scaling of Digital BiCMOS Circuits 159 A. Bellaouar, S. H. K. Embabi, and M. I. Elmasry (IEEE Journal of Solid-State Circuits, August 1990)
1.24 Scaling Rules for Bipolar Transistors in BiCMOS Circuits 169 G. P. Rosseel and R. W. Dutton (IEDM, 1989)
1.25 Performance-Driven Scaling of BiCMOS Technology 173 P. Raje, K. C. Saraswat, and K. M. Cham (IEEE Transactions on Electron Devices, March 1992)
Part 2 BiCMOS Digital Circuit Applications 183
Section 2.1 Introduction 185
2.1 An Overview of BiCMOS State-of-the-Art Digital Circuits (invited paper) 185 H. J. Shin
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Contents
Section 2.2 Gate Arrays 193
2.2 High Performance BiCMOS lOOK-Gate Array 193 J. D. Gallia et al. (IEEE Journal of Solid-State Circuits, February 1990)
2.3 0.5tim 2M-Transistor BiPNMOS Channeless Gate Array 200 H. Hara, T. Sakurai, M. Noda, T. Nagamatsu, K. Seta, H. Momose, Y. Niitsu, H. Miyakawa, and Y. Watanabe (IEEE Journal of Solid-State Circuits, November 1991)
2.4 A 100-MHz 64-Tap FIR Digital Filter in 0.8-nm BiCMOS 205 Gate Array T. Yoshino, R. Jain, P. T. Yang, H. Davis, W. Gass, and A. H. Shah (IEEE Journal of Solid-State Circuits, December 1990)
Section 2.3 ASICs 213
2.5 0.5[im BiCMOS Standard-Cell Macros Including 0.5W 3ns 213 Register File and 0.6W 5ns 32B Cache H. Hara, T. Sakurai, T. Nagamatsu, S. Kobayashi, K. Seta, H. Momose, Y. Niitsu, H. Miyakawa, T. Kuroda, K. Matsuda, Y. Watanabe, F. Sano, and A. Chiba (IEEE International Solid-State Circuits Conference, 1992)
2.6 BiCMOS Circuits for DPCM Coders in HDTV Systems 216 A. Rothermel (IEEE Journal of Solid-State Circuits, December 1990)
Section 2.4 Data and Signal Processors 222
2.7 3.3V BiCMOS Circuit Techniques for 250-MHz RISC 222 Arithmetic Modules K. Yano, M. Hiraki, S. Sukuri, M. Hanawa, M. Suzuki, S. Morita, A. Kawamata, N. Ohki, T. Nishida, and K. Seki (IEEE Journal of Solid-State Circuits, March 1992)
2.8 A Three-Million-Transistor Microprocessor 230 F. Abu-Nafal, et al. (IEEE International Solid-State Circuits Conference, 1992)
2.9 A BiCMOS 50MHz Cache Controller for a Superscaler 233 Microprocessor B. Joshi et al. (IEEE International Solid-State Circuits Conference, 1992)
2.10 A 1,000MIPS BiCMOS Microprocessor with Superscalar 236 Architecture O. Nishii, M. Hanawa, T. Nishimukai, M. Suzuki, K. Yano, M. Hiraki, S. Shukuri, and T. Nishida (IEEE International Solid-State Circuits Conference, 1992)
2.11 A 200-MFLOPS 100-MHz 64-b BiCMOS Vector-Pipelined 239 Processor (VPP) ULSI F. Okamoto, Y. Hagihara, C. Ohkubo, N. Nishi, H. Yamada, and T. Enomoto (IEEE Journal of Solid-State Circuits, December 1991)
2.12 250-MHz BiCMOS Super-High-Speed Video Signal Processor 247 (S-VSP) ULSI J. Goto, K. Ando, T. Inoue, M. Yamashina, H. Yamada, and T. Enomoto (IEEE Journal of Solid-State Circuits, December 1991)
Part 3 BiCMOS Memory Application 255
Section 3.1 Introduction 257
3.1 An Overview of BiCMOS State-of-the-Art Static and Dynamic 257 Memory Applications (invited paper) A. G. Eidin
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Contents
Section 3.2 BiCMOS Statte RAMs 268
3.2 BiCMOS Circuit Technology for a High-Speed SRAM 268 T. Douseka and Y. Ohmori {IEEE Journal of Solid-State Circuits, February 1988)
3.3 A 5-ns 1-Mb ECL BiCMOS SRAM 274 M. Takada, K. Nakamura, T. Takeshima, K. Furuta, T. Yamazaki, K. Imai, S. Ohi, Y. Sekine, Y. Minato, and H. Kimoto (IEEE Journal of Solid-State Circuits, October 1990)
3.4 A 3.8-ns 16K BiCMOS SRAM 279 W. Heimsch, R. Krebs, B. Pfäffel, and K. Ziemann {IEEE Journal of Solid-State Circuits, February 1990)
3.5 A 4-ns 4K x 1-bit Two-Port BiCMOS SRAM 285 T.-S. Yang, M. A. Horowitz, and B. A. Wooley (IEEE Journal of Solid-State Circuits, October 1990)
3.6 A 7-ns 1-Mb BiCMOS ECL SRAM with Shift Redundancy 295 A. Ohba, S. Ohbayashi, T Shiomi, S. Takano, K. Anami, H. Honda, Y. Ishigaki, M. Hatanaka, S. Nagao, and S. Kayano {IEEE Journal of Solid-State Circuits, April 1991)
3.7 A 6ns 4Mb ECL I/O BiCMOS SRAM with LV-TTL 300 Mask Option K. Nakamura, T. Oguri, T. Atsumo, M. Takada, A. Ikemoto, H. Suzuki, T Nishigori, and T Yamazaki (IEEE International Solid-State Circuits Conference, 1992)
3.8 A 9ns 4Mb BiCMOS SRAM with 3.3v Operation 303 H. Kato, A. Suzuki, T Hamano, T. Kobayashi, K. Sato, T Nakayama, H. Gojohbori, T Maeda, and K. Ochii {IEEE International Solid-State Circuits Conference, 1992)
Section 3.3 BiCMOS Dynamic RAMs 306
3.9 Trends in Megabit DRAM Circuit Design 306 K. Itoh {IEEE Journal of Solid-State Circuits, June 1990)
3.10 Comparison of CMOS and BiCMOS 1-Mbit DRAM 317 Performance T. Watanabe, G. Kitsukawa, Y Kawajiri, K. Itoh, R. Hori, Y. Ouchi, T Kawahara, and T. Matsumoto (IEEE Journal of Solid-State Circuits, June 1989)
3.11 BiCMOS Circuit Technology for High-Speed DRAM's 325 S. Watanabe, K. Sakui, T. Fuse, T. Hara, S. Aritome, and K. Hieda (IEEE Journal of Solid-State Circuits, January 1993)
3.12 Bipolar CMOS-merged Technology for a High-Speed 330 1-Mbit DRAM Y. Kobayashi, K. Asayama, M. Oohayashi, R. Hori, G. Kitsukawa, and K. Itoh {IEEE Transactions on Electron Devices, April 1989)
3.13 Substrate Current Reduction Techniques for BiCMOS DRAM 335 T. Kawahara, G. Kitsukawa, H. Higuchi, Y. Kawajiri, T. Watanabe, K. Itoh, R. Hori, Y. Kobayashi, and T. Matsumoto (IEEE Journal of Solid-State Circuits, October 1989)
3.14 Deep-Submicrometer BiCMOS Circuit Technology for 343 Sub-10-ns ECL 4-Mb DRAMs T. Kawahara, Y. Kawajiri, G. Kitsukawa, K. Sagara, Y Kawamoto, T. Akiba, S. Kato, Y. Kawase, and K. Itoh (IEEE Journal of Solid-State Circuits, April 1992)
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Contents
Section 3.4 BiCMOS Nonvolatile Memories 350
3.15 A 3.6ns 1Kb ECL I/O BiCMOS U.V. EPROM 350 D. Smith, J. Zeiter, T. Bowman, J. Rahm, B. Kertis, A. Hall, S. Natan, L. Sanderson, R. Tromp, and J. Tsang {International Symposium on Circuits and Systems, 1990)
3.16 Very High-Speed ROM Using Bipolar/CMOS Technology 354 K. Kurita, T. Hotta, M. Ueno, and A. Hotta {Electronics and Communications in Japan, 1988)
3.17 BiFAMOS Technology for High Speed Mega-Bit EPROMs 362 G. J. Hu, L. C. Tran, P. Keshtbod, J. Segal, K. H. Park, T. Amin, B. Prickett, S. C. Tsao, J. Yen, E. Smith, J. Bornstein, and A. R. Alvarez (7992 Symposium on VLSI Technology Digest of Technical Papers, 1992)
BiCMOS Analog Circuit Applications 365
Section 4.1 Introduction 367
4.1 Analog Circuit Design in BiCMOS Technology: An Overview (invited paper) 367 B. Leung
Section 4.2 BiCMOS Analog Circuit Design 374
4.2 Future of Analog in the VLSI Environment 374 E. V. Vittoz {International Symposium on Circuits and Systems, 1990)
4.3 The Art of Analog Circuit Design in a Digital VLSI World 378 B. J. Hosticka and W. Brockherde {International Symposium on Circuits and Systems, 1990)
4.4 BiCMOS Analog Circuit Techniques 382 B. A. Wooley {International Symposium on Circuits and Systems, 1990)
Section 4.3 BiCMOS Analog Circuits 386
4.5 A Single-Power-Supply 10-b Video BiCMOS Sample-and- 386 Hold IC K. Tsugaru, Y. Sugimoto, M. Noda, T. Ito, and Y. Suwa {IEEE Journal of Solid-State Circuits, June 1990)
4.6 A 1.2|im BiCMOS 100MHz Sample-and-Hold Circuit with a 393 Constant-Impedance Slew-Enhanced S&mpling Gate M. H. Wakayama, H. Tanimoto, T. Tasai, and Y. Yoshida {IEEE International Solid-State Circuits Conference, 1992)
4.7 A 12-b 750-ns Subranging A/D Converter with 396 Self-Correcting S/H D. A. Mercer {IEEE Journal of Solid-State Circuits, December 1991)
4.8 A 10-bit Video BiCMOS Track-and-Hold Amplifier 406 M. Nayebi and B. A. Wooley {IEEE Journal of Solid-State Circuits, December 1989)
4.9 An 8-bit 200-MHz BiCMOS Comparator 416 P. J. Lim and B. A. Wooley {IEEE Journal of Solid-State Circuits, February 1990)
4.10 A BiCMOS PLL-Based Data Separator Circuit with High 423 Stability and Accuracy S. Miyazawa, R. Horita, K. Hase, K. Kato, and S. Kojima {IEEE Journal of Solid-State Circuits, February 1991)
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Contents
4.11 A High-Frequency Fully Differential BiCMOS Operational 429 Amplifier A. N. Karanicolas, K. K. O, J. Y. A. Wang, H.-S. Lee, and R. L. Reif (IEEE Journal of Solid-State Circuits, March 1991)
4.12 1.5-V High-Performance SC Filters in BiCMOS Technology 435 R. Castello and L. Tomasini (IEEE Journal of Solid-State Circuits, July 1991)
4.13 Tunable BiCMOS Continuous-Time Filter for High-Frequency 442 Applications R. Alini, A. Baschirotto, and R. Castello (IEEE Journal of Solid-State Circuits, December 1992)
4.14 Design Considerations of High-Dynamic-Range Wide-Band 453 Amplifiers in BiCMOS Technology Z.-Y. Chang, W. M. C. Sansen, and M. S. J. Steyaert (IEEE Journal of Solid-State Circuits, November 1991)
Part 5 BiCMOS Smart Power Applications 461
Section5.1 Introduction 463
5.1 An Overview of BiCMOS State-of-the-Art Smart Power 463 Applications (invited paper) J. S. T. Huang
5.2 Evolution of MOS-Bipolar Power Semiconductor Technology 471 J. Baliga (Proceedings ofthe IEEE, April 1988)
5.3 A Comparison Between BIMOS Device Types 481 M. S. Adler (IEEE Transactions on Electron Devices, February 1986)
Section 5.2 BiCMOS Power and Smart Power Circuits 489
5.4 High-Voltage Technology Offers New Solutions for Interface 489 Integrated Circuits G. Thomas, G. Troussel, and F. Vialettes (IEEE Transactions on Electron Devices, December 1989)
5.5 A BiCMOS Thermal Head Intelligent Driver with Density 497 Controllers for Full-Tone Rendition Printers M. Tsumura, R. Takeuchi, and I. Shimizu (IEEE Journal of Solid-State Circuits, April 1988)
Author Index 501
Subject Index 505
Editor's Biography 513
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