1/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
Benefits of SRAM design with
Tunnel FETs
Costin Anghel, Andrei Vladimirescu, Amara Amara Institut Superieur d'Electronique de Paris (Paris, FR), [email protected]
2/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
• A closer look on the TFET characteristics • TFET vs. CMOS
• TFET vs. TFET • What should we expect as benefit from TFET?
• First benchmark – ring oscillator • Second benchmark – SRAM cells - Half Selection issue - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines
• Conclusion
Outline:
3/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
• A closer look on the TFET characteristics • TFET vs. CMOS
• TFET vs. TFET • What should we expect as benefit from TFET?
• First benchmark – ring oscillator • Second benchmark – SRAM cells - Half Selection issue - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines
• Conclusion
Outline:
4/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
TFET vs. CMOS
n+ n+ i
Gate Drain Source
Oxide
CMOS n-‐type
p+ n+ i
Gate Drain Source
Oxide
TFET n-‐type
TFET:
Pros.: Extremely Low IOFF
SS below 60mV/dec
Cons.: Low ION
R&D needed
CMOS:
Pros.: classical device
ION within the ITRS targets
Cons.: power issue
5/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
TFET vs. CMOS
TFET: ideal device
A.M. Ionescu, H. Riel, Nature, Vol. 479, pp.329-337, 2011.
ION is NOT so important
as long as:
IEFF is carefully optimized
Low IOFF
Steep characteristic è
improved ION/IOFF ratio
6/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
• A closer look on the TFET characteristics • TFET vs. CMOS
• TFET vs. TFET • What should we expect as benefit from TFET?
• First benchmark – ring oscillator • Second benchmark – SRAM cells - Half Selection issue - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines
• Conclusion
Outline:
7/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
Homo vs. Hetero Junction TFET
Homo-‐Junc5on TFET
Hetero-‐Junc5on TFET
p+ n+ i
Gate Drain Source
Oxide
Pros.: Theoretically higher ION
Theoretically lower VDD
Critical research mass attained
Cons.: High density of traps
Majority of demonstrators show deceiving performance
Pros.: Easier to fabricate
Low density of traps
Some demonstrators – already present
Cons.: Lower ION current
Critical research mass not attained
p+ n+ i
Gate Drain Source
Oxide
8/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
Homo-‐Junc5on TFET
Hetero-‐Junc5on TFET
Makosiej et al. Proc. of ISCAS 2012 Kim et al. Proc. of ISLPED 2009
Forward Output Characteris5cs
9/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
Homo-‐Junc5on TFET
Hetero-‐Junc5on TFET
Makosiej et al. Proc. of ISCAS 2012 Kim et al. Proc. of ISLPED 2009
Reverse Output Characteris5cs ”UNIDIRECTIONAL” behaviour
10/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
• A closer look on the TFET characteristics • TFET vs. CMOS
• TFET vs. TFET • What should we expect as benefit from TFET?
• First benchmark – ring oscillator • Second benchmark – SRAM cells - Half Selection issue - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines
• Conclusion
Outline:
11/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
TFET circuits – the Ring oscillator
TFET presents over and under-shoots due to its high Miller capacitance.
TFET CMOS PTM
12/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
TFET circuits – the Ring oscillator
Adam Makosiej et al. ISCAS, 2012.
0.01
0.10
1.00
10.00
0.9 1 1.1 1.2 1.3 1.4
Frequency (GHz)
Supply Voltage (V)
TFET
TFET -‐ low VOFF
PTM
The TFET circuits are not as fast as CMOS, however they dissipate significant less static power
13/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
• A closer look on the TFET characteristics • TFET vs. CMOS
• TFET vs. TFET • What should we expect as benefit from TFET?
• First benchmark – ring oscillator • Second benchmark – SRAM cells - Half Selection issue - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines
• Conclusion
Outline:
14/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
• Why do we really need SRAMs?
SRAM – what is this memory good for ?
- SPEED
- Low power (static and dynamic)
• Which are the other requirements for SRAM?
- Compact cell (low area)
15/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
TFET circuits – matrix
ACC – accessed; HS – half selected; WD – write disturb; RET – reten<on
The power consump<on has to be reduced for all cells during all opera5on modes (i.e. read, write and reten)on)
16/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
• A closer look on the TFET characteristics • TFET vs. CMOS
• TFET vs. TFET • What should we expect as benefit from TFET?
• First benchmark – ring oscillator • Second benchmark – SRAM cells - Half Selection issue - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines
• Conclusion
Outline:
17/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
Half selec5on in CMOS
ACC cell HS cell
WL activation leads to leakage in the HS cells
VDD
0 1
VDD VDD VDD
18/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
TFET-‐based SRAM cells
CMOS – 6T cell
The easiest way to build a TFET SRAM cell – mimic 6T CMOS cell
TFET – 6T cell
19/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
TFET benefit è reduced leakage in HS cells
TFET “unidirec<onality” HELPS reducing parasi<c current in HS cells
0 1
VSS VSS
ACC cell HS cell
VSS + ΔV VSS + ΔV
20/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
• A closer look on the TFET characteristics • TFET vs. CMOS
• TFET vs. TFET • What should we expect as benefit from TFET?
• First benchmark – ring oscillator • Second benchmark – SRAM cells - Half Selection issue - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines
• Conclusion
Outline:
21/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
Saripalli et al. Proc. of Nanoarch 2011
TFET-‐based SRAM cells
CMOS – 6T cell TFET – 6T cell
TFET “unidirec<onal” – how to connect the access transistors?
22/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
07/11/2013 NanoInnov C. ANGHEL
READ WRITE TFET circuits – 6T SRAM
Inward access TFETs – Doesn’t work in write – position of the source of the access transistors
Outward access TFETs – Could work – but problems – see next slides
Kim et al., ISLPED 2009
23/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
Why 6T outward cell doesn’t work
Extremely low SNMs regardless the TFET technology !!! – need different topology for TFET SRAM cell
0.6 0.8 1 1.4 2 2.50
0.05
0.1
Pull Up Ratio (PU)
SN
M V
alu
es [
V]
WSNMRSNM
0.6 0.8 1 1.4 2 2.50
0.05
0.1
Pull Up Ratio (PU)
SN
M V
alu
es [
V]
Homo-‐Junc5on TFET
Hetero-‐Junc5on TFET
Makosiej et al. Proc. of ISCAS 2012 Kim et al. Proc. of ISLPED 2009
24/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
• A closer look on the TFET characteristics • TFET vs. CMOS
• TFET vs. TFET • What should we expect as benefit from TFET?
• First benchmark – ring oscillator • Second benchmark – SRAM cells - Half Selection issue - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines
• Conclusion
Outline:
25/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
SRAM with separated read port
Ø Use the unidirectional condution of TFET to reduce the no. of transistors
CMOS – 8 T cell TFET – 7T cell
Kim et al. Proc. of ISLPED 2009 Verma, Chandrakasan, IEEE J. Solid-‐State Circuits, 43, 141–149, 2008.
26/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
Why 7T TFET cell doesn’t work
Ø In “write” one access transistor is reversed biased è its current is NOT controlled by its gate.
Write
Kim et al. Proc. of ISLPED 2009
Reten5on BLL=0V BLL=0V BLL=0V BLL=VDD
27/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
Homo-‐Junc5on TFET
Hetero-‐Junc5on TFET
Makosiej et al. Proc. of ISCAS 2012 Kim et al. Proc. of ISLPED 2009
Why 7T TFET cell doesn’t work
28/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
Outward access TFETs – leakage problem
Kim et al., ISLPED 2009 (D. Blaauw Univ. Of Michigan).
Why 7T TFET cell doesn’t work
29/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
Outward access TFETs – leakage problem BLL (GND) BLR (VDD)
WL WL
VDD
GND
TR1 TR2
DR1 DR2
LD1 LD2
“1” ”0"
Ileak
WL WL
VDD
GND
TR1 TR2
DR1 DR2
LD1 LD2
“1”"0"
Iwrite Ileak
WL WL
VDD
GND
TR1 TR2
DR1 DR2
LD1 LD2
“1””0"
Ileak
Leakage - cumulative and depends on the size of the written word
BLL (GND) BLR (VDD)
WL WL
VDD
GND
TR1 TR2
DR1 DR2
LD1 LD2
“1” ”0"
Ileak
WL WL
VDD
GND
TR1 TR2
DR1 DR2
LD1 LD2
“1”"0"
Iwrite Ileak
WL WL
VDD
GND
TR1 TR2
DR1 DR2
LD1 LD2
“1””0"
Ileak
BLL (GND) BLR (VDD)
WL WL
VDD
GND
TR1 TR2
DR1 DR2
LD1 LD2
“1” ”0"
Ileak
WL WL
VDD
GND
TR1 TR2
DR1 DR2
LD1 LD2
“1”"0"
Iwrite Ileak
WL WL
VDD
GND
TR1 TR2
DR1 DR2
LD1 LD2
“1””0"
Ileak
WRITE Word
Leakage
Leakage
Why 7T TFET cell doesn’t work
30/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
Outward access TFETs – leakage problem How important is this leakage at the cell level?
Our sims: 32 nA in a cell in “write disturb”
EX: 1k bit – 992 x 32nA leakage in the worst case ≃ 30µA
Why 7T TFET cell doesn’t work
31/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
Outward access TFETs – capacitance discharge problem
BLL (GND) BLR (VDD)
WL WL
VDD
GND
TR1 TR2
DR1 DR2
LD1 LD2
“1” ”0"
Ileak
WL WL
VDD
GND
TR1 TR2
DR1 DR2
LD1 LD2
“1”"0"
Iwrite Ileak
WL WL
VDD
GND
TR1 TR2
DR1 DR2
LD1 LD2
“1””0"
Ileak
1 0
0 WL
TR2 1
0
0
WL
TR2 0
-1
-1High capacitance mode
Charging….
Why 7T TFET cell doesn’t work
32/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
Outward access TFETs – capacitance discharge problem
How important is this leakage at the cell level?
Our sims: 300 nA in a cell in “write disturb” è Flipping BLL and BLR is not a good option in TFET cells
Why 7T TFET cell doesn’t work
33/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
• A closer look on the TFET characteristics • TFET vs. CMOS
• TFET vs. TFET • What should we expect as benefit from TFET?
• First benchmark – ring oscillator • Second benchmark – SRAM cells - Half Selection issue - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines
• Conclusion
Outline:
34/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
Different TFET SRAM cells were proposed by several groups They are all based on flipping the bitlines during write operation
Other TFET cells
Singh et al., 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010.
35/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
Different TFET SRAM cells were proposed by several groups They are all based on flipping the bitlines during write operation
Other TFET cells
Saripalli et al., Nanoarch 2011 (S. Datta, Penn State & Intel).
36/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
• A closer look on the TFET characteristics • TFET vs. CMOS
• TFET vs. TFET • What should we expect as benefit from TFET?
• First benchmark – ring oscillator • Second benchmark – SRAM cells - Half Selection issue - 6T TFET cell - 7T TFET cell - Other TFET cells - 8T with separated word lines
• Conclusion
Outline:
37/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
TFET circuits – new design Idea: Do not flip the bitlines during WRITE but use two wordlines
BLL(VDD)
BLR(0.6V/GND)
V1 V2
WL1 WL1
WL2 WL2
VDD
GND
TR1
TR2
TR3
TR4
DR1 DR2
LD1 LD2
Adam Makosiej et al. ISCAS, 2012.
WRITE 1
WRITE 0
No Half Selection or Write Disturb issues
38/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
Our 8T design – performance
- estimated operation speed: 300MHz for read and 1GHz for write - 5 orders of magnitude lower average leakage with respect to low power PTM
Adam Makosiej et al. ISCAS, 2012.
120mV @ VDD=1V 200mV @ VDD=1V
39/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
Comparison with CMOS
- TFET cell offers comparable performance for the cell
Fukuda et al, ISSCC, 2014 (Toshiba)
CMOS TFET Technology (nm) 65 28 Leakage (fA/cell) 27 42
Speed 7ns 3.3ns (read) 1ns (write)
VDD (V) 1.2 1 Cell Size (µm2) 2.159 0.338
Scalable No Yes
- TFET cell size is 6.38 times smaller with respect to CMOS cell
40/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
Conclusion: - Half Selection and Write Disturb – avoided - Reasonable margins – obtained - Reasonable speed – obtained - Very low static power – obtained - Reduced area - obtained
TFET can replace the CMOS in SRAM for low power applications
41/41 26/09/2014 – ESSDERC e2-SWITCH Workshop
C. ANGHEL
Many Thanks to: - Hraziia, Adam Makosiej, Navneet Gupta - Prof. Andrei Vladimirescu, Prof. Amara Amara
- Cyrille Le Royer – CEA LETI - Olivier Thomas – CEA LETI
Thank you for your attention!
