CD a 3101 Supplement

8/13/2019 CD a 3101 Supplement

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CDA 3101: Introduction to Computer Hardware andOrganization

Supplementary Notes

Charles N. WintonDepartment of Computer and Information Sciences

University of North FloridaJacksonville, FL 32224-2645

Levels of organization of a computer system:

a) Electronic circuit levelb) Logic level - combinational logic *, sequential logic *,

register-transfer logic *c) Programming level - microcode programming *,

machine/assembly language programming, high-level

language programmingd) Computer systems level - systems hardware * (basic

hardware architecture and organization - memory, CPU(ALU, control unit), I/0, bus structures), systemssoftware, application systems

* topics discussed in these notes

Objectives:

Understand computer organization and component logic Boolean algebra and truth table logic

Integer arithmetic and implementation algorithms IEEE floating point standard and floating point algorithms Register contruction Memory construction and organization Register transfer logic CPU organization Machine language instruction implementation

Develop a foundation for Computer architecture Microprocessor interfacing System software

Sections : combinational logic sequential logic computer architecture

200 5


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Contents

Section I - Logic Level: Combinational Logic.................................................... 1Table of binary operations .................................................................. 3 Graphical symbols for logic gates ........................................................... 4Representing data ........................................................................... 6

2s complement representation .......................................................... 10 Gray code .............................................................................. 15

Boolean algebra ............................................................................ 16 Canonical forms ............................................................................ 22

and notations .......................................................................... 23NAND-NOR conversions ....................................................................... 23Circuit analysis ........................................................................... 25 Circuit simplification: K-maps ............................................................. 25 Circuit design ............................................................................. 33Gray to binary decoder ..................................................................... 35 BCD to 7-segment display decoder ........................................................... 36Arithmetic circuits ........................................................................ 39AOI gates .................................................................................. 42Decoders/demultiplexers .................................................................... 43Multiplexers ............................................................................... 44Comparators ................................................................................ 46Quine-McCluskey procedure.................................................................. 48

Section II - Logic Level: Sequential Logic..................................................... 50 Set-Reset (SR) latches ..................................................................... 51 Edge-triggered flip-flops .................................................................. 54An aside about electricity ................................................................. 56

(Ohmss Law, resistor values, batteries, AC)D-latches and D flip-flops ................................................................. 58T flip-flops and JK flip-flops ............................................................. 60Excitation controls ........................................................................ 61Registers .................................................................................. 64Counters ................................................................................... 65Sequential circuit design finite state automata .......................................... 66Counter design ............................................................................. 70Moore and Mealy circuits ................................................................... 72Circuit analysis ........................................................................... 72 Additional counters ........................................................................ 74Barrel shifter ............................................................................. 77Glitches and hazards ....................................................................... 78Constructing memory ........................................................................ 83International Unit Prefixes (base 10) ...................................................... 88Circuit implementation using ROMs .......................................................... 89Hamming Code ............................................................................... 93

Section III Computer Systems Level........................................................... 96Representing numeric fractions ............................................................. 96 IEEE 754 Floating Point Standard ........................................................... 98Register transfer logic ................................................................... 101Register transfer language (RTL) .......................................................... 102UNF RTL .................................................................................. 106 Signed multiply architecture and algorithm ................................................ 112 Booths method ............................................................................ 114 Restoring and non-restoring division ...................................................... 11 7 Implementing floating point using UNFRTL .................................................. 125Computer organization ..................................................................... 128Control unit .............................................................................. 129Arithmetic and Logic unit ................................................................. 129CPU registers ............................................................................. 130 Single bus CPU organization ............................................................... 131 Microcode signals ......................................................................... 132 Microprograms ............................................................................. 134 Branching ................................................................................. 136 Microcode programming ..................................................................... 137Other machine language instructions ....................................................... 137Index register ............................................................................ 140 Simplified Instructional Computer (SIC) ................................................... 143Architectural enhancements ................................................................ 144CPU-memory synchronization ................................................................ 146Inverting microcode ....................................................................... 148Vertical microcode ........................................................................ 149 Managing the CPU and peripheral devices ................................................... 149 The Z80 ................................................................................... 152


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Logic level: Combinational Logic

Combinational logic is characterized by functional specificationsusing only binary valued inputs and binary valued outputs

Remark: for given values of r and s, the number of possible functionsis finite since both the domain and the range of functions are finite,of size 2 r and 2 s respectively (this is because the r input variablesand the s output variables assume only the binary values 0 and 1).Although finite, it is worth noting that in practice the number of

functions is usually quite large:

For example, for r = 5 input variables and s = 1 output variable, thedomain consists of the 2 5 = 32 possible input combinations of thetwo binary input values 0 and 1.

To specify a function, each of these 32 possible input combinationsmust be assigned a value in the range, which consists of the twobinary output values 0 and 1.

This yields 2 32 = 4 billion such functions of 5 variables!

In general, with r input variables and s output variables, the domainconsists of the k = 2 r combinations of the binary input values. Therange consists of the j = 2 s combinations of the binary output values.To specify a function, each of the j input combinations must beassigned to 1 of k possible values in the range. Since there are j k possible ways to do this, there are j k functions having r inputs and soutputs.

Each such function corresponds to a logic circuit having r(binary-valued) inputs and s (binary-valued) outputs.

When r = 2 input variables and s = 1 output variable, there are 2 4 = 16possible functions (circuits), each having the basic appearance

Recall that functions of 2 variables are called binary operations. Forthe usual algebra of numbers these include the familiar operations ofaddition, subtraction, multiplication, and division and as many moreas we might care to define.

combinationallogic

r inputvariables

X

s outputvariables

Z... ...

Z=f(X) ( Z is a function of X )

X

Y Z = f(X,Y) f


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For circuit logic, the input variables are restricted to the values 0and 1, so there are only 4 possible input combinations of X and Y,yielding exactly 16 possible binary operations. The correspondinglogic circuits provide fundamental building blocks for more complexlogic circuits. Such fundamental circuits are termed logic gates.Since there are only 16 of them, they can be listed out - seeoverleaf. They are named for ease of reference and to reflect commonterminology.

It should be noted that some of the binary operation are "degenerate."In particular,

Zero (X,Y) and One (X,Y) depend on neither X nor Y to determine theiroutput;

X(X,Y) and NOT X (X,Y) have output determined strictly by X;Y(X,Y) and NOT Y (X,Y) have output determined strictly by Y.

X and NOT X operations (or Y and NOT Y , for that matter) are usuallythought of as unary operations (functions of 1 variable) rather than

degenerate binary operations. As unary operations they arerespectively termed the " identity " and the " complement ".


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TABLE OF BINARY OPERATIONS

Inhibit X Inhibit Y X Y Zero AND on Y=1 X on X=1 Y XOR OR NOR COINC NOT Y Y X

0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1

0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1

1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1

1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0


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The complement (or NOT ) is designated by an overbar; e.g.,_X_ is the

complement of X.

The other most commonly employed binary operations for combinationallogic also have notational designations; e.g.,

AND is designated by , e.g., X YOR is designated by +, e.g., X + Y

NAND is designated by , e.g., X Y NOR is designated by , e.g., X Y

XOR is designated by , e.g., X YCOINCIDENCE is designated by , e.g., X Y.

Note that if we form the simple composite function f (NOT f, orthe complement of f), that

_f_

(X) =_f__

(__X__

) and=f= = f

Moreover, X Y =_X____

____

Y_ = X Y(NAND NOT AND) - Sheffer stroke

X Y =_X____

+____

Y_ (NOR = NOT OR) - Pierce arrow

X Y =_X____

____Y_ (COINC = complement of XOR)

In particular, NAND and AND, OR and NOR, XOR and COINC arerespectively complementary in the sense that each is respectively thecomplement of the other.

Rather than use a general graphical " logic gate " designation

ANSI (American National Standards Institute) has standardized on thefollowing graphical symbols for the most commonly used logic gates.

AND () NAND ( ) XOR ( )

OR (+) NOR ( ) COINC ( )

NOT

X

Y Z = f(X,Y)


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.f(A,B,C,D).

Composite functions such as f(g(x)) can be easily represented usingthese symbols; e.g., consider the composite

f(A,B,C,D) = ((A_B_

) C) ((A C) _D_

)

This is easily represented as a 3-level circuit diagrammed by:

AB

C

D

The level of a circuit is the maximal number of gates an input signalhas to travel through to establish the circuit output. Normally, bothan input signal and it's inverse are assumed to be available, so theNOT gate on B does not count as a 4 th level for the circuit.

Note that the behavior of the above circuit can be totallydetermined by evaluating its behavior for each possible inputcombination (we'll return to determining its values later):

A B C D f(A,B,C,D)

0 0 0 0 00 0 0 1 10 0 1 0 00 0 1 1 00 1 0 0 00 1 0 1 10 1 1 0 00 1 1 1 01 0 0 0 01 0 0 1 01 0 1 0 11 0 1 1 01 1 0 0 01 1 0 1 01 1 1 0 01 1 1 1 1

Note that this table provides an exhaustive specification of the logiccircuit more compactly given by the above algebraic expression for f.Its form corresponds to the "truth" tables used in symbolic logic. Forsmall circuits, the truth table form of specifying a logic function isoften used.

The inputs to a logic circuit typically represent data values encodedin a binary format as a sequence of 0's and 1's. The encoding schememay be selected to facilitate manipulation of the data. For example,if the data is numeric, it is normally encoded to facilitateperforming arithmetic operations. If the data is alphabetic


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characters, it may be encoded to facilitate operations such assorting. There are also encoding schemes to specifically facilitateeffective use of the underlying hardware. A single input line isnormally used to provide a single data bit of information to a logiccircuit, representing the binary values of 0 or 1. At the hardwarelevel, 0 and 1 are typically represented by voltage levels; e.g., 0 byvoltage L (" low ") and 1 by voltage H (" high "). For the TTL(Transistor-Transistor Logic) technology, H = +5V and L = OV (H isalso referenced as V cc - " common cathode " and L as GND or " ground ").

Representing Data

There are three fundamental types of data that must be considered:

logical data (the discrete truth values - True and False) numeric data (the integers and real numbers) character data (the members of a defined finite alphabet)

Logical data representation:

There is no imposed standard for representing logical data in computerhardware and software systems, but a single data bit is normally usedto represent a logical data item in the context, of logic circuits,with " True " represented by 1 and " False " by 0. This is therepresentation implicitly employed in the earlier discussion ofcombinational logic circuits, which are typically implementations oflogic functions described via the mechanisms of symbolic logic. If theroles of 0 and 1 are reversed (0 representing True and 1 representingFalse), then the term negative logic is used to emphasize the changein representation for logical data.

Numeric data:

The two types of numeric data,

integers real numbers

are represented very differently. The representation in each case mustdeal with the fact that a computing environment is inherently finite.

Integers:

When integers are displayed for human consumption we use a " baserepresentation . This requires us to establish characters whichrepresent the base digits. Since we have ten fingers, the naturalhuman base is ten and the Arabic characters

0, 1, 2, 3, 4, 5, 6, 7, 8, 9

are used to represent the base digits. Since logic circuits deal withbinary inputs (0 or 1), the natural base in this context is two. Ratherthan invent new characters, the first two base ten characters (0 and 1)


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are used to represent the base two digits. Any integer can berepresented in any base, so long as we have a clear understanding ofwhich base is being used and know what characters represent its digits.For example, 19 10 indicates a base ten representation of nineteen. Inbase two it is represented by 1 0 0 1 1 2 . When dealing differentbases, it is important to be able to convert from the representation inone base to that of the other. Note that it is easy to convert frombase 2 to base 10, since each base 2 digit can be thought of asindicating the presence or absence of a power of 2.

1 0 0 1 1 2 = 1 2 4 + 0 2 3 + 0 2 2 + 1 2 1 + 1 2 0

= 16 + 0 + 0 + 2 + 1 = 19 10 = 1 10 1 + 9 10 0

A conversion from base 10 to base 2 is more difficult but stillstraight forward. It can be handled "bottom-up" by repeated division by2 until a quotient of 0 is reached, the remainders determining thepowers of 2 that are present:

19/2 = 9 R 1 (2 0 is present)9/2 = 4 R 1 (2 1 is present)4/2 = 2 R 0 (2 2 is not present)2/2 = 1 R 0 (2 3 is not present)1/2 = 0 R 1 (2 4 is present)

The conversion can also be handled "top-down" by iterativelysubtracting out the highest power of 2 present until a difference of 0is reached:

19 - 16 = 3 (1) (16=2 4 is present so remove 16)no 8's (0) ( 8=2 3 is not present in what's left)

no 4's (0) ( 4=22 is not present)

3 - 2 = 1 (1) ( 2=2 1 is present so remove 2)1 - 1 = 0 (1) ( 1=2 0 is present in what's left)

Bases which are powers of 2 are particularly useful for representingbinary data since it is easy to convert to and from among them. Themost commonly used are base 8 ( octal ) which uses as base digits

0, 1, 2, 3, 4, 5, 6, 7

and base 16 (hexadecimal) which uses as base digits

0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F

where A, B, C, D, E, F are the base digits for ten, eleven, twelve,thirteen, fourteen, and fifteen. An n-bit binary item can easily beviewed in the context of any of base 2, base 8, or base 16 simply byappropriately grouping the bits; for example, the 28 bit binary item


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1 4 6 5 3 4 0 0 2 4| | | | | | | | | |

1 1 0 0 1 1 0 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0| | | | | | | |

C D 5 C 0 1 4

is easily seen to be 1465340024 8 = CD5C014 16 when the bits are groupedas indicated (using a calculator that handles base conversions, you candetermine that the base ten value is 215334932 10 ; note that suchcalculators are typically limited to ten base 2 digits, but handle 8hexadecimal digits, effectively extending the range of the calculatorto 32 bits when the hexadecimal digits are viewed as 4-bit chunks).

Since it is easier to read a string of hexadecimal (hex) digits than astring of 0's and 1's, and the conversion to and from base 16 is sostraightforward, digital information of many bits is frequentlydisplayed using hex digits (or sometimes octal, particularly for olderequipment).

Since digital circuits generally are viewed as processing binary data,a natural way to encode integers for the use by such circuits is touse fixed blocks of n bits each; in particular, 32-bit integers arecommonly used (i.e., n = 32). In general, an n-bit quantity may beviewed as naturally representing one of the 2 n integers in the range[0, 2 n-1 ] in its base 2 form. For example, for n = 5, there are 2 5 = 32such numbers. The 5-bit representations of these numbers in base 2form are

0 0 0 0 0 2 = 0 l0 0 0 0 0 1 2 = 1 10

. . .

1 1 1 1 1 2 = 31 10 Note that as listed, the representation does not provide for negativenumbers. One strategy to provide for negative numbers is to mimic the" sign-magnitude " approach normally used in everyday base 10representation of integers. For example, -27310 explicitly exhibitsas separate entries the sign and the magnitude of the number. Asign-magnitude representation strategy could use the first bit torepresent the sign (0 for +, 1 for -). While perhaps satisfactory foreveryday paper and pencil use, this strategy has awkwardcharacteristics that weigh against it. First of all, the operation ofsubtraction is algorithmically vexing even for base 10 paper andpencil exercises. For example, the subtraction problem

23 10 - 34 10

is typically handled not by subtracting 34 10 from 23 10 , but by firstsubtracting 23 10 from 34 10 , exactly the opposite of what the problem isasking for! Even worse, 0 10 is represented twice (e.g., when n = 5, 0 10 is represented by both 0 0 0 0 0 and 1 0 0 0 0). Conceptually, thesubtraction problem above can be viewed as the addition problem 23 10 +(-34 10 ). However, adding the corresponding sign-magnitude


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representations as base 2 quantities will yield an incorrect result inmany cases. Since numeric data is typically manipulatedcomputationally, the representation strategy should facilitate, ratherthan complicate, the circuitry designed to handle the datamanipulation. For these reasons, when n bits are used, the resulting2 n binary combinations are viewed as representing the integers modulo2 n , which inherently provides for negative integers and well-definedarithmetic (modulo 2 n).

The last statement needs some explanation. First observe that inconsidering the number line

| | | | | |. . . -2 31 . . . -2 -1 0 2 . . . 2 31 -1 . . .

truncation of the binary representation for any non-negative integer ito n bits results in i mod 2 n . Note that an infinite number ofnon-negative integers (precisely 2 n apart from each other) truncate toa given particular value in the range [0, 2 n-1]; i.e., there are 2 n

such groupings, corresponding to 0, 1, 2, . . . , 2n

-1. Negativeintegers can be included in each grouping simply by taking integers 2 n apart without regard to sign. These groupings are called the " residueclasses modulo 2 n . Knowing any member of a residue class isequivalent to knowing all of them (just adjust up or down by multiplesof 2 n to find the others, or for non-negative integers truncate thebase 2 representation at n bits to find the value in the range [0,2 n-1]). In other words, the 2 n residue classes represented by 0, 1, 2,..., 2 n-1 provide a (finite) algebraic system that inherits itsalgebraic properties from the (infinite) integers, which justifies theviewpoint that this is a natural way to represent integer data in thecontext of a finite environment. Note that negative integers are

implicitly provided for algebraically, since each algebraic entity(residue class) has an inverse under addition. For example, with n =5, adding the mod 2 5 residue classes for 7 10 and 25 10 yields

[25 10 ] + [7 10 ] = [32 10 ] = [0 10 ] , so [25 10 ] = [-7 10 ]

Returning to the computing practice point of view of identifying theresidue classes with the 5-bit representations of 0, 1, 2, ..., 2 5-1 inbase 2 form, the calculation becomes

1 1 0 0 1 2 + 0 0 1 1 1 2 = 0 0 0 0 0 2 (truncated to 5 bits).

The evident extension of this observation is that n-bit base 2addition conforms exactly to addition modulo 2 n, a fact that lendsitself to circuit implementation.

Again referring to the number line

| | | | | | | | | |. . . -16 . . . -2 -1 0 1 2 . . . 15 16 . . . 31 32

consider for n = 5 the following table exhibiting in base 10 the 32residue classes modulo 2 5. Each residue class is matched to the 5 bit


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representation corresponding to its base value in the range 0, 1, 2,..., 31:

5-bitresidue class representation

{ . . . , -32, 0, 32, . . . } = [0] 0 0 0 0 0{ . . . , -31, 1, 33, . . . } = [1] 0 0 0 0 1

{ . . . , -30, 2, 34, . . . } = [2]

0 0 0 1 0. . .{ . . . , -17, 15, 47, . . . } = [15] 0 1 1 1 1{ . . . , -16, 16, 48, . . . } = [16] = [-16] 1 0 0 0 0

. . .{ . . . , -2, 30, 62, . . . } = [30] = [-2] 1 1 1 1 0{ . . . , -1, 31, 63, . . . } = [31] = [-1] 1 1 1 1 1

Evidently, the 5-bit representations with a leading 0 viewed as base 2integers best represent the integers 0, 1, ..., 15. The 5-bitrepresentations with a leading 1 best represent -16, -15, ..., -2, -1.This representation is called the 5-bit 2's complement representation.

It provides for 0, 15 positive integers, and 16 negative integers.Since data normally originates in sign-magnitude form, an easy means isneeded to convert to/from the sign-magnitude form.

An examination of the table leads to the conclusion that finding themagnitude for a negative value in 5-bit 2's complement form can beaccomplished by subtracting from 32 (1 0 0 0 0 0) and truncating theresult. In general, this follows from the mod 2 5 residue classequivalences,

-[i] = [-i] + [0 10 ] = [-i] + [32 10 ] = [-i + 32 10 ] = [32 10 -i]

which demonstrates that subtracting from 32 and truncating the resultwill always result in the representation for -i. -i is called the 2'scomplement of i. One way to subtract from 32 is to subtract from1 1 1 1 1 (which is 31) and then add 1 (all in base 2). This isequivalent to inverting each bit and then adding 1 (in base 2) to theoverall result. There is nothing special in this discussion thatrequires 5 bits; i.e., the same rationale is equally applicable to ann-bit environment. Hence, in general, to find the 2's complement ofan integer represented in n-bit 2's complement form, invert its bitsand add 1 (in base 2).

Example 1: Determine the 8-bit 2's complement representation of -37 10 .

First, the magnitude of -37 10 is given by37 10 = 1 0 0 1 0 1 2

which is 0 0 1 0 0 1 0 1 in 8-bit 2's complement form.

The representation for -37 10 is then given by the 2's complement of37 10 , obtained by inverting the bits of the 8-bit representation ofthe magnitude and adding 1; i.e.,


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1 1 0 1 1 0 1 0+0 0 0 0 0 0 0 1

-37 10 = 1 1 0 1 1 0 1 1 in 8-bit 2's complement form.

Example 2: Determine the (base 10) value of the 9 bit 2's complementintegers

i = 0 0 0 0 1 1 0 1 1j = 1 1 1 0 1 1 0 1 0s = i + j

For i, since the lead bit is 0, the sign is + and the magnitude ofthe number is directly given by its representation as a base 2integer; i.e.,

i = 27 10 .

For j, since the lead bit is 1, the number is negative, so itsmagnitude is given by -j. Inverting j's bits and adding 1 gives

0 0 0 1 0 0 1 0 1+0 0 0 0 0 0 0 0 1

0 0 0 1 0 0 1 1 0 = 38 10 = -j (j's magnitude);

i.e., j = -38 10 .

i+j (which we now know is -11 10 ) can be computed directly usingordinary base 2 addition modulo 2 9; i.e.,

i: 0 0 0 0 1 1 0 1 1 = 27 10 j: + 1 1 1 0 1 1 0 1 0 = -38 10

i+j: 1 1 1 1 1 0 1 0 1 = -11 10

Example 2 illustrates that only circuitry for base 2 addition needs to

be developed to perform addition and subtraction on integersrepresented in n-bit 2's complement form.

Historically, a variation closed related to n-bit 2's complement,namely, n-bit 1's complement has also been used for integerrepresentation in computing devices. The 1's complement of an n-bitblock of 0's and 1's is obtained by inverting each bit. For thisrepresentation, arithmetic still requires only addition, but wheneverthere is a carry out of the sign position (and no overflow hasoccurred), 1 must be added to the result (a so-called " end-aroundcarry ", something easily achieved at the hardware level). Forexample, in 8-bit 1's complement

38 10 = 0 0 1 0 0 1 1 0-27 10 = 1 1 1 0 0 1 0 0

11 10 = 0 0 0 0 1 0 1 01 (end-around carry of carry-out)

0 0 0 0 1 0 1 1Note that the end-around carry is only used when working in 1'scomplement.

Integers do not have to be represented in n-bit blocks. Anotherrepresentation format is Binary Coded Decimal (BCD), where each


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decimal digit of the base 10 representation of the number isseparately represented using its 4-bit binary (base 2) form.

The 4-bit forms are

0 = 0 0 0 01 = 0 0 0 12 = 0 0 1 0

. . .9 = 1 0 0 1

so in BCD,27 is represented in 8 bits by 0 0 1 0 0 1 1 1

| | |2 7

183 is represented in 12 bits by 0 0 0 1 1 0 0 0 0 0 1 1| | | |

1 8 3

BCD is obviously a base 10 representation strategy. It has theadvantage of being close to a character representation form (discussedbelow). When used in actual implementation, it is employed insign-magnitude form (the best known of which is IBM's packed decimalform, which maintains the sign in conjunction with the last digit toaccommodate the fact that the number of bits varies from number tonumber). Since there is no clear choice as to how to represent thesign, we will not address the sign-magnitude form further in thecontext of discussing BCD. It is possible to build BCD arithmeticcircuitry, but it is more complex than that used for 2's complement.The arithmetic difficulties associated with BCD can easily be seen by

considering what happens when two decimal digits are added whose sumexceeds 9.

For example, adding 9 and 4 using ordinary base 2 yields

1 0 0 1 = 90 1 0 0 = 41 1 0 1 = 13

which differs from 0 0 0 1 0 0 1 1 , which is 13 in BCD.| | |

1 3

Achieving the correct BCD result from the base 2 result requiresadding a correction (+6 10 = 0 1 1 0 2); e.g.,

1 1 0 1+ 0 1 1 0

0 0 0 1 0 0 1 1 = 13 in BCD.| | |

In general, a correction of 6 is required whenever the sum of the twodigits exceeds 9. Hence, the circuitry has to allow for the fact that


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sometimes a correction factor is required and sometimes not. Since aBCD representation is normally handled using sign-magnitude,subtraction is an added problem to cope with.

Real numbers:

Real numbers are normally represented in a format deriving from theidea of the decimal expansion, which is used in paper and pencilcalculations to provide rational approximations to real numbers (thisis termed a " floating point representation , since the base pointseparating the integer part from the fractional part may shift asoperations are performed on the number). There is a defined standardfor representing real numbers, the IEEE 754 Floating Point Standard,whose discussion will be deferred until later due to its complexity.

An alternate representation for real numbers is to fix the number ofallowed places after the base point (a so-called " fixed pointrepresentation ) and use integer arithmetic. Since the number ofplaces is fixed, the base point does not need to be explicitly

represented (i.e., it is an " implied base point "). The result ofapplying arithmetic operations such as multiplication and divisiontypically requires the use of additional (hidden) positions after thebase point to accurately represent the result since a fixed pointformat truncates any additional positions resulting frommultiplication or division. For this reason precision is quicklylost, further limiting the practicality of using this format.

Character representation:

Character data is defined by a finite set, its alphabet, whichprovides the character domain. The characters of the alphabet are

represented as binary combinations of 0's and 1's. If 7 (ordered) bitsare used, then the 7 bits provide 128 different combinations of 0'sand 1's. Thus 7 bits provide encodings for an alphabet of up to 128characters. If 8 bits are employed, then the alphabet may have asmany as 256 characters. There are two defined standards in use in thiscountry for representing character data:

ASCII (American Standard Code for Information Interchange)EBCDIC (Extended Binary Coded Decimal Interchange Code).

ASCII has a 7-bit base definition, and an 8-bit extended versionproviding additional graphics characters. (table page 21)

In each case the standard prescribes an alphabet and itsrepresentation. Both standards have representation formats that makeconversion from character form to BCD easy (for each characterrepresenting a decimal digit, the last 4 bits are its BCDrepresentation). The representation is chosen so that when viewed innumeric ascending order, the corresponding characters follow thedesired ordering for the defining alphabet, which means a numeric sortprocedure can also be used for character sorting needs. Sincecharacter strings typically encompass many bits, character data isusually represented using hex digits rather than binary.


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For example, the text string "CDA 3101" is represented by

C 3 C 4 C 1 4 0 F 3 F 1 F 0 F 1 in EBCDIC| | | | | | | | |

C D A spc 3 1 0 1| | | | | | | | |

and 4 3 4 4 4 1 2 0 3 3 3 1 3 0 3 1 in ASCII (or ASCII-8).

Since characters are the most easily understood measure for datacapacity, an 8-bit quantity is termed a byte of storage and datastorage capacities are given in bytes rather than bits or some othermeasure. 2 10 = 1024 bytes is called a K-byte , 2 20 = 1,048,576 bytes iscalled a megabyte , 2 30 bytes is called a gigabyte , 2 20 bytes is called aterabyte , and so forth.

Other representation schemes:

BCD is an example of a weighted representation scheme that utilizesthe natural weighting of the binary representation of a number; i.e.,

w3 d 3 + w 2 d 2 + w 1 d 1 + w 0 d 0 where the digits d i are just 0 or 1 and the weights are w 3=8, w 2=4,w1=2, w 0=1. Since only 10 of the possible 16 combinations are used, w 3 is 0 for all but 2 cases (8 and 9). A variation uses w 3=2 to form whatis known as " 2421 BCD " . w 3=0 for 0,1,2,3,4 and w 3=1 for 5,6,7,8,9. Amajor advantage over regular BCD is that the code is " self-complementing " in the sense that flipping the bits produced the 9'scomplement.

Example : subtraction by using additiona subtraction such as 654 - 470 is awkward because of the need toborrow. The computation can be done by using addition if you think

in terms of654+(999-470)-999 = 654+529-999 = 1183-999 = 183+1 = 184.999-470 = 529 is called the " 9's complement " of 470, so thealgorithm to do a subtraction A-B is

1. form the 9's complement (529) of the subtrahend B (470)2. add it to the minuend A (654)3. discard the carry and add 1 (corresponding to the end-around

carry of 1's complement)Note that no subtraction circuitry is needed, but the technique doesneed an easy way to get the 9's complement.

With 2421 BCD, 470 = 0100 1101 0000 and the 9's complement of 470 is529 = 1011 0010 1111

Addition is still complicated as can be seen by adding 6+5 which is1100 + 1011 = 0001 carry 1 (i.e., ordinary binary addition fails).

A final BCD code, " excess-3 BCD ", is also self-complementing. It issimply ordinary BCD + 3, so for the above example,with excess-3, 470 = 0111 1010 0011 and the 9's complement of 470 is

529 = 1000 0101 1100.


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The lesson to learn is that codes must be formulated to represent datain a computer, and different representations are employed fordifferent purposes; e.g.,

2's complement is a number representation that facilitatesarithmetic in base 2

BCD is another number representation that facilitates translationof numbers to decimal character form but complicates arithmetic

ASCII represents characters in a manner that facilitates upper-case/lower-case adjustment and ease of conversion of decimalcharacters

Other schemes such as "2421 BCD" and "excess-3 BCD" seek toimprove decimal arithmetic by facilitating use of 9's complementto avoid subtraction

Sometimes representation schemes are designed to facilitate othertasks, such as representing graphical data elements or for tracking.For example, Gray Code is commonly used for identifying sectors on arotating disk. Gray code is defined recursively by using the rule:

to form the n+1 bit representation from the n-bit representation preface the n-bit representation by 0 append to this the n-bit representation in reverse order

prefaced by 1

Hence, the 1, 2, and 3-bit representations are

0 0 0 0 00 1 0 1 0 01

1 1 0 11 1 0 0 10

1 10 1 11

1 01 1 00

Consider three concentric disks shaded as follows:

0

0

0

0

0

00

0

0

0

0

0

1

1

1

1

1

1

1

1

1

11

1


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The shading provides a gray code identification for 8 distinct wedge-shaped sections on the disk.

As the disk rotates from one section to the next, no more than onedigit position (represented by shaded and unshaded segments) changes,simplifying the task of determining the id of the next section whengoing from one section to the next. Note that this is acharacteristic of the gray code.

In contrast, note that in regular binary for the transition from 3 to4, 011 to 100, all 3 digits change, which means hardware tracking thechange if this representation was used would potentially facearbitrary intermediate patterns in the transition from section 3 tosection 4, complicating the process of to determining that 4 is the idof the next section (e.g., something such as a delay would have to beadded to the control circuitry to allow the transition to stabilize).

For a disk such as above, a row of 3 reflectance sensors, one for each

concentric band, can be used to track the transitions.

Boolean algebra :

Boolean algebra is the algebra of circuits, the algebra of sets, andthe algebra of truth table logic. A Boolean algebra has twofundamental elements, a " zero " and a " one ," whose properties aredescribed below.

For circuits"zero" is designated by 0 or L (for low voltage) and "one" by 1 or H(for high voltage).

For sets,"zero" is the empty set and "one" is the set universe.For truth table logic,

"zero" is designated by F (for false) and "one" by T (for true).

Just as the algebraic properties of numbers are described in terms offundamental operations (addition and multiplication), the algebraicproperties of a Boolean algebra are described in terms of basicBoolean operations.

For circuits, the basic Boolean operations are ones weve alreadydiscussed

AND ( ), OR (+), and complement (_ _ )

For sets the corresponding operations areintersection ( ), union ( ), and set complement.

For truth table logic they areAND ( ), OR ( ), and NOT (~).

Recall that AND and OR are binary operations (an operation requiringtwo arguments), while complement is a unary operation (an operationrequiring one argument).


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For circuits, also recall that the multiplication symbol is used for AND the addition symbol + is use for OR the symbol for complement is an overbar; i.e.,

_X_ designates the

complement of X.

The utilization of for AND and + for OR is due to the fact that theseBoolean operations have algebraic properties similar to (but

definitely not the same as) those of multiplication and addition forordinary numbers. Basic properties for Boolean algebras (using thecircuit operation symbols, rather than those for sets or for symboliclogic) are as follows:

1. Commutative property : + and are commutative operations; e.g.,

X + Y = Y + X and X Y = Y X

In contrast to operations such as subtraction and division, acommutative operation has a left-right symmetry, permitting us toignore the order of the operation's operands.

2. Associative property : + and are associative operations; e.g.,

X + (Y + Z) = (X + Y) + Z and X (Y Z) = (X Y) Z

Non-associative operations (such as subtraction and division)tend to cause difficulty precisely because they are non-associative. The property of associativity permits selectiveomission of parentheses, since the order in which the operationis applied has no effect on the outcome; i.e., we can just aseasily write X + Y + Z as X + (Y + Z) or (X + Y) + Z since the

result is the same whether we first evaluate X + Y or Y + Z.

3. Distributive property : distributes over + and + distributesover ; e.g.,

X (Y + Z) = (X Y) + (X Z) and alsoX + (Y Z) = (X + Y) (X + Z)

With the distributive property we see a strong departure from thealgebra of ordinary numbers which definitely does not have theproperty of + distributing over .

The distributive property illustrates a strong element ofsymmetry that occurs in Boolean algebras, a characteristic knownas duality .

4. Zero and one : there is an element zero (0) and an element one(1) such that for every X,

X + 1 = 1 and X 0 = 0


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5. Identity : 0 is an identity for + and 1 is an identity for ;e.g.,

X + 0 = X and X 1 = X for every X

6. Complement property : every element X has a complement_X_ such

that

X +_X_ = 1 and X

_X_ = 0

The complement of 1 is 0 and vice-versa; it can be shown that ingeneral complements are unique; i.e., each element has exactlyone complement.

7. Involution property (rule of double complements): for each X,=X= = X

8. Idempotent property : for every element X,

X + X = X and X X = X

9. Absorption property : for every X and Y,

X + (X Y) = X and X + (_X_ Y) = X + Y

Anything "AND"ed with X is absorbed into X under "OR" with X.

Anything "AND"ed with_X_ is absorbed in its entirety under "OR"

with X.

10. DeMorgan property : for every X and Y,_X____

____

Y_ =

_X_ +

_Y_ and

_X____

+____

Y_ =

_X_

_Y_

The DeMorgan property describes the relationship between "AND"and "OR", which with the rule of double complements, allowsexpressions to be converted from use of "AND"s to use of "OR"sand vice-versa; e.g.,

X + Y ==X====

+====

Y= =

_X_

_Y_

X Y ==X========Y

= =

_X_ +

_Y_

Some of these properties can be proven from others (i.e., they do notconstitute a minimal defining set of properties for Boolean algebras);for example, the idempotent rule

X + X = X can be obtained by the manipulationX + X = X + (X 1) = X by the absorption property.

The DeMorgan property provides rules for using NANDs and NORs (whereNAND stands for "NOT AND" and NOR stands for "NOT OR"). The operationNAND (sometimes called the Sheffer stroke) is denoted by


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_X____

____

Y_ = X Y

and the operation NOR (sometimes called the Pierce arrow) is denotedby

_X____

+____

Y_ = X Y

Utilizing the rule of double complements and the DeMorgan property,any expression can be written in terms of the complement operation and or the complement operation and . Moreover, since the complementcan be written in terms of either or ; i.e.,

_X_ = X X = X X

any Boolean expression can be written solely in terms of either orsolely in terms of . This observation is particularly significantfor a circuit whose function is represented by a Boolean expression,since this property of Boolean algebra implies that the circuit

construction can be accomplished using as basic circuit elements onlyNAND circuits or only NOR circuits.

Note that properties such as commutative and associative are also acharacteristic of the algebra of numbers, but others, such as theidempotent and DeMorgan properties are not; i.e., Boolean algebra, thealgebra of circuits, has behaviors quite different from what we areused to with numbers. Just as successfully working with numbersrequires gaining understanding of their algebraic properties, workingwith circuits requires gaining understanding of Boolean algebra.

In working with numbers, just as we often omit writing the times

symbol

in formulas, we may omit the AND symbol in formulas.

Examples:

1. There is no cancellation; i.e., XY = XZ does not imply that Y = Z(if it did, the idempotent property XX = X = X 1 would implythat X = 1!)

2. Complements are uniqueTo see this just assume that Y is also a complement for X; i.e.,

X + Y = 1 and XY = 0. AND the 1 st equation through with

_X_ to get X

_X_ + Y

_X_ =

_X_

Since X _X_ = 0, this reduces to Y

_X_ =

_X_

Similarly, since X +_X_ = 1 and XY = 0, XY +

_X_ Y = Y reduces

to_X_ Y = Y

Putting the last two lines together we have_X_ = Y

3. The list of properties is not minimal; e.g., Given that the properties other than the idempotent

property are true, then it can be shown that the idempotentproperty is also true as follows:

X +_X_ = 1, so using the distributive property,

XX + X_X_ = X which in turn leads to


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XX = X since X_X_ = 0

A similar argument can be used to show that X + X = X Given that the properties other than the absorption

property are true, then it can be shown that the absorptionproperty is also true as follows:

Since 1 + Y = 1, X + XY = X, the 1st absorption criteria

Starting from X +

_

X

_

= 1 we get XY +

_

X

_

Y = YAdding X to both sides we get X + XY + _X_ Y = X + YBy the first absorption criteria this reduces to

X +_X_ Y = X + Y, which is the 2 nd absorption criteria

The DeMorgan property has great impact on circuit equations, since itprovides the formula for converting from OR to NAND and from AND toNOR.

The above proofs are by logical deduction. For a 2-element Booleanalgebra, proof can be done exhaustively be examining all cases; e.g.,we can verify DeMorgan by means of a " truth table ":

X | Y _X_ | _Y_ | _X_ _Y_ | X + Y | _X____ +____ Y_ | | | | |

0 | 0 1 | 1 | 1 | 0 | 1 | | | | |

0 | 1 1 | 0 | 0 | 1 | 0 | | | | |

1 | 0 0 | 1 | 0 | 1 | 0 | | | | |

1 | 1 0 | 0 | 0 | 1 | 0 | | | | |

This is called a "brute force" method for verifying the equation_X____

+____

Y_ =

_X_

_Y_ because it exhaustively checks every case using

the definition of the AND, OR and NOT operations.Since AND and OR are associative, we can write_X____

____

Y____

____

Z_ and

_X____

+____

Y____

+____

Z_ unparenthesized.

It can be shown that_X____

____

Y____

____

Z_ =

_X_ +

_Y_ +

_Z_

and_X____

+____

Y____

+____

Z_ =

_X_

_Y_

_Z_

This leads to the " generalized DeMorgan property " :

_X__

1

__X__

2

___.___

.___

.___

X__

n

_ =

_X__

1

+

_X__

2 + . . . +_X__

n

_X__

1

__+____

X__

2

__+__.___

.___

.__+____

X__

n

_ =

_X__

1

_X__

2 . . ._X__

n

which is often useful for circuits of more than 2 variables.There are multi-input NAND gates to take advantage of this property.

WARNING : NAND and NOR are not associative .


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Canonical forms:

Any combinational circuit, regardless of the gates used, can beexpressed in terms of combinations of AND, OR, and NOT. The mostgeneral form of this expression is called a canonical form. There aretwo types:

the canonical sum of products the canonical product of sums

Formulating these turns out to be quite easy if the truth table forthe circuit is constructed. For example, consider a circuit f(X,Y,Z)with specification:

X | Y | Z f(X,Y,Z) ||_X_

_Y_

_Z_

| X_Y_ Z | X Y

_Z_

| | || | |0 | 0 | 0 1 || 1 | 0 | 0

| | || | |0 | 0 | 1 0 || 0 | 0 | 0

| | || | |0 | 1 | 0 0 || 0 | 0 | 0

| | || | |0 | 1 | 1 0 || 0 | 0 | 0| | || | |1 | 0 | 0 0 || 0 | 0 | 0

| | || | |1 | 0 | 1 1 || 0 | 1 | 0

| | || | |1 | 1 | 0 1 || 0 | 0 | 1

| | || | |1 | 1 | 1 0 || 0 | 0 | 0

| | || | |

Note thatf(X,Y,Z) =

_X_

_Y_

__Z_

+ X_Y_ Z + X Y

_Z_

Each of these terms is obtained just by looking at the combinationsfor which f(X,Y,Z) is 1. Each of these is call a minterm . There are

8 possible minterms for 3 variables (see below).

Analogously, for the combinations for which f(X,Y,Z) is 0 we getf(X,Y,Z) = (X+Y+

_Z_

)(X+_Y_ +Z)(X+

_Y_ +

_Z_ )(

_X_ +Y+Z)(

_X_ +

_Y_ +

_Z_ )

Each of these terms is obtained just by looking at the combinationsfor which f(X,Y,Z) is 0. Each of these is call a maxterm . There are8 possible maxterms for 3 variables (see below). The minterms andmaxterms are numbered from 0 corresponding to the binary combinationthey represent.

X Y Z minterms maxterms

0. 0 0 0_X_

_Y_

_Z_ X+Y+Z

1. 0 0 1 _X_ _Y_ Z X+Y+ _Z_

2. 0 1 0_X_ Y

_Z_

_X_ +Y+

_Z_

3. 0 1 1_X_ YZ X+

_Y_ +

_Z_

4. 1 0 0 X_Y_

_Z_

_X_ +Y+Z

5. 1 0 1 X_Y_ Z

_X_ +Y+

_Z_

6. 1 1 0 XY_Z_

_X_ +

_Y_ +Z

7. 1 1 1 XYZ_X_ +

_Y_ +

_Z_


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Note that the maxterms are just the complements of theircorresponding minterms.

Representing a function by using its minterms is called the canonicalsum of products and by using its maxterms the canonical product ofsums ; i.e.,

f(X,Y,Z) =_X_

_Y_

__Z_

+ X_Y_ Z + X Y

_Z_ is the canonical sum of products

andf(X,Y,Z) = (X+Y+

_Z_

)(X+_Y_ +Z)(X+

_Y_ +

_Z_ )(

_X_ +Y+Z)(

_X_ +

_Y_ +

_Z_ ) is the canonical

product of sums for the function f(X,Y,Z).

The short-hand notation ( -notation )f(X,Y,Z) = (0,5,6) is used for the canonical sum of products.

Similarly the short-hand notation ( -notation )f(X,Y,Z) = (1,2,3,4,7) is used for the canonical product of sums.

Canonical representations are considered to be 2-level

representations, since for most circuits a signal and its opposite areboth available as inputs.

A combinational circuit's behavior is specified by one of truth table listing the outputs for every possible combination of

input values canonical representation of the outputs using or notation circuit diagram using logic gates

Converting to NANDS or NORS:

For a Boolean algebra, notice that the complement

_X_ is given by (X X)

Since XY is given by the complement of (X Y) we haveXY = (X Y) (X Y)

By DeMorgan X + Y = =X====+====Y= =_X_

_Y_ = (X X)(Y Y)

Hence, we can describe and equation using AND, OR, and complementsolely in terms of NANDS using the above conversions.

Similarly, for NOR we have the conversions-

_X_ = (X X)

X+Y = (X Y) (X Y) XY = =X==Y= = _X_ + _Y_ = (X X)(Y Y) (By DeMorgan)

By DeMorgan,a NAND gate is equivalent to (

_X____

____

Y_ =

_X_ +

_Y_ )

and a NOR gate is equivalent to (_X____

+____

Y_ =

_X_

_Y_ )


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Using these equivalences, an OR-AND (product of sums) combination canbe converted to NOR-NOR as follows:

Other equivalences to OR-AND that follow from this one are NAND-ANDand AND-OR as follows:

For the sum of products (AND-OR) we have the counterpart equivalences:

OR-AND NOR-NOR

NAND-AND

NAND-AND

AND-OR NAND-NAND

NOR-OR

OR-NAND


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.f(A,B,C,D)= (( A

_B_ ) C) ((A C)

_D_ ) .

(A_B_ ) C

(AC) _D_

At this point, if given a truth table, or a representation using or notation, we can generate a 2-level circuit diagram as the canonicalsum of products or product of sums. Similarly, given a circuitdiagram, we can produce its truth table. This process is calledcircuit analysis . For example, recall that the circuit equation,

f(A,B,C,D) = ((A_B_ ) C) ((A C)

_D_

)

was earlier represented as a 3-level circuit diagrammed by:

A

B

C

D

From the circuit equation we can obtain the truth table as follows,conforming to the value given earlier

A B C D f(A,B,C,D) A_B_ (A

_B_ ) C AC (A C)

_D_ ((A

_B_ ) C ) ((A C)

_D_ )

0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 0 1 0 1 1 0 1 1 0 0 0 1 1 0 0 0 1 1 1 0 0 1 1 0 0 1 0 0 0 0 1 1 1 0 01 0 0 1 0 1 1 1 0 01 0 1 0 1 1 0 0 0 11 0 1 1 0 1 0 0 1 01 1 0 0 0 0 1 1 0 01 1 0 1 0 0 1 1 0 01 1 1 0 0 0 1 0 0 01 1 1 1 1 0 1 0 1 1

From the truth table f(A,B,C,D) = (1,5,10,15)= (0,2,3,4,6,7,8,9,11,12,13,14)

Note that the canonical representations are not as compact as theoriginal circuit equation.

Circuit simplification:

A circuit represented in a canonical form (usually by or notation)can usually be simplified. There are 3 techniques commonly employed:

algebraic reduction Karnaugh maps ( K-maps ) Quine-McCluskey method

AC

A_B_


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Algebraic reduction is limited by the extent to which one is able toobserve potential combinations in examining the equation; e.g.,_

A_ B

_C_ D +

_A_ BCD + AB

_C_ D =

_A_ B

_C_ D +

_A_ BCD +

_A_ B

_C_ D + AB

_C_ D (idempotent)

=_A_ BD(

_C_ + C) + (

_A_ + A)B

_C_ D (distributive)

=_A_ BD 1 + B

_C_ D 1 (complement)

=_A_ BD + B

_C_ D (identity)

This is a minimal 2-level representation for the circuit. The furtheralgebraic reduction to (

_A_ +

_C_ )BD produces a 2-level circuit dependent

only on 2-input gates.

The Quine-McCluskey method is an extraction from the K-map approachabstracted for computer implementation. It is not dependent on visualgraphs and is effective no matter the number of inputs. Since it doesnot lend itself to hand implementation for more than a few variables,it will only be discussed later and in sketchy detail.

For circuits with no more than 4 or 5 input variables, K-maps providea visual reduction technique for effectively reducing a combinationalcircuit to a minimal form.

The idea for K-maps is to arrange minterms whose value is 1 (ormaxterms whose value is 0) on a grid so as to locate patterns whichwill combine.

For a 1-variable map, input variable X, the minterm locations are asfollows:

While a 1-variable map is not useful, it is worth including to roundout the discussion of maps using more variables.

For a 2-variable map, input variables X, Y has minterm locations

In general we only label the cells according to the binary number theycorrespond to in the truth table (the number used by the or notations). The map structure is then:

_X_

X

X 0 1

_X_

_Y_ X

_Y_

_X_ Y X Y

0 1

0

1

XY

0 1

2 3

0 1

0

1

XY


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For example, if we have f(X,Y) = (1,3), we mark the minterms for 1and 3 in the 2-variable map as follows:

Now we can graphically see that a reduction is possible by delineatingthe adjacent pair of minterms (corresponding to

_X_ Y + XY), which in

fact reduces to Y. Notice that there are visual clues: the 1 over thecolumn corresponds to Y and the looking down vertically, the 0 and 1"cancel".

2-variable K-maps also are not particularly useful, but again areillustrative.

With 3-variables, the pattern is

The key thing to note is that the order across the top follows theGray code pattern so that there is exactly one 0-1 matchup betweeneach column, including a match between the 1 st and 4 th columns.

For the function f(X,Y,Z) = (1,3,4,6), the K-map is

f(X,Y,Z) =_X_ Z + X

_Z_

The 1st term of the reduced form for f(X,Y,Z) is in the

_X_ row (flagged

by 0) and the 2 nd is in the X row (flagged by 1). In each case the Yterm cancels since it is the one with 0 matched to 1. Pay particularattention to the box that wraps around.

0 11

2 31

0 1

0

1

XY

0 1

4 5

00 01 11 10

0

1

XYZ

3

2

7

6

0 1

1

4

15

00 01 11 10

0

1

XYZ

3

12

7

6

1


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For a more complex example, consider f(X,Y,Z) = (1,3,4,5)

Here f(X,Y,Z) can be reduced to either of the following f(X,Y,Z) =

_X_ Z + X

_Y_

f(X,Y,Z) =_X_ Z + X

_Y_

+_Y_ Z

Not that the term_Y_ Z is "redundant" since its 1's are covered by the

other two terms. The first expression is called a minimal sum ofproducts expression for f(X,Y,Z) since it cannot be reduced further.For combinational circuits, the redundant term can be omitted, butsometimes in the context of sequential circuits, where intermediatevalues matter, it must be left in.

With 4-variables, the K-map pattern is

Now the Gray code pattern of the rows must also be present for thecolumns. More complex situations can also arise; for example,

0 1

1

4

15

1

00 01 11 10

0

1

XYZ

3

12

7

6

0

11

4 5

00 01 11 10

00

01

11

10

ABCD

3

2

1

7

16

1

12 13

1

8

19

1

15

114

11

10

0 1

4 5

00 01 11 10

00

01

11

10

ABCD

3

2

7

6

12 13

8 9

15

14

11

10


31/161

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describes f(A,B,C,D) = (0,2,6,7,8,9,13,15). There are two patternspresent that produce a minimal number of terms:

Hence, either of the following produces a minimal sum of producesexpression:

from the rows f(A,B,C,D) =_A_

_B_

_D_ +

_A_ B C + ABD + A

_B_

_C_

from the columns f(A,B,C,D) =_B_

_C_

_D_ + A

_C_ D + BCD +

_A_ C

_D_

In either case we know we have the function since all 1's are covered.

When working with maxterms, the 0's of the function are what isconsidered. For the function above,

f(A,B,C,D) = (1,3,4,5,10,11,12,14)and the K-map is

leading to the following two minimal product of sums expressions: f(A,B,C,D) = (A+B+

_D_ )(A+

_B_ +C)(A

_ _ +

_B_+D)( A

_ _ +B+

_C_ ) from the rows

f(A,B,C,D) = (_B_ +C+D)(A+C+

_D_ )(B+

_C_ +

_D_ )(

_A_ +

_C_ +D) from the columns.

Be sure to observe that when working with maxterms, "barred" itemscorrespond to 1's and unbarred items correspond to 0's, exactly theopposite of what is done when working with minterms .

Just as a 4-variable K-map is formed by combining two 3-variable maps,a 5-variable K-map can be formed by combining two 4-variable maps

0

11

4 5

00 01 11 10

00

01

11

10

ABCD

3 2

1

7

16

1

12 13

1

8

19

1

15

114

11 10

0

11

4

5

00 01 11 10

00

01

11

10

ABCD

3 2

1

7

16

1

12

13

1

8

19

1

15

114

11 10

0

1

04

05

0

00 01 11 10

00

01

11

10

ABCD

3

0

2

7

6

12

013

8

9

15

14

0

11

010

0


32/161

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(conceptually, 1 on top of the other, representing 0 and 1 for the 5 th variable).

In general, blocks of size 2 n are the ones that can be reduced. Hereare blocks of size 4 on a 4-variable K-map:

f(A,B,C,D) = AB f(A,B,C,D) = AD

f(A,B,C,D) =_B_

_D_ f(A,B,C,D) =

_B_ D

In each case, the horizontal term with 0 against 1 is omitted and thevertical term with 0 against 1 is omitted. Be sure to pay particularattention to the pattern with a 1 in each corner, where A is omittedvertically and C is omitted horizontally.

Note that each block of 4 contains 4 blocks of 2, but these are notdiagrammed since they are absorbed (in contrast, the Quine-McCloskeymethod, which we wont look at until later, does keep tabs on all suchblocks!).

In general, an implicant ( implicate for 0's) is a term that is aproduct of inputs (including complements) for which the functionevaluates to 1 whenever the term evaluates to 1. These arerepresented by blocks of size 2n on K-maps.

0 1

4 5

00 01 11 10

00

01

11

10

ABCD

3

2

7

6

12

113

1

8 9

15

114

1

11

10

0

1

4

5

00 01 11 10

00

01

11

10

ABCD

3 2

7 6

12

13

1

8

9

1

15

114

11

110

0

11

4 5

00 01 11 10

00

01

11

10

ABCD

3

2

1

7

6

12 13

8

19

15

14

11

10

1

0

1

1

4

5

00 01 11 10

00

01

11

10

ABCD

3

12

7 6

12

13

8

9

1

15 14

11

110


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A prime implicant (implicate for 0's) is one not contained in anylarger blocks of 1's.

An essential prime implicant is a prime implicant containing a 1 notcovered by any other prime implicant.

A distinguished cell is a 1-cell covered by exactly 1 prime implicant.

A don't care cell is one that may be either 0 or 1 for a particularcircuit. The value used in K-map analysis is one which increases theamount of reduction. Don't care conditions occur because in circuits,there are often combinations of inputs that cannot occur, so we don'tcare whether their values are 0 or 1.

General Procedure for Circuit Reduction Using K-maps

1. Map the circuit's function into a K-map, marking don't cares byusing dashes

2. Treating don't cares as if they were 1's (0's for implicates),

box in all prime implicants (implicates), omitting any consistingsolely of dashes.3. Mark any distinguished cells with * (dashes don't count)4. Include all essential prime implicants in the sum, change their

1's to dashes and remove their boxes - exit if there aren't anymore 1's at this point.

5. Remove any prime implicants whose 1's are contained in a boxhaving more 1's (dominated case)

if there is a case where the number of 1's is the same (co-dominant case), discard the smaller box

if there is a case where the number of 1's is the same and thebox sizes are the same, discard either.

6. Go back to step 3 if there are any new distinguished cells7. Include the largest of the remaining prime implicants in the sumand go back to step 4 (this step is rarely needed) - if there isno largest, choose any

8. If step 7 was used, choose from among the possible sums the onewith the fewest terms, then the one using the fewest variables.

Remark: if this procedure is employed with the K-map

step 7 will be employed.

0

11

4

5

00 01 11 10

00

01

11

10

ABCD

3

2

1

7

16

1

12

13

1

8

19

1

15

114

11

10


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Worked out example:

There are 2 essential prime implicants to put in the sum: A_D_ +

_A_ D

Now change the 1's in these 2 boxes to don't cares and redraw the

map:

The map has 2-sets of co-dominant implicants, so pick one of the co-dominant boxes from each and delete it; mark distinguished cells.

Adding in the new essential prime implicants covers all 1's so

f(A,B,C,D) = A_D_ +

_A_ D +

_B_

_D_ + A C

0

11

1

4

5

1

00 01 11 10

00

01

11

10

ABCD

3

12

1

7

1

6

12

113

8

19

15

114

1

11

110

1

*

*

0

11

-

4

5

-

00 01 11 10

00

01

11

10

ABCD

3

-2

1

7

-6

12

-13

8

-9

15

114

-

11

110

-

0

11

-

4

5

-

00 01 11 10

00

01

11

10

ABCD

3

-2

1

7

-6

12- 13

8

-9

15114

-

11

110

-

*

*

*

*


35/161

Page 33

We earlier considered the circuit analysis process , where given acircuit diagram, it can be converted into a circuit equation based onthe gates employed, and from there converted into a truth table. Thecircuit design process proceeds as follows:

1. Formalize the problem statement into inputs and outputs, devisingrepresentations for inputs and outputs

2. Translate the problem statement to a logic function3. Determine the outputs corresponding to inputs (some of which may

be dont cares)4. Convert to or notation (truth table optional), including any

dont cares Example: if f(A,B,C) = 1 for 0,3,4 and 1,5 are dont cares,

then the circuit is given by either off(A,B,C) = (0,3,4) + d(1,5) orf(A,B,C) = (2,6,7) + d(1,5)

5. Create a K-map from the or notation6. Use K-map reduction to obtain a minimal circuit equation

7.

Produce a circuit diagram from the circuit equationEmploying XOR gates requires manipulation of the circuit equation.Employing NAND and NOR gates can be accomplished by adjusting thecircuit diagram. [Recall that using the equivalences

a NAND gate is equivalent to

and a NOR gate is equivalent to

there are diagrammatic techniques for converting sum of products andproduct of sums expressions to ones using NAND and NOR].

Example: (circuit design) Design a matching circuit for the following:There are 3 types of ball bearings in a bin (plastic, steel, andbrass). An assembly machine needs ball bearings of each type atdifferent points in the assembly process. Given the type of ballbearing it needs at present, it needs to look through the bin for aball bearing matching the type; ie.,

Needed type

Observed typeAccept/Reject


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Step 1: FormalizeType Representation

Plastic 01 Accept = 1Steel 10 Reject = 0Brass 11

Steps 2,3,4: Translate to logic functionNeeded obsrvd

A B C D f(A,B,C,D) = (5,10,15) + d(0,1,2,3,4,8,12)

0 0 0 0 d = (6,7,9,11,13,14) + d(0,1,2,3,4,8,12)0 0 0 1 d0 0 1 0 d0 0 1 1 d0 1 0 0 d0 1 0 1 10 1 1 0 00 1 1 1 0

1 0 0 0 d1 0 0 1 01 0 1 0 11 0 1 1 01 1 0 0 d1 1 0 1 01 1 1 0 01 1 1 1 1

Steps 5: K-map reduction

Step 6: Circuit equation f(A,B,C,D) =_A_

_C_ + ABCD +

_B_

_D_

or f(A,B,C,D) = (_A_ +C)(B+

_D_ )(A+

_C_ )(

_B_ +D)

Step 7: Circuit diagram (there are 2 obvious NORs)

f(A,B,C,D) =_A____

+____

C_ + ABCD +

_B____

+____

D_

0

-1

-

4

-5

1

00 01 11 10

00

01

11

10

ABCD

3

-2

-

7

6

12

-13

8

-9

15

114

11

10

1

*

*

*

0

-1

-

4

-5

00 01 11 10

00

01

11

10

ABCD

3

-2

-

7

06

0

12

-13

0

8

-9

0

15 14

0

11

010

*

**

*


37/161

Page 35

A

B

C

D

Example: (circuit design) Design a combinational circuit to convert 3-bit Gray code to 3-bitbinary (this is called a Gray to binary decoder).

X AGray in Y B Binary out

Z C

X Y Z A B C A = (4,5,6,7), B= (2,3,4,5), C= (1,2,4,7)

0 0 0 0 0 00 0 1 0 0 1 0 1 0 0 1 1 0 1 1 0 1 0

1 0 0 1 1 1 1 0 1 1 1 0 1 1 0 1 0 0 1 1 1 1 0 1

A = X

B = X_Y_ +

_X_ Y = X Y

C = X_Y_

_Z_ +

_X_

_Y_ Z + XYZ +

_X_ Y

_Z_

= (X_Z_ +

_X_ Z)

_Y_ + (XZ+

_X_

_Z_ )Y = (X Z)

_Y_ + (

_X__

__Z_)Y = (X Z) Y = X YZ

Pay particular attention to the patterns that produced the XORs!

f(A,B,C,D)

_A____

+____

C_

ABCD

_B____

+____

D_

0 1

4

15

1

00 01 11 10

0

1

XYZ

3

12

1

7

16

1

0

1

1

4

15

00 01 11 10

0

1

XYZ

3 2

1

7

16

0

1

4

15

1

00 01 11 10

0

1

XYZ

3 2

7

16

1

K-mapfor A

K-mapfor C

K-mapfor B


38/161

Page 36

e

b

c

d

f

g

X A

Gray in Y B Binary out

Z C

Gray to Binary Decoder

A Gray to binary decoder is an example of a circuit that could bepackaged as a specialized circuit.

As an example of a more complex decoder, consider the 7-segment display

This are used to produce representations of decimal digits and (to alesser extent) the hex characters A-F as follows:

0 1 2 3 4 5 6 7 8 9 A B C D E F _ _ _ _ _ _ _ _ _ _ _ _| | | _| _| |_| |_ |_ | |_| |_| |_| |_ | _| |_ |_|_| | |_ _| | _| |_| | |_| | | | |_| |_ |_| |_ |

Pay particular attention to the difference between the representationsfor 6 and B (a common mistake is to interpret the B pattern as 6).

Note that a logic circuit to convert 4-bit (hexa)decimal data to 7-segment display format will require 7 outputs, one for each of segmentsa,b,c,d,e,f,g. If only a BCD conversion is needed, then the circuit is

simplified (somewhat) because for the inputs for A,B,C,D,E,F, the outputsare dont cares. The construction of such a circuit can be achieved bythe means already covered, albeit with some tedium due to the number ofoutputs.

The SN7447 chip is a BCD to 7-segment display decoder/driver (LEDsegments have to be protected from excess current, a capability built into this chip so that it can directly drive LED segments without use ofpull-up resistors). A worked out circuit diagram for this chip follows:

a


39/161

Page 37

BI Blanking Input; RBO Ripple Blanking Output; LT Lamp Test; RBI Ripple Blanking InputPoints marked are take HIGH by taking the blanking input line LOW (this forces all outputs HIGH)

SN 7447: BCD to 7-segment Display Decoder/Drivera

b

c

d

e

f

g

A

B

C

D

1

2

4

8

_B__I_

RBO

ABC

WiredAND

_L__T_

_R__B__I

Lamp test

B

C

D

_A_

_B_

_D_

_C_

_d_

_g_

_f_

_e_

_c_

_b_

_a_

BD_A_ C

BD

AB

A

_

B

_

_

C

__

D

_

_B_ C

CD

A_B_ C

_A_ BC

_A_ B

_C_

A_B_

_C_

_A_

_B_

C

B_C_

A_C_

_D_

ABC

_B_

_C_

_D_


40/161

Page 38

BI (Blanking Input), RBI (Ripple Blanking Input), and LT (Lamp Test) haveno effect if they are not connected or if their lines are held HIGH.

If the blanking input is taken LOW, a 1 is forced at each pointmarked , in effect blanking all LED by taking their lines high

Taking the lamp test input LOW forces the internal linesrepresenting A,B,C to go LOW, which internally produces the sameeffect as an input of numeric 0 or 8, thus enabling LED linesa,b,c,d,e, and f. LED line g requires an additional enable via theinternal lamp test line.

Taking the ripple blanking input line LOW enables the six input NANDgates in the circuit to respond to the internal lines representing_A_ ,

_B_ ,

_C_ ,

_D_ , which will then cause the blanking of the LEDs if

the numeric value of the input is 0. To suppress leading 0s ina sequence of digits, the blanking input line for each digit isused as an output (Ripple Blanking Output) connected to theripple blanking input line of the digit of next lower order (notethat as soon as a non-zero digit occurs in the sequence, itproduces a HIGH signal on RBO which will then cause rippleblanking to be disabled for all subsequent lower order digits).

Careful examination of the circuit shows that segment a is not lit forthe number 6!

BCD to 7-segment display function table:

D C B A_a_

_b_

_c_

_d_ _

e_ _

f_

_g_

0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 1 0 0 1 0 0 0 1 0 0 1 0

0 0 1 1 0 0 0 0 1 1 0 0 1 0 0 1 0 0 1 1 0 0 0 1 0 1 0 1 0 0 1 0 0 0 1 1 0 1 1 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 0- - - - - - - - - - -

(non-BCD input combinations are all dont cares)

Standard K-map analysis results in the following equations:_a_ = A

_B_

_C_

_D_ +

_A_ C + BD [BD added in from dont cares for blanking output purposes]

_b_ = A

_B_ C +

_A_ BC + BD [BD added in from dont cares for blanking output purposes]

_c_

=_A_ B

_C_ + CD [CD added in from dont cares for blanking output purposes]

_d_ = ABC + A

_B_

_C_ +

_A_

_B_ C

_e_ = A +

_B_ C

_f_ = AB + B

_C_ + A

_C_

_D_

_g_ = ABC +

_B_

_C_

_D_

Remark: the SN7447

display patternfor 6 is given by|_|_|


41/161

Page 39

Arithmetic circuits:

Half adder 2-bit addition is accomplished by XOR. A circuit for 2-bit addition that outputs both the sum (S) and carry (C out ) is called ahalf adder (a full adder also accounts for an input carry from a prioraddition (C in )

X Y S C out 0 0 0 00 1 1 01 0 1 01 1 0 1

Full adder To accommodate an input carry we have

X Y C in S C out

0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1

S = X Y C in by the same analysis used for the C output variable ofthe Gray to binary decoder discussed earlier.

Cout =

_

X

_

YC in + XYC in + X

_

Y

_

C in + XY

_

C

_

in which reduces nicely to= ( _X_ Y + X _Y_ )C in + XY(C in + _C_ in ) = (X Y)C in + XY

Both (X Y)C in and XY are produced by two half adders arranged asfollows:

Hence to get a full adder (FA) we simple use two half-adders with anOR gate applied to the two carries:

XY

S

Cout

Half adder (HA)

XY

CinS

(X Y)C in XY

HA HAX

Y

Cin

S

Cout


42/161

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[carry out via carry in from 1st FA]

4-bit parallel adder: Input is two 4-bit quantities (X 3 ,X 2 ,X 1 ,X 0) and(Y 3 ,Y 2 ,Y 1 ,Y 0). Input corresponding digits to each full adder circuitand propagate each carry out to the carry in of the next higher fulladder.

It is evident that this technique can be extended for multiple bits.The major drawback to this circuit construction is the fact that thecarry propagation must go through many circuit levels to reach thehigh order bit. For this reason, adders may employ carryanticipation ; for example, for a 2-bit adder, the C out value can bedetermined combinationally by examining its specification or simply

employing logic; i.e., C out is given by(X 1 AND Y 1) OR [carry out via X1 and Y1 alone] ((X 1 OR Y 1) AND X 0 AND Y 0) OR((X 1 OR Y 1) AND C in AND (X 0 OR Y 0)

Multiplier: Input is two 3-bit quantities (X 2 ,X 1 ,X 0) and (Y 2 ,Y 1 ,Y 0).Think in terms of the construction

X2 X1 X0 Y2 Y 1 Y 0

X2Y0 X1Y0 X0Y0 X2Y1 X1Y1 X0Y1

X2Y2 X1Y2 X0Y2

X2Y0 + 2 . . . + 2 X 0Y0

where + 2 is the binary addition accomplished by a full adder. Thenumber of gates for this kind of construction is the reasonmultiplication circuits may use sequential circuit techniques (to becovered later).

Subtraction: Full and half-subtractors can be constructed analogouslyto full and half-adders. Half subtractor 2-bit subtraction is alsoaccomplished by XOR. A circuit for 2-bit subtraction that outputsboth the difference (D) and borrow (B out ) is called a half subtractor (afull subtractor also accounts for an input borrow from a prior

subtraction (B in )

X Y D B out

0 0 0 00 1 1 11 0 1 01 1 0 0

FA FA FA FA

X3 Y 3

S1S3 S2 S0

X2 Y 2 X1 Y 1 X0 Y 0 Cin

Cout

XY

D

Bout

Half subtractor (HS)


43/161

Page 41

Full subtractor To accommodate an input borrow we have

X Y B in D B out

0 0 0 0 00 0 1 1 10 1 0 1 1

0 1 1 0 11 0 0 1 01 0 1 0 01 1 0 0 01 1 1 1 1

D = X Y B in by the same analysis used for the C output variable ofthe Gray to binary decoder discussed earlier.

Bout =_X_

_Y_ B in +

_X_ Y

_B_ in +

_X_ YB in + XYB in which reduces nicely to

= (_X_

_Y_ + XY)B in +

_X_ Y(B in +

_B_ in ) = (

_X___

___Y_)B in +

_X_ Y

Both (

_

X

___

____

Y

_

)B in and

_

X

_

Y are produced by two half subtractors arranged asfollows:

Hence to get a full subtractor (FS) we simple use two half-subtractorswith an OR gate applied to the two borrows:

4-bit parallel subtractor: Input is two 4-bit quantities (X 3 ,X 2 ,X 1 ,X 0)and (Y 3 ,Y 2 ,Y 1 ,Y 0). Input corresponding digits to each full subtractorcircuit and propagate each borrow out to the borrow in of the nexthigher full subtractor.

XY

BinD

(_X___

___Y_)B in

XY

HS HS

X

Y

Bin

D

Bout

FS FS

FS

FS

X3 Y 3

D1D3 D2 D0

X2 Y 2 X1 Y 1 X0 Y 0 Bin

Bout


44/161

Page 42

Just as for the adder circuit, it is evident that this technique can beextended for multiple bits. Note that the difference between the adderand subtractor circuits is in how the propagated signal is dealt with(whether carry or borrow).

BCD adder: Recall that BCD addition required adding 6 if the sumexceeded 9. A BCD adder can then be formed by combining a 4-bit binaryadder with circuitry to make the adjustment when the sum exceeds 9.Note that the test for 9 or greater is R 3 (R 2+R1+R0).

X3 Y 3 X 2 Y 2 X 1 Y 1 X 0 Y 0

R3 R 2 R 1 R 0

S3 S 2 S 1 S 0

BCD Sum

Note that when the exceeds 9 test is 0, the HA,FA,HA combinationsimply adds in 0, which has no effect on the sum; otherwise, 011 isadded to R 3R2R1 , in effect adding 6.

Other specialized circuits:

AOI gates: (AND-OR-Invert)

Suppose you have an expression such as (A +_B_ + C)(A + B). Then

double-inverting and applying the DeMorgan property, this becomes

(A +_B_ + C)(A + B) = (

_A_ B

_C_ )+ (

_A_

_B_ )

which is an AND-OR-Invert expression. Hence AOI gates are employed toimplement product of sums expressions. A 2-wide, 3-input AOI gate hasthe form:

4-bit binary adder

FAHA HA(add 6)

carryout

carryin

test for result > 9


45/161

Page 43

Decoders/demultiplexers:

Both the Gray to binary decoder and BCD to 7-segment displaydecoder/driver constructed earlier are cases of a class of circuitscalled decoders and demultiplexers. Basically, a decoder translatesinput data to a different output format.

Of particular interest is a decoder that decodes an input address toactivate exactly one of several outputs. In particular, a 1 of 2 n decoder is one for which exactly one of 2 n output lines goes High inresponse to an n-input address. If there is a data input line also,and the selected output matches the data input, then the circuit iscalled a demultiplexer .

Example 1: 1 of 8 demultiplexer

In essence a demultiplexer routes the input data to the addressedoutput.

Example 2: Constructing a 1 of 16 decoder/demultiplexer from two 1 of8 decoder/demultiplexers

Decoder/demultiplexers usually include a chip select or enable input to activate/deactivate the circuit. With an enable input alarger decoder/demultiplexer can be constructed from smaller ones;for example, a 1 of 16 decoder/demultiplexer can be constructed fromtwo 1 of 8 decoder/demultiplexers as follows:

This kind of construction is very useful for addressing memory.

124

01234567

Data in

Address in

Addressed outputs

124

01234567

Data in

124

01234567Address in CS

CS

1248

Addressed outputs

01234567

8

9101112131415


46/161

Page 44

A 1 of n decoder can also be used to directly implement a logicfunction . For example, the specification

f(X,Y,Z) = (2,5,6)

can be implemented using a 1 of 8 decoder by

Internally, a decoder simply uses AND gates to produce the desiredoutputs; e.g., a 1 of 4 decoder has the construction

So the circuit implementation for f(X,Y,Z) as implemented above isjust a sum of products (in fact, the canonical form since it is justminterms ORed together).

Multiplexers:

A multiplexer circuit is the inverse of a demultiplexer and is evenmore useful for implementing logic circuits because it does notrequire ORing of outputs.

An 8 input multiplexer has the form

For a multiplexer, the address refers to the input lines. The outputvalue is that of the addressed input. Normally, both a chip select lineand the complement of the output are also provided.

124

01234567

XYZ

f(X,Y,Z) = (2,5,6)1 of 8decoder

124

01234567

Data in

Address in

Output

CS

Output

Address in

0

1

2

3

Addressed outputs


47/161

Page 45

A 4 input multiplexer (MUX) has the construction:

The basic addressing strategy is the same as for a decoder, but for amultiplexer the AND gates are also used to enable (or suppress) inputvalues. Chip select is not implemented above, but can be accomplished byincreasing the input capacity of each AND gate, attaching the chip select

line to each AND. The OR gate that had to be supplied externally whenusing a decoder to implement a logic function is now incorporated intothe construction.

Implementing a logic function using a multiplexer is best illustrated byan example. Suppose that the specification

f(A,B,C,D) = (0,2,3,11,14)is what is given. f(A,B,C,D) can be implemented using an 8-inputmultiplexer as follows:

A B C D f(A,B,C,D)

0 0 0 0 10 0 0 1 00 0 1 0 10 0 1 1 10 1 0 0 00 1 0 1 00 1 1 0 00 1 1 1 01 0 0 0 01 0 0 1 01 0 1 0 01 0 1 1 11 1 0 0 0

1 1 0 1 01 1 1 0 11 1 1 1 0

Note that columns A,B,C select 0,1, ..., 7 in pairs, each of whichcorresponds to one of 0,D,

_D_ ,1 on the output side. This provides a

mapping from the truth table to an 8-input MUX as indicated. The SN74151chip is an 8-input MUX commonly used for this purpose.

0

1

2

3

Output

Output

Address in

_

D

_

1

0

0

0

D

0_D_ 12

4

0

1

2

3

4

5

6

7

ABC CS

f(A,B,C,D)

_f_

_D_

1

0

0

0

D

0_D_

0

1

2

3

4

5

6

7


48/161

Page 46

=

=

=

=

Comparators:

A comparator takes two input values and reports them as .Starting from the most significant bit, the comparator cascadescomparisons until corresponding bits are found that are different (thelimiting case is all bits are equal). The first occurrence ofcorresponding bits that are different determines whether the outputshould be > or

Ts

OUTPUTS

X3 Y3

X2 Y2

X1 Y1

X0 Y0

The top line is a< test. Eachremaining line isan = test for ahigher order bit

pair. 1 isoutput if the B3 ORA3 = B3 AND A2 > B2 ORA3 = B3 AND A2 = B2 AND A1 > B1 ORA3 = B3 AND A2 = B2 AND A1 = B1 AND A0 > B0 then

the "" output line will be 1

else (the result must be "=")the "" output line will be 0

Particular attention should be given to how the logic has beenimplemented in the circuit diagram. Contrast this to an approachthat seeks to work from a truth table specification to a minimalsum of products or product of sums solution.


50/161


51/161

Page 49

Step 3:Form the table of minterms and blocks from the first 2 steps. Markeach minterm participating in a block in the corresponding row-column as illustrated below. Any column with a single entry isessential. Continuing with the example we have:

0000 0010 0011 0100 0101 1000 1010 1011 1100 1101 1110 1111

-0-0 * * * *

--00 * * * *

-01- * * * *

-10- * * * *

1--0 * * * *

1-1- * * * *

11-- * * * *

Step 4:Remove the rows associated with essential entries along with anycolumns intersected by one or more of these

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