CMPEN 411VLSI Digital Circuits
Spring 2011
Lecture 08: MOS & Wire Capacitances
Sp11 CMPEN 411 L08 S.1
Lecture 08: MOS & Wire Capacitances
[Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]
Review: Delay Definitions
Vin
input
waveformtp = (tpHL + tpLH)/2
Propagation delay
50%
Vin Vout
Sp11 CMPEN 411 L08 S.2
t
Vout
output
waveform
t
50%
tpHL tpLH
tf
90%
10%
tr
signal slopes
CMOS Inverter: Dynamic
� Transient, or dynamic, response determines the maximum speed at which a device can be operated.
Sp11 CMPEN 411 L08 S.3
CMOS Inverter: Dynamic
VDD
Today’s focus
� Transient, or dynamic, response determines the maximum speed at which a device can be operated.
Sp11 CMPEN 411 L08 S.4
Rn
Vout = 0
Vin = V DD
CL tpHL = f(Rn, CL)
Next lecture’s focus
Sources of Capacitance
CDB2
CG4
Vout2Vin
Vout
VoutV
M2 M4
Vout2
CL
pdrain
Sp11 CMPEN 411 L08 S.5
Cw
CDB1
CGD12
CG3
wiring (interconnect) capacitance
intrinsic MOS transistor capacitances
extrinsic MOS transistor (fanout) capacitances
VoutVin
M1M3
Vout2
ndrain
Sources of Capacitance
wiring (interconnect) capacitance
intrinsic MOS transistor capacitances
Vout2Vin
extrinsic MOS transistor (fanout) capacitances
Vout
CL
Sp11 CMPEN 411 L08 S.6
Cw
CDB2
CDB1
CGD12
CG4
CG3
VoutVin
M2
M1
M4
M3
Vout2
ndrain
pdrain
Intrinsic MOS Capacitances
�Structure capacitances
�Channel capacitances
�Diffusion capacitances from the depletion regions of the reverse-biased pn-junctions
GC = C + C C = C + C
Sp11 CMPEN 411 L08 S.7
CGS
CSB CDB
CGD
CGB
S
G
B
D
CGS = CGCS + CGSO CGD = CGCD + CGDO
CGB = CGCB
CSB = CSdiff CDB = CDdiff
MOS Structure Capacitances
xdSource
n+
Drain
n+W
Ldrawn
xd
Poly Gate
Top view
lateral diffusion
Sp11 CMPEN 411 L08 S.8
n+n+
tox
Leff
CGSO = CGDO = Cox xd W = Co W
Overlap capacitance (linear)
MOS Channel Capacitances
S D
GVGS +
CGS = CGCS + CGSO CGD = CGCD + CGDO
� The gate-to-channel capacitance depends upon the operating region and the terminal voltages
Sp11 CMPEN 411 L08 S.9
p substrate
B
-
n+n+
depletion
regionn channel
CGB = CGCB
Review: Summary of MOS Operating Regions
� Cutoff (really subthreshold) VGS ≤VT
� Exponential in VGS with linear VDS dependence
ID = IS e (qVGS/nkT) (1 - e -(qVDS/kT) ) (1 - λ VDS) where n ≥ 1
� Strong Inversion VGS >VT
� Linear (Resistive) VDS <VDSAT = VGS - VT
ID = k’ W/L [(VGS – VT)VDS – VDS2/2] (1+λVDS) κ(VDS)
Sp11 CMPEN 411 L08 S.10
ID = k’ W/L [(VGS – VT)VDS – VDS /2] (1+λVDS) κ(VDS)
� Saturated (Constant Current) VDS ≥VDSAT = VGS - VT
IDSat = k’ W/L [(VGS – VT)VDSAT – VDSAT2/2] (1+λVDS) κ(VDS)
VT0(V) γ(V0.5) VDSAT(V) k’(A/V2) λ(V-1)
NMOS 0.43 0.4 0.63 115 x 10-6 0.06
PMOS -0.4 -0.4 -1 -30 x 10-6 -0.1
Average Distribution of Channel Capacitance
Operation Region
CGCB CGCS CGCD CGC CG
Cutoff CoxWL 0 0 CoxWL CoxWL + 2CoW
Linear (Resistive)
0 CoxWL/2 CoxWL/2 CoxWL CoxWL + 2CoW
Saturation 0 (2/3)CoxWL 0 (2/3)CoxWL (2/3)CoxWL +
Sp11 CMPEN 411 L08 S.11
Saturation 0 (2/3)CoxWL 0 (2/3)CoxWL (2/3)CoxWL + 2CoW
� Channel capacitance components are nonlinear and
vary with operating voltage
� Most important regions are cutoff and saturation
� Total gate cap is getting smaller with increased
saturation
MOS Diffusion Capacitances
S D
GVGS +
-
� The junction (or diffusion) capacitance is from the reverse-biased source-body and drain-body pn-junctions.
Sp11 CMPEN 411 L08 S.12
p substrate
B
-
n+n+
depletion
regionn channel
CSB = CSdiff CDB = CDdiff
Source Junction View
channel
W
xj
channel-stop
implant (NA+)
source
bottom plate
(ND)
junction
depth
Sp11 CMPEN 411 L08 S.13
side walls
channel
LS
substrate (NA)
Cdiff = Cbp + Csw = Cj AREA + Cjsw PERIMETER
= Cj LS W + Cjsw (2LS + W)
depth
Transistor Capacitance Values for 0.25µµµµ
Example: For an NMOS with L = 0.25 µm, W = 0.36 µm, LD = LS = 0.625 µm
CGC = Cox WL =
CGSO = CGDO = Cox xd W = Co W =
so Cgate_cap = CoxWL + 2CoW =
C = C L W =
Sp11 CMPEN 411 L08 S.14
Cox
(fF/µm2)
Co
(fF/µm)
Cj
(fF/µm2)
mj φb(V)
Cjsw
(fF/µm)
mjsw φbsw(V)
NMOS 6 0.31 2 0.5 0.9 0.28 0.44 0.9
PMOS 6 0.27 1.9 0.48 0.9 0.22 0.32 0.9
Cbp = Cj LS W =
Csw = Cjsw (2LS + W) =
so Cdiffusion_cap =
Transistor Capacitance Values for 0.25µµµµ
Example: For an NMOS with L = 0.25 µm, W = 0.36 µm, LD = LS = 0.625 µm
CGC = Cox WL = 0.52 fF
CGSO = CGDO = Cox xd W = Co W = 0.11 fF
so Cgate_cap = CoxWL + 2CoW = 0.74 fF
C = C L W = 0.45 fF
Sp11 CMPEN 411 L08 S.15
Cbp = Cj LS W = 0.45 fF
Csw = Cjsw (2LS + W) = 0.45 fF
so Cdiffusion_cap = 0.90 fF
Diff_cap dominates Gate_cap? Worst case onlyTypically Diff_cap <=Gate_cap when normal operation
Review: Sources of Capacitance
VoutV
CDB2CGD12
M2 M4
Vout2
CG4
Vout2Vin
Vout
CL
pdrain
Sp11 CMPEN 411 L08 S.16
Vout
Cw
Vin
CDB1
CGD12
M1M3
Vout2
CG3
wiring (interconnect) capacitance
intrinsic MOS transistor capacitances
extrinsic MOS transistor (fanout) capacitances
ndrain
Gate-Drain Capacitance: The Miller Effect
Vin
CGD1 Vout
∆V
∆V
Vout
∆V
∆V
2CGB1
� M1 and M2 are either in cut-off or in saturation.
� The floating gate-drain capacitor is replaced by a capacitance-to-ground (gate-bulk capacitor).
Sp11 CMPEN 411 L08 S.17
� Miller Effect: A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground whose value is two times the original value.
M1
∆V
VinM1
∆V 2CGB1
Drain-Bulk Capacitance: Keq’s (for 0.25 µµµµm)
� We can simplify the diffusion capacitance calculations even further by using a Keq to relate the linearized capacitor to the value of the junction capacitance under zero-bias
Ceq = Keq Cj0
Sp11 CMPEN 411 L08 S.18
high-to-low low-to-high
Keqbp Keqsw Keqbp Keqsw
NMOS 0.57 0.61 0.79 0.81
PMOS 0.79 0.86 0.59 0.7
Extrinsic (Fan-Out) Capacitance
� The extrinsic, or fan-out, capacitance is the total gate capacitance of the loading gates M3 and M4.
Cfan-out = Cgate (NMOS) + Cgate (PMOS)
= (CGSOn+ CGDOn+ WnLnCox) + (CGSOp+ CGDOp+ WpLpCox)
Sp11 CMPEN 411 L08 S.19
� Simplification of the actual situation
� Assumes all the components of Cgate are between Vout and GND (or VDD)
� Assumes the channel capacitances of the loading gates are constant
Layout of Two Chained Inverters (See pg 197)
InOut
Metal1
VDD
1.2 µm=2λλλλ
1.125/0.25
PMOS
Sp11 CMPEN 411 L08 S.20
GND0.375/0.25
NMOS
Polysilicon
W/L AD (µµµµm2) PD (µµµµm) AS (µµµµm2) PS (µµµµm)
NMOS 0.375/0.25 0.3 1.875 0.3 1.875
PMOS 1.125/0.25 0.7 2.375 0.7 2.375
Components of CL (0.25 µµµµm)
C TermExpression Value (fF)
H→→→→LValue (fF)L→→→→H
CGD1 2 Con Wn0.23 0.23
CGD2 2 Cop Wp0.61 0.61
CDB1 KeqbpnADnCj + KeqswnPDnCjsw 0.66 0.90
CDB2 KeqbppADpCj + KeqswpPDpCjsw 1.5 1.15
Sp11 CMPEN 411 L08 S.21
CDB2 KeqbppADpCj + KeqswpPDpCjsw 1.5 1.15
CG3 (2 Con)Wn + CoxWnLn 0.76 0.76
CG4 (2 Cop)Wp + CoxWpLp 2.28 2.28
Cw from extraction 0.12 0.12
CL ∑ 6.1 6.0
Wiring Capacitance
� The wiring capacitance depends upon the length and width of the connecting wires and is a function of the fan-out from the driving gate and the number of fan-out gates.
� Wiring capacitance is growing in importance with the scaling of technology.
Sp11 CMPEN 411 L08 S.22
Wiring capacitance is growing in importance with the scaling of technology.
Parallel Plate Wiring Capacitance
electrical field lines
W
H
current flow
L
Sp11 CMPEN 411 L08 S.23
H
tdi dielectric (SiO2)
substrate
Cpp = (εdi/tdi) WLpermittivity
constant
(SiO2= 3.9)
Permittivity Values of Some Dielectrics
Material εdiFree space 1
Teflon AF 2.1
Aromatic thermosets (SiLK) 2.6 – 2.8
Polyimides (organic) 3.1 – 3.4
Fluorosilicate glass (FSG) 3.2 – 4.0
Sp11 CMPEN 411 L08 S.24
Fluorosilicate glass (FSG) 3.2 – 4.0
Silicon dioxide 3.9 – 4.5
Glass epoxy (PCBs) 5
Silicon nitride 7.5
Alumina (package) 9.5
Silicon 11.7
Hafnium dioxide 22
IBM vs. INTEL
IBM has now announced another milestone in semiconductor manufacturing.
This new manufacturing technique uses a material technologists refer to as
a "low-k dielectric" to meticulously shield millions of individual copper circuits
on a chip. IBM is the first to use the low-k dielectric technique with copper
wiring. Chip wires were previously insulated with silicon dioxide. IBM has
figured out how to replace the silicon dioxide with a low-k dielectric shield.
Intel Corporation today announced it has identified new materials to replace
those that have been used to manufacture chips for more than 30 years. The
Sp11 CMPEN 411 L08 S.25
those that have been used to manufacture chips for more than 30 years. The
breakthrough is to replace the gate oxide, which is silicon dioxide, with a high-K
dielectric
Question: this two breakthrough technologies are different:
IBM replaces SiO2 with low-k dielectric while Intel replace
SiO2 with high-K dielectric. Please explain why IBM and Intel
take different approaches
Sources of Interwire Capacitance
Cwire = Cpp + Cfringe + Cinterwire
= (εdi/tdi)WL
+ (2πεdi)/log(tdi/H)
+ (εdi/tdi)HL
Sp11 CMPEN 411 L08 S.26
interwire
fringe
pp
When W<1.75H the interwire cap dominates!
Impact of Interwire Capacitance
Sp11 CMPEN 411 L08 S.27
(from [Bakoglu89])
Wiring Insights
� For W/H < 1.5, the fringe component dominates the parallel-plate component. Fringing capacitance can increase the overall capacitance by a factor of 10 or more.
� When W/H < 1.75 interwire capacitance starts to dominate
� Interwire capacitance is more pronounced for wires in the higher interconnect layers (further from the substrate)
Sp11 CMPEN 411 L08 S.28
� Rules of thumb
� Never run wires in diffusion
� Use poly only for short runs
� Shorter wires – lower R and C
� Thinner wires – lower C but higher R
� Wire delay nearly proportional to L2
Wiring Capacitances
Field Active Poly Al1 Al2 Al3 Al4
Poly 88
54
Al1 30 41 57
40 47 54
Al2 13 15 17 36
25 27 29 45
Al3 8.9 9.4 10 15 41
fringe in aF/µm
pp in aF/µm2
Sp11 CMPEN 411 L08 S.29
Al3 8.9 9.4 10 15 41
18 19 20 27 49
Al4 6.5 6.8 7 8.9 15 35
14 15 15 18 27 45
Al5 5.2 5.4 5.4 6.6 9.1 14 38
12 12 12 14 19 27 52
Poly Al1 Al2 Al3 Al4 Al5
Interwire Cap 40 95 85 85 85 115
per unit wire length in aF/µm for minimally-spaced wires
Dealing with Capacitance
� Low capacitance (low-k) dielectrics (insulators) such as polymide or even air instead of SiO2
� family of materials that are low-k dielectrics
� must also be suitable thermally and mechanically and
� compatible with (copper) interconnect
� Copper interconnect allows wires to be thinner without
Sp11 CMPEN 411 L08 S.30
� Copper interconnect allows wires to be thinner without increasing their resistance, thereby decreasing interwire capacitance
� SOI (silicon on insulator) to reduce junction capacitance
Next Lecture and Reminders
� Next lecture
� MOS resistance
- Reading assignment – Rabaey, et al, 4.3.2, 4.4.1-4.4.4
Sp11 CMPEN 411 L08 S.31