INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONSInt. J. Circ. Theor. Appl. 2013Published online in Wiley Online Library (wileyonlinelibrary.com). DOI: 10.1002/cta.1939
Cost reduction in bottom-up hierarchical-based VLSIfloorplanning designs
Chyi-Shiang Hoo, Kanesan Jeevan*,† and Harikrishnan Ramiah
Department of Electrical Engineering, University of Malaya, Lembah Pantai, 50603 Kuala Lumpur, Malaysia
The number of transistors in a very-large-scale integration (VLSI) chip design has increased rapidly,and the features of integrated circuits have progressively scaled down nowadays. Hence,floorplanning [1–7] is a crucial step in VLSI circuit design [8] as it determines the quality of thedeep submicron chip quality, manufacturing cost and the time-to-market. Although there are severalcircuit design objectives to be considered during floorplanning, such as area minimization,wirelength optimization [9], delay reduction [10, 11], thermal stability [12–14], clock tree synthesis[15] or any combination of these objectives [16–18], the basic objective of floorplanning is tominimize the area of the VLSI chip.
However, floorplanning problems have been proven to be NP-hard. Since floorplan framework has adirect impact on the floorplanning results [7], different framework approaches are proposed to handlethe floorplanning problems, depending on their scale and difficulties. In IMF [19], three major
*Correspondence to: K. Jeevan, Department of Electrical Engineering, University of Malaya, Lembah Pantai, 50603Kuala Lumpur, Malaysia.†E-mail: [email protected]
framework categories have been studied: (1) the flat [20–41], (2) the hierarchical [42–48] and (3) themultilevel [49, 50], as depicted graphically in [7].
There have been a number of flat framework floorplan representations developed either slicing ornon-slicing structure (mosaic and general) [51], in order to tackle the floorplan problems in terms ofevaluation complexity, type of floorplans, redundancies, encode–decode process runtimes andpossible permutations [51]. Because non-slicing representations are claimed to be P-admissible [31,32] and can represent all the solutions, some researches were carried out to reduce the redundancyin slicing [48] and transforming slicing structure into non-slicing structure [43, 44, 47].Nevertheless, the flat frameworks are feeble in terms of scalability handling capability as the designsize increases. Many mathematical results in floorplanning representations do not translate intobetter VLSI layout [51]. Most of the encoding and decoding processes between representations andfloorplan topologies are quite time consuming (e.g. the lowest representation-to-placement runtimeamong the existing representations is O(n) for O-tree [22][37], B*-tree [20] and slicing binary tree[35, 36]. Furthermore, the redundancy of the representations cannot be completely eliminated, andthis increases the runtime and the complexity of the evaluation. Moreover flat frameworks cannottackle multi-objective floorplanning optimization [45].
In order to cope up with the drawbacks in the flat frameworks, hierarchical frameworks areintroduced. The general flat framework is strongly NP-complete [46] while the area minimizationusing hierarchical framework is proven to be weakly NP-complete [45]. In hierarchical framework,there are two basic approaches which are the top-down and the bottom-up approaches. In order toconstruct a VLSI floorplan by using the top-down hierarchical framework, a circuit layout will bepartitioned by the floorplanner into p number of smaller subregions, and allocating modules intothe subregions without overriding the constraints, such as balance weights for the subregions.While for the bottom-up hierarchical framework construction, the floorplanner starts with partialsolutions (p number of modules are clustered), merged with other modules or clusters recursivelyuntil a complete solution (complete layout) is obtained. The clustering process is done based oncertain objectives.
In general, the top-down hierarchical placer is preferable as the initial global placement as theinformation about the circuit can be transferred from higher hierarchical level to the lower one.Besides, the top-down floorplan outcome is predictable in terms of outline and whitespace.However, the bottom-up placer requires much simpler model based on hierarchical construction ascompared to the top-down hierarchical construction. Besides, bottom-up placer can handle arbitrary-sized modules in a physical hierarchical manner [52], and this approach is more flexible ascompared to the top-down. Mixed-Mode Placement (MMP) employs a bottom-up framework whichis optimized by the quadratic programming and min-cut technique [53]. However, MMP is notcompared with other techniques empirically [54]. Hierarchical Performance Driven Multi-levelPartitioning [55] is a floorplanning algorithm which clusters the modules in a bottom-up manner atthe beginning and being refined eventually. However, no experimental result is available in thisreport for the empirical comparison with other floorplanning algorithms. MB*-tree [56] proposes atwo-stage multilevel framework which is initiated with the bottom-up clustering, followed by top-down uncoarsening.
2. PROBLEM DESCRIPTION
There are two types of modules involved in the floorplanning problems, which are the hard and the softtypes. Hard modules are defined with their widths and heights fixed and cannot be altered. Soft moduledimensions can be changed during the floorplanning process without exceeding the maximumdimension ratio and retaining the areas of the modules. The inputs to a floorplanner are: the areas ofthe modules, the maximum aspect ratios for soft modules and the fixed dimensions for hard moduleswhile the output is the final floorplan where the location of the modules and I/O pins aredetermined. The chip size indicating the utilization of the space and the wirelength indicating thetiming performance are measured using the final floorplan layout.
Let B is a set of c rectangular modules represented as B= {b1, b2, … , bc}, S is a set of e netlistsrepresented as S= {s1, s2, … , se} and the width, height and area of the module bm are denoted aswm, hm and Am, respectively, with the constraint of 1≤m≤ c. Each module bm is associated via theset of netlist sh, where sh ε S and 1≤ h≤ e.
In the VLSI floorplanning problem, all the modules bm are placed to generate a floorplan layoutwhere there is no physical overlap among the modules. Typically, VLSI floorplanning is to optimizethe chip's area and/or the wirelength brought on by the placement of bm's without prolonging theruntime considerably. The area of the VLSI chip floorplan layout is defined by the area of thesmallest rectangle formed to encapsulate all the modules placed. Wirelength is usually measured bycalculating half-perimeter wirelength (HPWL), which is less complicated and less time consuming.In this work, the chip's area minimization is the main objective.
3. PROPOSED ALGORITHM
A hierarchical-based floorplan layout is described by a p-nary tree [45], if there are p child nodes foreach node in maximum (tree-order = p). An example of a 5-nary tree which is constructed bybottom-up clustering process is employed to represent the bottom-up hierarchical floorplan layout,as illustrated in Figure 1. However, the computational complexity and the runtime increase when theorder p increases, due to the NP-hard property. Though p can be reduced to be less than five, aminimum value of five is necessitated to generate all the possible perturbations.
In this work, a bottom-up hierarchical floorplanning algorithm with p equal to five is developed todeal with hard module floorplanning problems. In handling soft module floorplanning problem, theorder is brought down to two due to the flexibility of change of dimensions of soft modules. Cull-and-Aggregate Bottom-up Floorplanner (CABF) algorithm consists of two steps, namely culling andaggregating as shown in Figure 2.
3.1. Linear ordering culling stage
Let a cluster tree to be denoted as T, an arbitrary node in T to be denoted as v and the set of unorderedchild nodes with the parent node v to be denoted by θ(v). In order to determine the order in which
Figure 1. Bottom-up hierarchical construction and corresponding modules placement.
remained=1?Culling stage Aggregating stage Final floorplan
No
Figure 2. Flowchart for CABF algorithm.
C.-S. HOO, K. JEEVAN AND H. RAMIAH
modules are selected, linear ordering algorithm is employed. Linear ordering is one of the well-knowntechniques for initial placement construction. Initially, for node v of the tree T, the first module of theculling list θ′(v) is selected randomly, to be the seed module from θ(v) for hard module floorplanningproblems. Meanwhile, in handling the soft module floorplanning problems, the smallest module fromθ(v) will be selected as the seed module. Then, the seed module will be removed from the set ofunordered modules, and the algorithm will enter an iterative loop. For each iteration, a vector, χ, whichindicates the hard module dimensions' differences or the soft module areas' differences between thecurrently ordered module and the remaining unordered modules in θ(v), is generated. Let the modules'heights and widths are denoted by hi and wi, respectively, then the χ-vector is defined as:
χ ¼< χ1; χ2;…; χs >
where
i. s=maximum edges in a complete graph of θ(v) number of nodes
s ¼ θ vð Þ2
� �¼ θ vð Þ!
2! θ vð Þ � 2ð Þ! ¼θ vð Þ θ vð Þ � 1ð Þ
2
andii.
χu ≤ χuþ1; for 1≤ u≤ s� 1:
Let {j, k} ∈ θ(v) and j≠ k. Different approaches are employed for hard and soft modulefloorplanning problems as below:
a. In hard module floorplanning problem, the u-th member of the χ-vector is defined as:
χu ¼ χjk
¼ minhj � wk
�� ��max hj;wk
� � !
;wj � wk
�� ��max wj;wk
� � !
;hj � hk�� ��
max hj; hk� �
!;
wj � hk�� ��
max wj; hk� �
!(
b. In soft module floorplanning problem, the u-th member of the χ-vector is defined as:
χu ¼ χjk ¼ wj�hj� �� wk�hkð Þ�� ��:
After a module is selected, the next module is selected based on the min{χ} in the χ-vector, which isχ1. The unordered module which corresponds to χ1 would lead to the next ordered module in theculling list θ′(v). Now, all the ordered modules will be removed from the set of unordered modulesθ(v). This linear ordering algorithm will be terminated once the number of ordered modules in the θ′(v)-list is two (soft module floorplanning problems) and five (hard module floorplanning problems).
Let a region with height h and width w, to be partitioned into a pair of child partitions, with the widthsw1 and w2, respectively. Also, assume two child clusters with the dimensions of w1, h1, w2 and h2 astheir heights and widths, respectively, where the widths of child clusters and child partitions are thesame, and h1 and h2 are maximally equal to h. By summing the areas of these two child partitions,which are Q1 and Q2, respectively, we have the area of the cluster Q=Q1+Q2, where Q1≤Q, andQ2≤Q. It is a common technique where clusters are placed into a partition, and then the partition istreated as a new cluster [7]. Hence, the child clusters are placed into the partition, where each childclusters are assigned onto the child partitions which possess the same width.
Since the whitespace created in a cluster cannot be altered as no compaction algorithm is introduced,the whitespace is passed on to the next higher level. This propagated whitespace will never be takeninto consideration during next culling or aggregating process. Thus, the whitespace S yield by bothclusters in the partitioned region is simply the addition of the whitespace of both clusters, which isS1 + S2 whilst the relative whitespace a is equal to S/Q. The relative whitespace sγ is equal to Sγ / Qγ,where 1≤ γ≤ 2, as illustrated in Figure 3. Let the relative whitespaces of the child partitions to bedenoted as q1 and q2, the relative whitespace of the cluster a can be defined as:
s ¼ S
Q
¼ S1Q
þ S2Q
¼ S1Q1
�Q1
Q
� �þ S2
Q2�Q2
Q
� �
As discussed above, s = Sγ / Qγ, 1≤ γ≤ 2, the expression for relative whitespace a can be reduced to:
s ¼ s1Q1
Qþ s2
Q2
Q(1)
Since Q=Q1 +Q2, and, therefore, we have Q1/Q+Q2/Q = 1 where the ratios (Q1/Q) and (Q2/Q) arealways positive values. Thus, it is distinctly evidenced that the relative whitespace of a partition withtwo child partitions is a convex combination of its own child partitions' relative whitespaces. Hence, itcan be induced that the relative whitespace s always lies between s1 and s2, by referring to themathematical properties of the convex combination. By assuming s1≤ s2, then we have s1≤ s≤ s2.In bottom-up clustering technique, the dimension of the partition will be shrunk until all the childclusters are just sufficiently being fitted in [7]. Hence, h =max(h1, h2), and then, s1 = 0. Now, theinequality equation can be reduced to 0≤ s≤ s2 and a2 can be calculated using:
Figure 3. Region which is divided into two child partitions (with areas of Q1 and Q2, respectively), whereeach of them is placed by two child clusters (dotted modules).
The expression is now rewritten to be 0≤ s≤ 1�(h2/h1). Hence, by handling the maximum limit ofthe inequality equation, the VLSI chip's area minimization sorting function can be simplified to thelinear order sorting cost function as given by (2):
cost function ¼ 1� h2h1
(2)
with the constraint that h2≤ h1.It can evident that (2) is a linear function which can be computed handily. Manifestly, the VLSI area
minimization floorplanning problem can be solved optimally when the ratio (h2/h1) is maximized sothat it is closer to unity. Though the dimensional reduction of (2), the area-based floorplanningproblem's complexity can be reduced remarkably by just handling one-dimensional cost functionoptimization.
3.3. Aggregating stage
3.3.1. Aggregating cost metric. Adya and Markov [42] proved that the aspect ratio of the chip, whichis defined as the ratio of the width to the height of the chip, has an effect on the wirelength. In Chenet al. [57] the proper interpretation was done by proving that the aspect ratio closer to unity will bebeneficial to the shortening of wirelength. This is done by splitting the HPWL into two wirelength-strips along two perpendicular directions, and, thus, the expected x-direction wirelength wirex, y-direction wirelength wirey and summation of both x and y components wirex +wirey are linear alongthe width W, height H and summation of width and height W+H of the chip, respectively. Thisconcept of aspect ratio is adapted into the cost metric of the aggregating stage.
However, area and aspect ratio are different dimensionally, where area is the product of dimensionwhilst aspect ratio is the division of the dimension. Hence, area and aspect ratio are normalized in orderto overcome the disparity. Let the relative whitespace, aspect ratio, width and height of the cluster to bedenoted by a, R, w and h respectively. Then, the cost metric of the aggregating stage is defined as:
Zð Þ sð Þ þ 1-Zð Þ R–1ð Þ (3)where
a = whitespace/ (w*h)Z= the normalized area's weightage, bounded by 0≤ Z≤ 1, andR= max{w/h, h/w}.
It is observed that (3) is a convex combination of the convergence of the aspect ratio towards unityand the relative whitespace, which result in the priority issue between these two independent variables.Even though it is proven that the near-optimal solution can be generated by finding out the suitablechoice of coefficients [58], it is not practical for a placer to automate all the possible coefficientpairs. Consequently, the relative whitespace is given the dominance rather than the other, as areaoptimization is the main concern in this work.
3.3.2. Aggregating algorithm for hard module floorplanning problems. During the aggregatingprocess, four groups are foremost generated by allocating the first n modules from the culling list,namely θ′(v)-list (discussed in section 3.1) to each of the group denoted by Gn�1 = {d1,…, dn}where 2≤ n≤ 5 and dn is the n-th member of the culling list. Let the first five modules in the cullinglist to be {b1, b3, b5, b2, b4}, then the group vector G formed is:
For each group, the best permutation of all the modules selected is chosen based on the cost metric(3), without violating the overlap-free constraint. Let the centers of two modules, b1 and b2, to bedenoted as {x1,y1} and {x2, y2}, respectively, then this two modules are defined as physicallyoverlapping each other when they fulfill these two conditions:
• x2 � x1j j < w2þw1j j2 ; where w2> 0, w1> 0
• y2 � y1j j < h2þh1j j2 ; where h2> 0, h1> 0
For the coincidence where two or more groups generate same value of cost metric, the group withhigher number of members will be selected. After the aggregating process, the cluster formed will beaddressed to be a new single module. Next, the culling stage is followed with another aggregatingstage. These culling and aggregating processes are carried out recursively till all the hard modules inthe floorplanning problem are agglomerated and assigned as one single module, as illustrated in Figure 4.
3.3.3. Aggregating algorithm for soft module floorplanning problems. In handling the soft modulefloorplanning, the aggregating stage is simply the combination of two modules. After theaggregation, a new cluster is created by adding the areas of both modules. During bottom-up
hierarchical floorplanning, information about the heights and widths of the modules are unnecessarydue to the flexibility of the soft modules' dimensions to alter freely in order to satisfy themselvesduring the final floorplan. Hence, a minimal whitespace or even whitespace-free floorplan can begenerated. When the cluster tree is constructed, constraints are computed and one soft module isassigned to the individual constraints. Let the soft module's dimension ratio, U is defined as:
U ¼ U min; ;U max½ � ¼ u∈R U min≤u≤U maxgjf
where Umin and Umax are defined as the lower and lower bounds of the dimension ratios of the softmodule, respectively. If the height and width constraints of the space where the soft module isassigned to are set to be xconst and yconst, respectively, then the height, h, and width, w, of the softmodule with area of A have the values of:
CABF was executed by using the GNU GCC compiler on a Windows-XP PC workstation with IntelPentium M 1.2-GHz CPU and 256-MB RAM memory. CABF best results are obtained after beingcompiled for 30 times, and the comparisons are made on the following state-of-the-art floorplanning/placement algorithms: Corner Block List (CBL) [23], soft modules with Lagragian Relaxation (SOFT-LR) [59], Transitive Closure Graph-Sequence Pair [27], Block-packing with Branch-and-Bound(BloBB) [60], Parquet [42,60], PATOMA [50], Chen et al. [49], Moving Block Sequence-Organizational Evolutionary Algorithm (MBS-OEA) [29], Elitist Non-Dominated Sorting basedGenetic Algorithm Floorplanner (ENDSGA) [61], Discrete Particle Swarm Optimization (DPSO) [62],Evolutionary Simulated Annealing (ESA) [63] and Hybrid Simulated Annealing (HSA) [64]. TheMicroelectronics Center of North Carolina (MCNC) and Gigascale Systems Research Center (GSRC)[65] benchmarks are used as the standards for comparisons, as presented in Table I. In reference toTable I, it is observed that the number of modules for the benchmark circuits varies from 9 to 600,
which is sufficient to validate the scalability and robustness of the floorplanning algorithms. The capabilityof CABF in handling large-sized placement problems is demonstrated. The maximum dimension ratio iscalculated by dividing the maximum dimension of a module with its minimum dimension. Similarly, theminimum dimension ratio is the ratio of the module's minimum dimension to its maximum dimension.The quality of CABF placer's area optimization results is evaluated by calculating the whitespace of thechip. The whitespace is calculated by computing the difference between the area of the smallestrectangle which envelops all the VLSI modules in the chip, and the total area of these modules.Although the wirelength optimization is not our main concern, the performance of the wirelengthminimization of the placement is evaluated by using HPWL. As discussed in Sections 2 and 3.2.1,HPWL of a floorplan layout is defined as:
HPWL ¼ ∑e
i¼1HPWL
where
HPWLi ¼ HPWL of netlist-i
¼ ðmaxi∈e xif g � mini∈e xif gÞ þ maxi∈e yif g � mini∈e yif gð Þ; ande is the total netlists of the floorplanning benchmark problem:
Normalization technique is employed to compute and make a fair comparison between CABFresults and the other floorplanning algorithms. The normalized value is defined as the ratio of theresults of the other algorithms to the CABF results [7].
4.1. Hard modules floorplanning problems
In this work, the experimental results of all the hard module floorplanning problems by executing CABFare shown in Table II. In reference to the statistics, it is observed that the chip floorplan layouts for all the
benchmark circuits are compacted at a minimal value of 1.46% and maximally to 9.95% of relativewhitespaces. The runtimes for the proposed CABF is ranging from 0.03 to 28 s. The near-optimal areas,near-optimal HPWLs and the short runtimes indicate that CABF is a robust floorplanning algorithmwhere the near-optimal solutions can be generated within a restrained timeframe, even though CABF isan area-driven floorplanner. Moreover, the small increment in percentages of relative whitespacesobtained out of the simulations with CABF with the increased number of blocks indicates that CABF isa floorplanner with improved scalability, consistency and reliability.
Table III compares the MCNC benchmark results of CABF with BloBB, Parquet, Chen et al.,ENDSGA, DPSO, ESA and HSA. The CPU speeds used for the simulation of the respective
Table III. Result comparison by using MCNC hard module benchmark circuits.
a,bsimulated on a 1.2-GHz Linux Athlon workstation.csimulated on a 2.0-GHz PC/Intel system.dsimulated on the SUN SPARCv9 workstation.esimulated on a 1.46-GHz PC/AMD workstation.f,gsimulated on a 2.0-GHz PC/Intel system.hsimulated on a 1.2-GHz PC/Intel system.d,edo not evaluate the results in terms of runtime.
floorplanning algorithms are shown in Table III, and CABF is simulated in the CPU with the slowestspeed. The areas and runtimes of all the state-of-the-art algorithms are normalized and given inTable IV. From Table III, the results indicate that the proposed CABF gives comparable results interms of area in all the cases run with CABF. By referring to the normalized areas in Table IV, it isquite obvious that CABF generates improved or the same normalized results in 34 out of 37 casesshown. Also, by referring to the normalized runtimes in Table IV, CABF shows improved runtimesin 19 out of 25 cases although CABF is simulated on a slower PC. It is noted that CABF showsimproved runtimes, especially compared to the state-of-the-art algorithms, such as ESA and HSA,with runtimes in a range of 30 to 38545 times faster. This achievement is fulfilling the current trendin industrial floorplanning which requires high speed and robustness. For example, Xilinx® hadrevealed the necessity of FPGA-based platform design for a shorter timeframe in physical design sothat the engineers can modify, apprehend, analyze and implement their designs in FPGAs quickly[66]. By using MCNC benchmarks, it is proven that CABF can deliver comparable results in termsof area with a shorter runtime. Figure 5 shows the optimized ami49 MCNC hard module benchmarkplacement layout by using CABF.
Table IV. Normalized result comparison by using MCNC hard module benchmark circuits.
a,bsimulated on a 1.2-GHz Linux Athlon workstation.csimulated on a 2.0-GHz PC/Intel system.dsimulated on the SUN SPARCv9 workstation.esimulated on a 1.46-GHz PC/AMD workstation.f,gsimulated on a 2.0-GHz PC/Intel system.hsimulated on a 1.2-GHz PC/Intel system.d,edo not evaluate the results in terms of runtime.
Figure 5. Optimized hard module floorplanning placement layout by CABF on ami49 (MCNC benchmark).
Table V compares the GSRC hard module benchmark results of CABF with BloBB, Parquet, Chenet al., ENDSGA and DPSO. In Table V, the CPU speeds of the all the floorplanning algorithms areshown. The areas and runtimes in Table V are normalized with respect to CABF and are given inTable VI for easy comparisons. From Tables V and VI, the results indicate that the proposed CABFgenerates floorplans utilizing equal or better area optimization in a shorter period of runtime for allthe cases. The normalized runtimes of CABF are ranging from 1.3 to 88 times faster than otherfloorplanning algorithms even though CABF was simulated on the slowest PC. These comparisonsby using GSRC hard module benchmarks show that CABF gives improved performances in termsof areas and runtimes against the other floorplanning algorithms. Figure 6 shows the optimizedlayout of n600 GSRC hard modules benchmark placement using CABF.
In reality, GSRC benchmarks are preferable as they can reflect the real VLSI floorplanning problems.This is because GSRC benchmarks have much larger number of blocks as compared to the MCNCbenchmarks. However, both benchmarks are used for comparisons. By using MCNC and GSRCbenchmark circuits, the comparison between CABF's near-optimal relative whitespace generated in thehard module floorplanning problems and the other floorplanning algorithms is carried out, as shown inFigure 7. It is observed that the relative whitespaces of CABF are lower than others and the results aresignificantly improved when the scale of the problem increases. By referring to the relative whitespacetrendline in Figure 7, the optimal results of floorplanning problems with scale size larger than 600 canbe predicted. Though all the relative whitespace trendlines tend to converge for larger number ofblocks, CABF algorithm tends to saturate to the lowest relative whitespace. This highlights thesignificant improvement of CABF in handling hard module floorplanning problems, as compared toother algorithms in terms of robustness, scalability and convergence. These properties will aid CABF in
0
5
10
15
20
25
0 100 200 300 400 500 600 700 800 900
Rel
ativ
e w
hite
spac
e (%
)
Number of modules
BloBB
Parquet
Chen at al. (2007)
ENDSGA
DPSO
CABF
BloBB
Parquet
Chen et al.
ENDSGA
DPSO
CABF
Figure 7. MCNC and GSRC hard module benchmark relative whitespace comparisons.
Figure 6. Optimized hard module floorplanning placement layout by CABF on n600 (GSRC benchmark).
handling ultra-large-scale industrial floorplanning which can be up to 3.9 billion of transistors in a singlechip of Altera® FPGA device [67].
Runtime comparisons are carried out on the following recent floorplanning algorithms: BloBB,Parquet, Chen et al., ESA and HSA. All these floorplanning algorithms were implemented on PCswith CPU speeds ranging from 1.2 GHz to 2.0 GHz, and their runtime results using the GSRC andMCNC hard module benchmark circuits are shown in Figure 8(a). Due to the substantially largervalues of predicted runtimes of HSA when the number of modules increases, the runtimes ofBloBB, Parquet and CABF could not be distinguished clearly, and hence the enlarged runtimetrendlines of these three floorplanning algorithms are shown separately in Figure 8(b). Based on theruntime trendlines of Figures 8(a) and 8(b), the runtimes of all the floorplanning algorithms areincreasing rapidly as compared to CABF when the size of the benchmark problems increases. It isto be noted that the runtime trendline of BloBB is in parallel with CABF indicating that BloBBruntime is higher than the CABF runtime thorough. From Figures 7 and 8, the lower dependency ofCABF in terms of area minimization and runtime results with respect to the scale of the problems isevident. This makes the trade-off between the runtimes and the area optimization easier.
4.2. Soft modules floorplanning problems
The experimental results for soft module floorplan problems, which were run with CABF, are shown inTable VII. Out of 21 optimal solutions, CABF achieves whitespace-free solutions in 19 cases. In otherwords, 90.5% of the soft module floorplan layout solutions generated by using CABF have zerowhitespaces. Regardless of the increment of number of modules in the floorplanning problems, thefloorplan results remain intact. This observation proves the capability of CABF in handlingfloorplanning problems which have huge number of modules effectively. It is shown that CABF hasthe capability of handling large-size problems giving zero whitespaces and maintaining reliabilityand stability of the algorithm.
(a) Runtime comparisons
(b) Magnified runtime comparisons
-2000
0
2000
4000
6000
8000
10000
12000
0 100 200 300 400 500 600 700
Run
times
(s)
Number of modules
BloBB
Parquet
Chen et al. (2007)
HSA
ESA
CABF
BloBB
Parquet
Chen et al.
HSA
ESA
CABF
-20
0
20
40
60
80
100
0 100 200 300 400 500 600 700 800 900
Run
times
(s)
Number of modules
BloBB
Parquet
CABF
BloBB
Parquet
CABF
Figure 8. Runtime comparison by using MCNC and GSRC hard module benchmark circuits.
Table VIII compares the area and runtime results of CABF with CBL, SOFT-LR and MBS-OEA byusing the MCNC and GSRC soft modules benchmark circuits, while Table IX shows the normalizedareas and normalized PC runtimes computed from Table VIII. The PC speeds of all the algorithmsare shown in Table VIII. As all these floorplanning algorithms were simulated with different PCspeed, the normalized runtimes cannot be used as the standards for comparison of these algorithms
Table VIII. MCNC and GSRC soft module benchmark comparisons.
SOFT-LRa CBLj MBS-OEAk CABFh
Area (mm2) Runtime (s) Area (mm2) Runtime (s) Area (mm2) Runtime (s) Area (mm2) Runtime (s)
asimulated on a 600-MHz PC/Intel system.jsimulated on the SUN SPARCv20 workstation.ksimulated on a IBM IntelliStation Z Pro Type 6221.hsimulated on a 1.2-GHz PC/Intel system.
with CABF. Hence, in order to predict the runtime results of all these floorplanning algorithms underthe same simulation platform, normalized PC runtimes are employed where it is calculated bymultiplying the normalized runtimes with the respective normalized PC speeds. The normalizedPC speeds are the ratios of ‘the PC's operating frequencies of other algorithms’ to ‘the PC'soperating frequency of CABF’. In other words, PC runtime is the product of runtime results, andthe PC frequency speed in GHz whilst normalized PC runtime is the ratio of the PC runtimes ofother algorithm to CABF. The fundamental concept of introducing PC runtime is the algorithmwith same complexity will have a slower runtime result if it is simulated in a lower PC withfrequency speed, and vice versa. Hence, PC runtime is able to compensate the uncertainty causedby the PC frequency speed. From Tables VIII and IX, it is seen that the results of CABF are betterin terms of area based on the comparison with all the other existing algorithms. Also, CABF hasshown significantly improvements in terms of area and runtime for higher number of modules. Inreference to Table IX, it is evident that the normalized PC runtimes of CABF are much lower ascompared to other algorithms, with CABF runtimes ranging from 1.3 to 185488 times faster. Inother words, CABF will generate the near-optimal area minimization results with the time at least26% times faster than the other algorithms if all the floorplanning algorithms are simulated underthe same PC. Figure 9 shows the optimized layout of n300 GSRC soft modules benchmarkplacement layout.
By using the MCNC and GSRC soft module floorplanning benchmark circuits, CABF near-optimalrelative whitespace results are compared with other floorplanning algorithms and the comparison isillustrated in Figure 10. In reference to the relative whitespace trendline in Figure 10, it is evidentthat two floorplanners, namely MBS-OEA and SOFT-LR, tend to reach relative whitespaces whichis higher in value as compared to CABF, when the number of blocks in the floorplanning problemsincreases. Meanwhile, in reference to the another floorplanning algorithms, which is CBL, it isobserved clearly that CBL tend to converge to a relative whitespace with lower value, and CABFrelative whitespace trendline tends to remain constant having a value about zero. Based on theresults of these four floorplanning algorithms, it is pretty clear that the trendline of CABF depictsthe CABF results in terms of relative whitespace remain at a nearly zero value when the scale of thefloorplanning problems increases, whilst the other existing floorplanners bring about to whitespaceswith higher values on convergence.
Figure 9. Best n300 soft module floorplanning placement layout by CABF.
-2
0
2
4
6
8
10
12
0 50 100 150 200 250 300 350 400
Rel
ativ
e W
hite
spac
e (%
)
Number of Modules
SOFT-LR
CBL
MBS-OEA
CABF
SOFT-LR
CBL
MBS-OEA
CABF
Figure 10. Relative whitespace comparison by using MCNC and GSRC soft module benchmark circuits.
C.-S. HOO, K. JEEVAN AND H. RAMIAH
5. CONCLUSION
A variable-order bottom-up floorplanning algorithm, called CABF has been proposed in this paper.CABF is accomplished to compact a chip floorplan layout, where the floorplanning problemsinvolve both soft and hard modules. In handling hard module floorplanning problems, the 2-D areaminimization cost function is proven mathematically that it can be reduced to 1-D length-basedoptimization metric. In culling stage, modules are sorted based on differences in widths and heights(hard modules floorplanning problems) or differences in areas (soft modules floorplanningproblems). Meanwhile, in aggregating stage, formation of group with maximum members of five(hard modules floorplanning problems) or two (soft modules floorplanning problems) enables theCABF to select the best cluster to be formed. These two stages of CABF have reduced the searchspace and complexity and hence increased the speed of CABF giving promising results. The resultsobtained experimentally have established the better performance of CABF especially when thecircuit size and complexity increase especially in the soft modules floorplanning. In reference to thegraphs, it is manifest that CABF has an edge over the other existing floorplanning algorithms interms of area optimization, in handling larger sized floorplanning problems. In comprehensive, it isevident that CABF is an effective floorplanner, in respect of scalability and reliability and can be arobust floorplanner for industrial applications.
The authors would like to thank HIR grants H-16001-00-D000051, FRGS grant FP065/2010B and RG095/12ICT from the University of Malaya, Kuala Lumpur, Malaysia, for the research fund support.
REFERENCES
1. Otten RHJM. Graphs in floor-plan design. International Journal of Circuit Theory and Applications, Special Issue:Fudamental Methods in Computer-aided Circuit Design 1988; 16(4):391–410. DOI: 10.1002/cta.4490160405.
2. Micheli GD. Computer-aided design and optimization of control units for VLSI processors. International Journal ofCircuit Theory and Applications 1988; 16(4):347–369. DOI: 10.1002/cta.4490160403.
3. Zhang L, Zhang Y, Jiang Y, Shi C-JR. Symmetry-aware placement algorithm using transitive closure graph represen-tation for analog integrated circuit. International Journal of Circuit Theory and Applications 2010; 38(3):221–241.DOI: 10.1002/cta.551.
4. Hsu C-L, Huang Y-S, Lee F-C. Interlaced switch boxed placement for three-dimensional FPGA architecture design.International Journal of Circuit Theory and Applications 2010; 40(5):489–502. DOI: 10.1002/cta.739.
5. Tsay R-S, Kuh ES, Hsu C-P. Module Placement for Large Chips Based on Sparse Linear Equations. InternationalJournal of Circuit Theory and Applications 1988; 16(4):411–423. DOI: 10.1002/cta.4490160406.
6. Zhang L, Raut R, Jiang Y, Kleine U, Kim Y. A hybrid evolutionary analogue module placement algorithm forintegrated circuit layout designs. International Journal of Circuit Theory and Applications 2005; 33(6):487–501.DOI: 10.1002/cta.332.
7. Hoo C-S, Yeo H-C, Jeevan K, Ganapathy V, Ramiah H, Badruddin IA. Hierarchical congregated ant system forbottom-up VLSI placements. Engineering Applications of Artificial Intelligence 2013; 26(1):584–602. DOI:10.1016/j.engappai.2012.04.007.
8. Földesy P, Rodríguez-Vázquez A. A behavioural modelling technique for visual microprocessor mixed-signal VLSIchips. International Journal of Circuit Theory and Applications 2002; 30(2-3):139–163. DOI: 10.1002/cta.193.
9. Niemier MT, Kogge PM. Problems in designing with QCAs: Layout = Timing. International Journal of CircuitTheory and Applications 2001; 29(16):49–62. DOI: 10.1002/1097-007X(200101/02)29:1<49::AID-CTA132>3.0.CO;2-1.
10. Alioto M,Consoli E, Palumbo G. From energy-delay metrics to constraints on the design of digital circuits.International Journal of Circuit Theory and Applications 2011. DOI: 10.1002/cta.757.
11. Nikolaidis S, Chatzigeorgiou A. Analytical estimation of propagation delay and short-circuit power dissipation inCMOS gates. International Journal of Circuit Theory and Applications 1999; 27(4):375–392. DOI: 10.1002/(SICI)1097-007X(199907/08)27:4<375::AID-CTA64>3.0.CO;2-7.
12. Conte G. A general method for small-signal circuit analysis considering thermal effects. International Journal ofCircuit Theory and Applications 1978; 6(1):41–47. DOI: 10.1002/cta.4490060106.
13. Mardiris VA, Karafyllidis IG. Design and simulation of modular 2n to 1 quantum-dot cellular automata (QCA)multiplexers. International Journal of Circuit Theory and Applications 2012; 38(8):771–785. DOI: 10.1002/cta.595.
14. Storti-Gajani G, Premoli A. Electrothermal stability of uniform arrays of one-port elements. International Journal ofCircuit Theory and Applications 2009; 37(1):67–85. DOI: 10.1002/cta.496.
15. Eudes T, Ravelo B. Analysis of multi-gigabits signal integrity through clock H-tree. International Journal of CircuitTheory and Applications 2009. DOI: 10.1002/cta.818.
16. Anand S, Saravanasankar S, Subbaraj P. A multiobjective optimization tool for very large scale integrated nonslicingfloorplanning. International Journal of Circuit Theory and Applications 2012. DOI: 10.1002/cta.829.
17. Anand S, Saravanasankar S, Subbaraj P. Customized simulated annealing based decision algorithms for combinato-rial optimization in VLSI floorplanning problem. Computational Optimization and Applications 2012; 52(3). DOI:10.1007/%2Fs10589-011-9442-y.
18. Hoo C-S, Jeevan K, Ganapathy V, Ramiah H. Variable-order ant system for VLSI multiobjective floorplanning.Applied Soft Computing 2013; 13(7):3285–3297. DOI: 10.1016/j.asoc.2013.02.011.
19. Chen TC, Chang YW, Lin SC. A new multilevel framework for large-scale interconnect-driven floorplanning. IEEETransactions on Computer-Aided Design of Integrated Circuits and Systems 2007; 27(2):286–294. DOI: 10.1109/TCAD.2007.907065.
20. Chang YC, Chang YW, Wu GM, Wu SW. B*-trees: A new representation for nonslicing floorplans. In DAC'00:Proceedings of the 37th Annual ACM/IEEE Design Automation Conference, 2000; 458–463.
21. Hoo C-S, Jeevan K, Ganapathy V, Ramiah H. Ant System-Corner Insertion Sequence: An Efficient VLSI Hard ModulePlacer. Advances in Electrical and Computer Engineering 2013; 13(1):13–16. DOI: 10.4316/AECE.2013.01002.
22. Guo PN, Takahashi T, Cheng CK, Yoshimura T. Floorplanning using a tree representation. IEEE Transactions onComputer-Aided Design Integrated Circuits and Systems 2001; 20(2):281–289. DOI: 10.1109/43.908471.
23. Hong X, Huang G, Cai Y, Gu J, Dong S, Cheng CK, Gu J. Corner Block List: An effective and efficient topolog-ical representation of nonslicing floorplan. In proceedings of ACM/IEEE Design Automation Conference, 2000;8–12.
24. Hong X, Huang G, Cai Y, Gu J, Dong S, Cheng CK, Gu J. Corner Block List and its application to floorplan opti-mization. IEEE Transactions on Circuits and Systems II 2004; 51(5):228–233. DOI: 10.1109/TCSII.2004.824047.
25. Kang M, Dai WWM. General floorplanning with L-shaped, T-shaped and soft blocks based on bounded slicing gridstructure. In Proceedings of the Asia and South Pacific Design Automation Conference, 1997; 265–170.
26. Lin JM, Chang YW. TCG: A transitive closure graph-based representation for nonslicing floorplans. In Proceedingsof ACM/IEEE Design Automation Conference, 2001; 764–769.
27. Lin JM, Chang YW. TCG-S: Orthogonal coupling of p*-admissible representation with worst case linear-time pack-ing scheme. IEEE Transactions on Computer-Aided Design Integrated Circuits and Systems 2004; 23(6):968–980.DOI: 10.1109/TCAD.2004.828114.
28. Lin JM, Chang YW, Lin SP. Corner Sequence: A p-admissible floorplan representation with a worst case linear timepacking scheme. IEEE Transactions on Very Large Scale Integration Systems 2003; 11(4):679–686. DOI: 10.1109/TVLSI.2003.816137.
29. Liu J, Zhong WC, Jiao LC, Li X. Moving block sequence and organizational evolutionary algorithm for generalfloorplanning with arbitrarily shaped rectilinear blocks. IEEE Transactions on Evolutionary Computation 2008;12(5):630–646. DOI: 10.1109/TEVC.2008.920679.
30. Ma Y, Hong X, Dong S, Chang YW. Floorplanning with abutment constraints and I-shaped/t-shaped blocks based oncorner block list. In Proceedings of Design Automation Conference, 2001; 770–775.
31. Murata H, Fujiyoshi K, Nakatake S, Kajitani Y. Rectangle-packing-based module placement. In Proceedings ofACM/IEEE International Computer-aided Design Automation Conference, 1995; 472–479.
32. Murata H, Fujiyoshi K, Nakatake S , Kajitani Y. VLSI module placement based on rectangle-packing bythe sequence pair. IEEE Transactions on Computer-Aided Design Integrated Circuits and Systems 1996;15(12):1518–1524. DOI: 10.1109/43.552084.
33. Nakatake S, Fujiyoshi F, Murata H, Kajitini Y. Module placement on BSG-structure and IC layout applications. InProceedings of ACM/IEEE International Computer-Aided Design Automation Conference, 1996; 484–491.
34. Ohtsuki T, Suzigama N, Hawanishi H. An optimization technique for integrated circuit layout design. In Proceedingsof International Conference on Circuit and System Theory, 1970; 101–107.
35. Otten RHJM. Automatic floorplan design. In Proceedings of ACM/IEEE Design Automation Conference, 1982a;261–267.
36. Otten RHJM. Layout structures. In Proceedings of Large Scale Systems Symposium, 1982b; 349–353.37. Pang Y, Cheng CK, Yoshimura T. An enhanced perturbing algorithm for floorplan design using the O-tree
representation. In Proceedings of the 2000 International Symposium on Physical Design, 2000; 168–173.38. Tang X, Wong DF. Fast-SP: A fast algorithm for block placement based on sequence pair. In Proceedings of IEEE
Asia South Pacific Design Automation Conference, 2001; 521–526.39. Young EFY, Chu CCN, Shen ZC. Twin binary sequence: A nonredundant representation for general nonslicing
floorplan. IEEE Transactions on Computer-Aided Design Integrated Circuits and Systems 2003; 22(4):457–469.DOI: 10.1109/TCAD.2003.809651.
40. Zhuang C, Sakanushi K, Jin L, Li X. An enhanced Q-sequence augmented with empty-room-insertion and parenthe-sis tress. In Proceedings of Conference on Design, Automation and Test in Europe, 2002; 61–68.
41. Zhou H, Wang J. ACG-Adjacent constraint graph for general floorplans. In Proceedings of International ConferenceComputer Design, 2004; 572–575.
42. Adya SN, Markov IL. Fixed-outline floorplanning: enabling hierarchical design. IEEE Transaction on Very LargeScale Integration Systems 2003; 11(6):1120–1135. DOI: 10.1109/TVLSI.2003.817546.
43. Lai MH, Wong DF. Slicing tree is a complete floorplan representation. In Proceedings of Conference on Design,Automation and Test, 2001; 228–232.
44. Pan P, Liu CL. Area minimization for floorplans. IEEE Transactions on Computer-Aided Design on IntegratedCircuits and Systems 1995; 14(1):123–132. DOI: 10.1109/43.363119.
45. Pan P, Shi WP, Liu CL. Area minimization for hierarchical floorplans. Algorithmica 1996; 15(6):550–571. DOI:10.1007/%2FBF01940881.
46. Stockmeyer L. Optimal orientations of cells in slicing floorplan designs. Information and Control 1983; 57(2-3):91–101.DOI: 10.1016/S0019-9958(83)80038-2.
47. Wang TC, Wong DF. Optimal floorplan area optimization. IEEE Transactions on Computer-Aided Design ofIntegrated Circuits and Systems 1992; 11(8):992–1002. DOI: 10.1109/43.149770.
48. Wong DF, Liu CL. A new algorithm for floorplan design. In Proceedings of ACM/IEEE Design AutomationConference, 1986; 101–107.
49. Chen DS, Lin CT, Wang YW, Cheng CH. Fixed-outline floorplanning using robust evolutionary search. EngineeringApplications of Artificial Intelligence 2007; 20(6):821–830. DOI: 10.1016/j.engappai.2006.10.006.
50. Cong J, Romesis M, Shinnerl JR. Fast floorplanning by look-ahead enabled recursive bipartitioning. IEEETransactions on Computer-Aided Design of Integrated Circuits and Systems 2006; 25(9):1719–1732. DOI:10.1109/TCAD.2005.859519.
51. Chan HH, Adya SN, Markov IL. Are floorplan representations important in digital design? In Proceedings of Inter-national Symposium Physical Design, 2005; 129–136.
52. Dai WM, Kuh ES. Simultaneous floorplanning and global routing for hierarchical building-block layout. IEEETransactions on Computer-Aided Design Integrated Circuits and Systems 1987; 6(5):828–837. DOI: 10.1109/TCAD.1987.1270326.
53. Yu H, Hong X, Cai Y. MMP: A novel placement algorithm for combined macro-block and standard cell layoutdesign. In Proceedings of Asia and South Pacific Design Automation Conference, 2000; 271–276.
54. Roy JA, Adya SN, Papa DA, Markov IL. Min-cut floorplacement. IEEE Transactions on Computer-Aided DesignIntegrated Circuits and Systems 2006; 25(7):1313–1326. DOI: 10.1109/TCAD.2005.855969.
55. Wang L, Selvaraj H. Performance driven circuit clustering and partitioning. In International Conference on Informa-tion Technology Coding and Computing, 2002; 352–354.
56. Lee HC, Chang YW, Hsu JM, Yang YW. Multilevel floorplanning/placement for large-scale modules using B*-tree.In Proceedings of ACM/IEEE Design Automation Conference, 2003; 812–817.
57. Chen S, Yoshimura T. Fixed-outline floorplanning: block-position enumeration and a new method for calculating areacosts. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2008; 27(5):858–871. DOI:10.1109/TCAD.2008.917968 .
58. Jagannathan A, Hur SW, Lillis J. A fast algorithm for context-aware buffer insertion. ACM Transactions on DesignAutomation of Electronic Systems (TODAES) 2002; 7(1):368–373. DOI: 10.1145/504914.504922.
59. Young FY, Chu CCN, Luk WS, Wong YC. Handling soft modules in general nonslicing floorplan using LagrangianRelaxation. IEEE Transactions Computer-Aided Design Integration Circuits Systems 2001; 20(5):687–692. DOI:10.1109/43.920707.
60. Chan HH, Markov IL. Practical slicing and non-slicing block-packing without simulated annealing. In Proceedingsof ACM Great Lake Symposium on VLSI, 2004; 282–287.
61. Fernando P, Katkoori S. An elitist non-dominated sorting based genetic algorithm for simultaneous area andwirelength minimization for VLSI floorplanning. 21st International Conference on VLSI Design (VLSID), 2008;337–342.
62. Chen GL, Guo WZ, Chen YZ. A PSO-based intelligent decision algorithm for VLSI floorplanning. Soft Computing-AFusion of Foundations, Methodologies and Applications 2009; 14(12):1329–1337. DOI: 10.1007/s00500-009-0501-6.
63. Chen J, Chen J. A hybrid evolution algorithm for VLSI floorplanning. In International Conference on ComputationalIntelligence and Software Engineering (CiSE), 2010; 1–4.
64. Chen J, Zhu W, Ali MM. A hybrid simulated annealing algorithm for nonslicing VLSI floorplanning. IEEETransactions on Systems, Man, and Cybernetics, Part C: Applications and Reviews 2011; 41(4):544–553. DOI:10.1109/TSMCC.2010.2066560.
65. Gigascale System Research Center. MCNC and GSRC benchmark circuits. 2005; Available from: http://www.cse.ucsc.edu/research/surf/GSRC/progress.html. Accessed on: 21 May 2009.
66. Xilinx. Xilinx Press Release. Available from: http://www.xilinx.com/prs_rls/xil_corp/0468_hierdesign.htm.Accessed on: 1 Feb. 2010.
67. Altera. Altera Product Release. Available from: http://www.altera.com/corporate/news_room/releases/2011/prod-ucts/nr-sv_milestone.html. Accessed on: 22 Apr. 2012.
