CSE331 W01.1 Irwin Fall 06 PSU CSE 331 Computer Organization and Design Fall 2006 Week 1 Section 1:...

CSE331 W01.1 Irwin Fall 06 PSU

CSE 331Computer Organization and

DesignFall 2006

Week 1

Section 1: Mary Jane Irwin (www.cse.psu.edu/~mji)

Section 2: Feihui Li (www.cse.psu.edu/~feli )

Adaptado al curso Diseño de Sistemas Digitales. R. Pereira

[slides adapted from D. Patterson slides with additional credits to Y. Xie]


Course Administration Texts: Computer Organization and Design: The

Hardware/Software Interface, 3rd Edition, Patterson and Hennessy


Course Goals and Structure

Introduction to the major components of a computer system, how they function together in executing a program, how they are designed

MIPS assembler programming using the spim system VHDL design simulation using the Synopsys VSS tools

Prerequisite: CSE 271 (INTRO TO DIGITAL SYSTEMS. Introduction to logic design and digital systems, boolean algebra, and introduction to combinatorial and sequential circuit design and analysis)

En el curso Estructura de Microprocesadores aprenderán otro lenguaje ensamblador (IA80x86)


spim Assembler and Simulator

spim is a simulator that runs MIPS32 assembly language programs

It provides a simple assembler, debugger and a simple set of operating system services

It implements both a simple, terminal-style interface (spim) and a visual windowing interface (xspim and PCSpim)

Available as xspim (or spim) for unix, linux, and Mac OS X

- installed on the CSE unix/linux machines in the lab

PCSpim (or spim) for Windows (NT, 2000, XP)- can be downloaded and installed on your own PC from

www.cs.wisc.edu/~larus/SPIM


What You Should Already Know How to write, compile and run programs in a higher

level language (C, C++, Java, …) How to create, organize, and edit files and run

programs on Unix How to represent and operate on positive and negative

numbers in binary form (two’s complement, sign magnitude, etc.)

Logic design How to design of combinational and sequential components

(Boolean algebra, logic minimization, technology mapping, decoders and multiplexors, latches and flipflops, registers, mealy/moore finite state machines, state assignment and minimization, etc.)

How to use a logic schematic capture and simulation tool (e.g., LogicWorks)


Schedule

This week’s material Course introduction, basics of a computer system,

introduction to SPIM

- Reading assignment – PH 1.1 through 1.3 and A.9 through A.10

Next week’s material Introduction to MIPS assembler, adds/loads/stores

- Reading assignment - PH 2.1 through 2.4


The Evolution of Computer Hardware

When was the first transistor invented? Modern-day electronics began with the invention in

1947 of the transfer resistor - the bi-polar transistor - by Bardeen et.al at Bell Laboratories


The Evolution of Computer Hardware

When was the first IC (integrated circuit) invented? In 1958 the IC was born when Jack Kilby at Texas

Instruments successfully interconnected, by hand, several transistors, resistors and capacitors on a single substrate


The Underlying Technologies

Year Technology Relative Pref/Unit Cost

1951 Vacuum Tube 1

1965 Transistor 35

1975 Integrated Circuit (IC) 900

1995 Very Large Scale IC (VLSI) 2,400,000

2005 Ultra VLSI 6,200,000,000

What if technology in the transportation industry advanced at the same rate?


The PowerPC 750

Introduced in 1999

3.65M transistors366 MHz clock

rate40 mm2 die size250nm

technology


Technology Outlook

High Volume Manufacturing

2004 2006 2008 2010 2012 2014 2016 2018

Technology Node (nm)

90 65 45 32 22 16 11 8

Integration Capacity (BT)

2 4 8 16 32 64 128 256

Delay = CV/I scaling

0.7 ~0.7 >0.7 Delay scaling will slow down

Energy/Logic Op scaling

>0.35 >0.5 >0.5 Energy scaling will slow down

Bulk Planar CMOS High Probability Low ProbabilityAlternate, 3G etc Low Probability High ProbabilityVariability Medium High Very HighILD (K) ~3 <3 Reduce slowly towards 2 to 2.5RC Delay 1 1 1 1 1 1 1 1

Metal Layers 6-7 7-8 8-9 0.5 to 1 layer per generation


Impacts of Advancing TechnologyProcessor

logic capacity: increases about 30% per year

performance: 2x every 1.5 years

Memory DRAM capacity: 4x every 3 years, about 60% per

year memory speed: 1.5x every 10 years cost per bit: decreases about 25% per year

Disk capacity: increases about 60% per year


Growth Capacity of DRAM Chips

K = 1024 (210)In recent years growth rate has slowed to 2x every 2 year


Computer Organization and Design

This course is all about how computers work

But what do we mean by a computer? Different types: embedded, laptop, desktop, server

Different uses: automobiles, graphics, finance, genomics…

Different manufacturers: Intel, Apple, IBM, Sony, Sun…

Different underlying technologies and different costs !

Analogy: Consider a course on “automotive vehicles” Many similarities from vehicle to vehicle (e.g., wheels)

Huge differences from vehicle to vehicle (e.g., gas vs. electric)

Best way to learn: Focus on a specific instance and learn how it works

While learning general principles and historical perspectives


Embedded Computers in You Car


Growth of Sales of Embedded Computers


Why Learn This Stuff?

You want to call yourself a “computer scientist/engineer”

You want to build HW/SW people use (so need performance)

You need to make a purchasing decision or offer “expert” advice

Both hardware and software affect performance Algorithm determines number of source-level statements

Language/compiler/architecture determine the number of machine-level instructions

- (Chapter 2 and 3)

Processor/memory determine how fast machine-level instructions are executed

- (Chapter 5, 6, and 7)


What is a Computer?

Components: processor (datapath, control) input (mouse, keyboard) output (display, printer) memory (cache (SRAM), main memory (DRAM), disk

drive, CD/DVD) network

Our primary focus: the processor (datapath and control)

Implemented using millions of transistors Impossible to understand by looking at each transistor We need abstraction!


Major Components of a Computer


Head’s Up This week’s material

Course introduction- Reading assignment – PH 1.1 through 1.3 and A.9 through A.10

Reminders Make sure your unix account is operational; change your

password to something you can remember and that is secure (must be six to eight alphanumeric characters)

Question/comments about the system go to [email protected] ; questions about the programming assignments go to the course TAs

Check out the course homepage at ANGEL!

Next week’s material Introduction to MIPS assembler

- Reading assignment - PH 2.1 through 3.3, 3.4, and 3.7


Quote for the Day

“We all make mistakes … Our designs have to work flawlessly despite us.”

Bob Colwell

The Pentium Chronicles


Below the Program High-level language program (in C)

swap (int v[], int k)(int temp;

temp = v[k];v[k] = v[k+1];v[k+1] = temp;

)

Assembly language program (for MIPS)swap: sll $2, $5, 2

add $2, $4, $2lw $15, 0($2)lw $16, 4($2)sw $16, 0($2)sw $15, 4($2)jr $31

Machine (object) code (for MIPS) 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000

. . .

C compiler

assembler

one-to-many

one-to-one


Advantages of Higher-Level Languages ?

Higher-level languages

As a result, very little programming is done today at the assembler level

Allow the programmer to think in a more natural language and for their intended use (Fortran for scientific computation, Cobol for business programming, Lisp for symbol manipulation, Java for web programming, …)

Improve programmer productivity – more understandable code that is easier to debug and validate

Improve program maintainability Allow programs to be independent of the computer on which

they are developed (compilers and assemblers can translate high-level language programs to the binary instructions of any machine)

Emergence of optimizing compilers that produce very efficient assembly code optimized for the target machine


Machine Organization

Capabilities and performance characteristics of the principal Functional Units (FUs)

e.g., register file, ALU, multiplexors, memories, ...

The ways those FUs are interconnected

e.g., buses

Logic and means by which information flow between FUs is controlled

The machine’s Instruction Set Architecture (ISA) Register Transfer Level (RTL) machine description


ISA Sales


Major Components of a Computer

Processor

Control

Datapath

Memory

Devices

Input

Output

Network


Below the Program

C compiler

assembler

High-level language program (in C) swap (int v[], int k) . . . Assembly language program (for MIPS) swap: sll $2, $5, 2 add $2, $4, $2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31

Machine (object) code (for MIPS) 000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000


Input Device Inputs Object Code

Processor

Control

Datapath

Memory

000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000 100011 00010 01111 0000000000000000 100011 00010 10000 0000000000000100 101011 00010 10000 0000000000000000 101011 00010 01111 0000000000000100 000000 11111 00000 0000000000001000

Devices

Input

Output

Network


Object Code Stored in Memory

Processor

Control

Datapath

Memory

000000 00000 00101 0001000010000000000000 00100 00010 0001000000100000100011 00010 01111 0000000000000000100011 00010 10000 0000000000000100101011 00010 10000 0000000000000000101011 00010 01111 0000000000000100000000 11111 00000 0000000000001000

Devices

Input

Output

Network


Processor Fetches an Instruction

Processor

Control

Datapath

Memory

000000 00000 00101 0001000010000000000000 00100 00010 0001000000100000100011 00010 01111 0000000000000000100011 00010 10000 0000000000000100101011 00010 10000 0000000000000000101011 00010 01111 0000000000000100000000 11111 00000 0000000000001000

Processor fetches an instruction from memory

Devices

Input

Output

Network


Control Decodes the Instruction

Processor

Control

Datapath

Memory000000 00100 00010 0001000000100000

Control decodes the instruction to determine what to execute

Devices

Input

Output

Network


Datapath Executes the Instruction

Processor

Control

Datapath

Memory

contents Reg #4 ADD contents Reg #2results put in Reg #2

Datapath executes the instruction as directed by control

000000 00100 00010 0001000000100000

Devices

Input

Output

Network


What Happens Next?

Processor

Control

Datapath

Memory

000000 00000 00101 0001000010000000000000 00100 00010 0001000000100000100011 00010 01111 0000000000000000100011 00010 10000 0000000000000100101011 00010 10000 0000000000000000101011 00010 01111 0000000000000100000000 11111 00000 0000000000001000

Fetch

DecodeExec

Devices

Input

Output

Network


Processor Fetches the Next Instruction

Processor

Control

Datapath

Memory

000000 00000 00101 0001000010000000000000 00100 00010 0001000000100000100011 00010 01111 0000000000000000100011 00010 10000 0000000000000100101011 00010 10000 0000000000000000101011 00010 01111 0000000000000100000000 11111 00000 0000000000001000

Processor fetches the next instruction from memory

How does it know which location in memory to fetch from next?

Devices

Input

Output

Network


Processor Organization Control needs to have circuitry to

What location does it load from and store to?

Decide which is the next instruction and input it from memory Decode the instruction Issue signals that control the way information flows between

datapath components Control what operations the datapath’s functional units

perform

Execute instructions - functional units (e.g., adder) and storage locations (e.g., register file)

Interconnect the functional units so that the instructions can be executed as required

Load data from and store data to memory

Datapath needs to have circuitry to


Output Data Stored in Memory

Processor

Control

Datapath

Memory

000001000101000000000000000000000000000001001111000000000000010000000011111000000000000000001000

At program completion the data to be output resides in memory

Devices

Input

Output

Network


Output Device Outputs Data

Processor

Control

Datapath

Memory

000001000101000000000000000000000000000001001111000000000000010000000011111000000000000000001000

Devices

Input

Output

Network


The Instruction Set Architecture (ISA)

instruction set architecture

software

hardware

The interface description separating the software and hardware


The MIPS ISA

Instruction Categories Load/Store Computational Jump and Branch Floating Point

- coprocessor

Memory Management Special

R0 - R31

PCHI

LO

OP

OP

OP

rs rt rd sa funct

rs rt immediate

jump target

3 Instruction Formats: all 32 bits wide

Registers

Q: How many already familiar with MIPS ISA?


How Do the Pieces Fit Together?

I/O systemProcessor

Compiler

OperatingSystem

Applications

Digital Design

Circuit Design

Instruction Set Architecture

Firmware

Coordination of many levels of abstraction Under a rapidly changing set of forces Design, measurement, and evaluation

Memory system

Datapath & Control

network

CSE 411CSE 421

CSE 331 & 431

CSE 447 & 477

CSE 271 & 471

CSE 458


Review and Reminder Next week’s material

Introduction to MIPS assembler- Reading assignment - PH 2.1 through 2.4

Other reminders Install PCSpim on your laptop

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CSE331 W01.1 Irwin Fall 06 PSU CSE 331 Computer Organization and Design Fall 2006 Week 1 Section 1:...

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