CSE331 W10.1 Irwin&Li Fall 2006 PSU

CSE 331Computer Organization and

DesignFall 2006

Week 10Section 1: Mary Jane Irwin (www.cse.psu.edu/~mji)

Section 2: Feihui Li (www.cse.psu.edu/~feli )Course material on ANGEL: cms.psu.edu

[adapted from D. Patterson slides]

CSE331 W10.2 Irwin&Li Fall 2006 PSU

Head’s Up Last week’s material

Designing a MIPS single cycle datapath This week’s material

More on single cycle datapath design and exam review- Reading assignment –  PH: 5.4, B.8, C.1-C.2

Next week’s material Multicycle MIPS datapath implementation

- Reading assignment –  PH: 5.5, C.3

Reminders Final Exam is Tuesday, Dec 19, 4:40 to 6:30, 110 Business HW 7 will be due, ~ Nov 30 (by 11:55pm) Quiz 6 will be due, ~ Dec 4 (by 11:55pm)

Nov 27 is the late-drop deadline

CSE331 W10.3 Irwin&Li Fall 2006 PSU

Each MAS (microarchitectural specifications) included Pipeline and block diagrams Textual description of the theory of operation Unit inputs and outputs and protocols governing data

transfers Corner cases of the design that were especially tricky New circuits required for implementation Notes on testing and validation

The Pentium Chronicles, Colwell, pg. 82

CSE331 W10.4 Irwin&Li Fall 2006 PSU

Review: Creating a Datapath from the Parts Assemble the datapath elements, add control lines

as needed, and design the control path Fetch, decode and execute each instructions in

one clock cycle – single cycle design no datapath resource can be used more than once per

instruction, so some must be duplicated (e.g., why we have a separate Instruction Memory and Data Memory)

to share datapath elements between two different instruction classes need multiplexors at the input of the shared elements with control lines to do the selection

Cycle time is determined by length of the longest path

CSE331 W10.5 Irwin&Li Fall 2006 PSU

Review: A Simple MIPS Datapath Design

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovfzero

ALU controlRegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemReadSign

Extend16 32

MemtoRegALUSrc

ReadAddress

Instruction

InstructionMemory

Add

PC

4 Shiftleft 2

Add

PCSrc

CSE331 W10.6 Irwin&Li Fall 2006 PSU

Adding the Control Selecting the operations to perform (ALU, Register

File and Memory read/write) Controlling the flow of data (multiplexor inputs) Information comes from the 32 bits of the instruction

I-Type: op rs rt address offset31 25 20 15 0

R-type:31 25 20 15 5 0

op rs rt rd functshamt

10 Observations

op field always in bits 31-26

addr of two registers to be read are always specified by the rs and rt fields (bits 25-21 and 20-16)

base register for lw and sw always in rs (bits 25-21) addr. of register to be written is in one of two places – in rt

(bits 20-16) for lw; in rd (bits 15-11) for R-type instructions offset for beq, lw, and sw always in bits 15-0

CSE331 W10.7 Irwin&Li Fall 2006 PSU

(Almost) Complete Single Cycle Datapath

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr ALU

ovfzero

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

Register

File

Read Data 1

Read Data 2

RegWrite

SignExtend16 32

MemtoRegALUSrc

Shiftleft 2

Add

PCSrc

10

RegDst

0

1

10

1

0

ALUcontrol

ALUOpInstr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

CSE331 W10.8 Irwin&Li Fall 2006 PSU

ALU Control

ALU control input

Function

0000 and0001 or0010 xor0011 nor0110 add1110 subtract1111 set on less than

ALU's operation based on instruction type and function code

Notice that we are using different encodings than in the book

CSE331 W10.10 Irwin&Li Fall 2006 PSU

ALU Control, Con’t Controlling the ALU uses of multiple decoding levels

main control unit generates the ALUOp bits ALU control unit generates ALUcontrol bits

Instr op funct ALUOp action ALUcontrollw xxxxxx 00sw xxxxxx 00beq xxxxxx 01add 100000 10 add 0110subt 100010 10 subtract 1110and 100100 10 and 0000or 100101 10 or 0001xor 100110 10 xor 0010nor 100111 10 nor 0011slt 101010 10 slt 1111

add 0110add 0110subtract 1110

CSE331 W10.12 Irwin&Li Fall 2006 PSU

ALU Control Truth TableF5 F4 F3 F2 F1 F0 ALU

Op1

ALU Op0

ALU control3

ALU control2

ALU control1

ALU control0

X X X X X X 0 0 0 1 1 0X X X X X X 0 1 1 1 1 0X X 0 0 0 0 1 0 0 1 1 0X X 0 0 1 0 1 0 1 1 1 0X X 0 1 0 0 1 0 0 0 0 0X X 0 1 0 1 1 0 0 0 0 1X X 0 1 1 0 1 0 0 0 1 0X X 0 1 1 1 1 0 0 0 1 1X X 1 0 1 0 1 0 1 1 1 1

Four, 6-input truth tables

Our ALU m control input

Add/subt Mux control

CSE331 W10.13 Irwin&Li Fall 2006 PSU

ALU Control Logic From the truth table can design the ALU Control logicInstr[3]Instr[2]Instr[1]Instr[0]

ALUOp1

ALUOp0

ALUcontrol3

ALUcontrol2

ALUcontrol1

ALUcontrol0

CSE331 W10.14 Irwin&Li Fall 2006 PSU

(Almost) Complete Datapath with Control Unit

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

CSE331 W10.16 Irwin&Li Fall 2006 PSU

Main Control UnitInstr RegDst ALUSrc MemReg RegWr MemRd MemWr Branch ALUOp

R-type000000

lw100011

sw101011

beq000100

Completely determined by the instruction opcode field Note that a multiplexor whose control input is 0 has a

definite action, even if it is not used in performing the operation

CSE331 W10.17 Irwin&Li Fall 2006 PSU

R-type Instruction Data/Control Flow

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

zero

CSE331 W10.18 Irwin&Li Fall 2006 PSU

R-type Instruction Data/Control Flow

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

CSE331 W10.19 Irwin&Li Fall 2006 PSU

Store Word Instruction Data/Control Flow

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

CSE331 W10.20 Irwin&Li Fall 2006 PSU

Store Word Instruction Data/Control Flow

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

CSE331 W10.21 Irwin&Li Fall 2006 PSU

Load Word Instruction Data/Control Flow

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

CSE331 W10.22 Irwin&Li Fall 2006 PSU

Load Word Instruction Data/Control Flow

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

CSE331 W10.23 Irwin&Li Fall 2006 PSU

Branch Instruction Data/Control Flow

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

CSE331 W10.24 Irwin&Li Fall 2006 PSU

Branch Instruction Data/Control Flow

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

CSE331 W10.25 Irwin&Li Fall 2006 PSU

Main Control Unit

Instr RegDst ALUSrc MemReg RegWr MemRd MemWr Branch ALUOp

R-type000000

1 0 0 1 0 0 0 10

lw100011

0 1 1 1 1 0 0 00

sw101011

X 1 X 0 0 1 0 00

beq000100

X 0 X 0 0 0 1 01

Setting of the MemRd signal (for R-type, sw, beq) depends on the memory design

CSE331 W10.26 Irwin&Li Fall 2006 PSU

Control Unit Logic From the truth table can design the Main Control logic

Instr[31]Instr[30]Instr[29]Instr[28]Instr[27]Instr[26]

R-type lw sw beqRegDst

ALUSrc

MemtoReg

RegWrite

MemRead

MemWrite

Branch

ALUOp1

ALUOp0

CSE331 W10.27 Irwin&Li Fall 2006 PSU

Review: Handling Jump Operations Jump operation have to

replace the lower 28 bits of the PC with the lower 26 bits of the fetched instruction shifted left by 2 bits

ReadAddress

Instruction

InstructionMemory

Add

PC

4

Shiftleft 2

Jumpaddress

26

4

28

J-Type: op jump target address

31 0

CSE331 W10.28 Irwin&Li Fall 2006 PSU

Adding the Jump Operation

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

Shiftleft 2

0

1

Jump

32Instr[25-0]

26PC+4[31-28]

28

CSE331 W10.29 Irwin&Li Fall 2006 PSU

Adding the Jump Operation

ReadAddress

Instr[31-0]

InstructionMemory

Add

PC

4

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

ovf

zero

RegWrite

DataMemory

Address

Write Data

Read Data

MemWrite

MemRead

SignExtend16 32

MemtoReg

ALUSrc

Shiftleft 2

Add

PCSrc

RegDst

ALUcontrol

1

1

1

00

0

0

1

ALUOp

Instr[5-0]

Instr[15-0]

Instr[25-21]

Instr[20-16]

Instr[15 -11]

ControlUnit

Instr[31-26]

Branch

Shiftleft 2

0

1

Jump

32Instr[25-0]

26PC+4[31-28]

28

CSE331 W10.30 Irwin&Li Fall 2006 PSU

Main Control Unit

Instr RegDst ALUSrc MemReg RegWr MemRd MemWr Branch ALUOp Jump

R-type000000

1 0 0 1 0 0 0 10 0

lw100011

0 1 1 1 1 0 0 00 0

sw101011

X 1 X 0 0 1 0 00 0

beq000100

X 0 X 0 0 0 1 01 0

j000010

X X X 0 0 0 X XX 1

Setting of the MemRd signal (for R-type, sw, beq) depends on the memory design

CSE331 W10.31 Irwin&Li Fall 2006 PSU

Single Cycle Implementation Cycle Time

Unfortunately, though simple, the single cycle approach is not used because it is very slow

Clock cycle must have the same length for every instruction

What is the longest path (slowest instruction)?

CSE331 W10.33 Irwin&Li Fall 2006 PSU

Instruction Critical Paths

Instr. I Mem Reg Rd ALU Op D Mem Reg Wr TotalR-typeloadstorebeqjump

4 1 2 1 8

4 1 2 4 1 12

Calculate cycle time assuming negligible delays (for muxes, control unit, sign extend, PC access, shift left 2, wires) except:

Instruction and Data Memory (4 ns) ALU and adders (2 ns) Register File access (reads or writes) (1 ns)

4 1 2 4 11

4 1 2 7

4 4

CSE331 W10.34 Irwin&Li Fall 2006 PSU

Single Cycle Disadvantages & Advantages Uses the clock cycle inefficiently – the clock cycle

must be timed to accommodate the slowest instr especially problematic for more complex instructions like

floating point multiply

May be wasteful of area since some functional units (e.g., adders) must be duplicated since they can not be shared during a clock cycle

but It is simple and easy to understand

Clk

lw sw Waste

Cycle 1 Cycle 2

CSE331 W10.35 Irwin&Li Fall 2006 PSU

Where We are Headed Another approach

use a “smaller” cycle time have different instructions take different numbers of cycles a “multicycle” datapath

AddressRead Data

(Instr. or Data)

Memory

PC

Write Data

Read Addr 1

Read Addr 2

Write Addr

Register

File

Read Data 1

Read Data 2

ALU

Write Data

IRM

DR

AB A

LUou

t