Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 1

Question Paper Solution

UNIT I

1 . Explain the CMOS inverter transfer characteristics highlighting the regions of

operation of the MOS transistors.

(DEC 08/JAN 09,JUN-JUL 09,MAY-JUN 10,JUN-JUL 2011,) (12 marks)

Region A:

Vout=Vdd

Solving Vout= expression

In,p

Vin = 5

Vin = 4

Vin = 3

Vin = 0

Vin = 1

Vin = 2

NMOSPMOS

Vin = 0

Vin = 1

Vin = 2Vin = 3

Vin = 4

Vin = 4

Vin = 5

Vin = 2Vin = 3

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 2

2. Describe with neat diagrams, the P well fabrication process

(DEC JAN 09, MAY-JUN 10,JUN-JUL 11) (08 marks)

Fabrication steps involved

a) b)

c) Photoresist layer d) Strip resist

e) Liner oxide f) Deposition

g) N well implant h) Ion Implantation

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 3

i) Strip resist j)

k) l)

3. Explain the action of enhancement mode transistor for different values of Vgs and

Vds. (JUN- JUNL 09) (07 marks)

Modes of operation

The operation of a MOSFET can be separated into three different modes, depending on the

voltages at the terminals. In the following discussion, a simplified algebraic model is used that is

accurate only for old technology. Modern MOSFET characteristics require computer models that

have rather more complex behavior.

For an enhancement-mode, n-channel MOSFET, the three operational modes are:

Cutoff, subthreshold, or weak-inversion mode

When VGS < Vth:

According to the basic threshold model, the transistor is turned off, and there is no

conduction between drain and source. In reality, the Boltzmann distribution of electron energies

allows some of the more energetic electrons at the source to enter the channel and flow to the

drain, resulting in a subthreshold current that is an exponential function of gate–source voltage.

While the current between drain and source should ideally be zero when the transistor is being

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 4

used as a turned-off switch, there is a weak-inversion current, sometimes called subthreshold

leakage. In weak inversion the current varies exponentially with gate-to-source bias VGS as given

approximately by

,

where ID0 = current at VGS = Vth, the thermal voltage VT = kT / q and the slope factor n is

given by n = 1 + CD / COX,

with CD = capacitance of the depletion layer and COX = capacitance of the oxide layer. In a

long-channel device, there is no drain voltage dependence of the current once VDS > > VT,

Frequently, threshold voltage Vth for this mode is defined as the gate voltage at which a selected

value of current ID0 occurs, for example, ID0 = 1 μA, which may not be the same Vth-value used

in the equations for the following modes.Some micropower analog circuits are designed to take

advantage of subthreshold conduction. By working in the weak-inversion region, the MOSFETs

in these circuits deliver the highest possible transconductance-to-current ratio, namely: gm / ID

= 1 / (nVT), almost that of a bipolar transistor

4. How is a NMOS transistor fabricated? Explain with neat sketches.

( JUN-JUL 09,JUN 12) (10 Marks)

Basic Fabrication Steps

1) Growing silicon dioxide to serve as an insulator between layers deposited on the surface of the

silicon wafer. Doping the silicon substrate with acceptor and donor atoms to create p- and n-type

diffusions that form isolating PN junctions and one plate of the MOS capacitor. Depositing

material on the wafer to create masks, wires and the other plate of the MOS capacitor. Etching

deposited materials to create the appropriate geometric patterns.

2) Growing Silicon Dioxide: Thermal oxidation creates high quality film used as mask during

diffusion, insulator and gate dielectric.

3) Physical vapor deposition to deposit metals (Al, Cu). Chemical vapor deposition to

depositSiO2, single-crystal (epitaxial) and polycrystalline (poly) Si.

4) Photo resist is spun onto wafer then exposed with UV light, X-rays or electron beam (no

mask). Develop to remove exposed resist. Wet etching Dry etching isotropic anisotropic Remove

photo resist mask Performance note: minimum feature size often determined by photo resist and

etching process

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 5

5. What is a tristate inverter? Explain ( JUN-JUL 09) (03 marks)

Tristate buffer produces Z when not enabled. Tristate inverter produces restored output

and Violates conduction complement rule because we want a Z output.

6. Distingush between enhancement and depletion mode transistors.

(DEC-JAN 10) (05 marks)

Depletion

• The channel Pre exits.

• It can be operated in depletion mode As well as enhancement mode.

• Drain current flows on application of Drain to source voltage at Vgs =0V.

• Ex. JFET, MOSFET.

Enhancement

• Channel is physically absent & is induced by applying gate voltage above the threshold

voltage.

EN A Y

0 0 Z

0 1 Z

1 0 0

1 1 1

A

Y

EN

A

Y

EN = 0

Y = 'Z'

Y

EN = 1

Y = A

A

EN

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 6

• Can be operated in only enhancement mode.

• Practically no current flows on applying Vds at Vgs =0V. Current flows only when Vgs

is above the threshold level.

• Ex. MOSFET.

Enhancement Mode Transistor Depletion mode transistor

7. Explain with diagrams, the main steps in twin tub process.

(DEC-JAN 10) (10 marks)

To create a n well:

Diffusion

Heat wafer in Arsenic gas chamber until diffusion occurs.

Ion Implantation

Arsenic or phosphorous are implanted in window.

A thin layer of oxide is deposited.

A thin layer of polysilicon is deposited using Chemical Vapor Deposition (CVD) .

Remove oxide layer using acid.

Dope open area using Ion implantation or diffusion

n well

SiO2

p substraten well

p substraten well

n+n+ n+p+p+p+

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 7

8. Compare CMOS and Bipolar technologies.

(DEC-JAN 10,MAY JUN 10) (05 marks)

Characteristics of CMOS Technology

1. Lower static power dissipation

2. Higher noise margins

3. Higher packing density – lower manufacturing cost per device

4. High yield with large integrated complex functions

5. High input impedance (low drive current)

6. High delay sensitivity to load (fan-out limitations)

7. Low output drive current (issue when driving large capacitive loads)

8. Low Tran conductance, where Tran conductance, gm Vin

9. Bi-directional capability (drain & source are interchangeable)

10. A near ideal switching device

Characteristics of BiCMOS Technology

1. BiCMOS is inherently robust with respect to temperature and process variations,

resulting in less variability in final electrical parameters, resulting in higher yield, an

important economic consideration.

2. Large circuits can impose severe performance penalties due to simultaneously switching

noise, internal clock skews and high nodal capacitances in critical paths.

3. BiCMOS can take advantage of any advances in CMOS and/or bipolar technology,

greatly accelerating the learning curve normally associated with new technologies.

p substrate

Metal

Thick field oxide

n well

n+n+ n+p+p+p+

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 8

UNIT 2

1. Discuss the effect of channel modulation on the performance of an nMOS transistor

(DEC JAN 09) (05 marks)

2. List the cplor, stick encoding, mask layout encoding and CIF layers for the

following layers used in VLSI technology: (DEC JAN 09)

i) n diffusion ii) polysilicon iii) Metal1 iv) Impact (04 marks)

Polysilicon (gates) = red, Doped n+ / p+ (active) = green, N-well either by ----- (dashed line) or

yellow, Metal1 = blue, Metal 2= gray, Contacts = Black X

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 9

3. Write the stick diagram for a parity generator using nMOS logic.

(DEC JAN 09) (08 marks)

4. Write the layout for the logic expression Y= A+BC using CMOS logic (08 marks)

(DEC JAN 09)

5. Discuss the limits of scaling on (DEC JAN 09)

i) Supply voltage due to noise ii) sub threshold current iii) interconnects.

( 10 marks)

In our discussions we will consider 2 scaling factors, α and β. 1/ β is the scaling factor for

VDD and oxide thickness D. 1/ α is scaling factor for all other linear dimensions. We will

assume electric field is kept constant. Resistance of track R ~ L / wt. R (scaled) ~ (L / α) / ( (w/

α )* (t /α)). R(scaled) = αR . Therefore resistance increases with scaling

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 10

6. Explain the transmission gate operation. (MAY JUN 10) (04 marks)

7. Draw lambda based design rules for double metal CMOS process for layers and

transistors (MAY JUN 10) (08 marks)

Lambda Based Design Rules

1. Design rules based on single parameter, λ

2. Simple for the designer

3. Wide acceptance

4. Provide feature size independent way of setting out mask

5. If design rules are obeyed, masks will produce working circuits

6. Minimum feature size is defined as 2 λ

7. Used to preserve topological features on a chip

8. Prevents shorting, opens, contacts from slipping out of area to be contacted

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 11

8. Draw the circuit and stick diagram for NAND gate (MAY JUN 10) (04 marks)

9. With a neat diagram, explain lambda rules for contact cuts and vias. (DEC08) `

(12 marks)

1. Design rules based on single parameter, λ

2. Simple for the designer

3. Wide acceptance

4. Provide feature size independent way of setting out mask

5. If design rules are obeyed, masks will produce working circuits

6. Minimum feature size is defined as 2 λ

7. Used to preserve topological features on a chip

8. Prevents shorting, opens, contacts from slipping out of area to be contacted

10. Draw the stick diagram for the NMOS implementation of the Boolean expression

Y'=AB+C. (DEC08) ` (08 marks)

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 12

11. What is noise margin? Obtain the values of VIL,VIH, VOL,and VOH .

( JUN-JUL 09) (06 marks)

12. Draw the schematic and stick diagram of CMOS 2 input NAND.

( JUN-JUL 09) (06 marks)

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 13

13. Implement the pass transistor logic circuit for the expression Y= A+BC

( DEC 10) (08 marks)

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 14

UNIT III

1. Realize a 2 input NAND gate for a clocked CMOS logic and also for CMOS domino

logic (DEC JAN 09, JUN JUL 11,DEC 11) (10 marks)

Clocked CMOS logic CMOS DOMINO LOGIC

2. Explain different types of pseudo – NMOS logic (MAY JUN 10, DEC10)

(07 marks)

Pseudo NMOS Logic: In the old days, nMOS processes had no pMOS. Instead, use pull-up

transistor that is always ON. In CMOS, use a pMOS that is always ON

PMOS acts as a load device,since Gate is grounded and it also works as a constannt current

source.( Because source is connected to Vdd). Since Gate is grounded it is always Biased

Logic is controlled by NMOS which acts as a switch. If switch is open ,Vo= VDD and

therefore Vout= Voh. If switch is closed ,Vo= low(0) and therefore Vout= Vol {Vout can

a

M2

VDD

b

0

b

M1

0

Cout

a

A

W

B C

X Y Z

domino AND

dynamic

NAND

static

inverter

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 15

ever be low} because PMOS is always ON. For a device to give good gain ,the ratio of ßn/ ß

Adding a single pFET to otherwise nFET-only circuit produces a logic family called Pseudo-

nMOS. It uses fewer FETs because only the nFET logic block is needed to create the logic.

For N inputs, a pseudo-nMOS logic gate requires (N + 1) FETs. In conventional CMOS, the

pFET group is added to reduce the DC power dissipation. Standard N-input CMOS gates use

2N FETs. If the nFET switch is closed, then the array acts as a pull-down device that tries to

pull down to ground. The disadvantage is that, as pFET is always biased ON, VOL can never

achieve the ideal value of 0V.

Advantages: Reduces the number of transistors and the area

Disadvantages: There is static power dissipation, when NMOS is ON because PMOS is

always turned ON and current flows in gate structure.

3. Explain CMOS domino logic and derive the evaluation voltage equation

(MAY JUN 10) (08 marks)

Domino Logic: Domino logic is a CMOS logic style obtained by adding a static inverter to the

output of the basic dynamic gate circuit. The resulting structure is shown in figure. The recharge

and evaluate events still occur, but now it is the capacitor Cx between the dynamic stage and the

inverter that is affected. A clock value of = 0 defines the precharge.

During this time, Cx is charge to a voltage Vx = VDD which forces the output voltage to

Vout = 0 V. Inputs are valid during the evaluation interval when = 1. If Cx holds its

charge, Vx remains high and Vout = 0 V indicate a logic 0 output. If Cx discharges, then Vx

tends to zero and Vout tends to Vdd. This corresponds to a logic 1 output.

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 16

Domino logic gate outputs are non-inverting because of the inclusion of the inverter at the

output stage. This makes logic design using only domino gates somewhat tricky since the NOT

operation is required for a complete set of logic operations.

Advantages: 1. Domino logic is attractive for high-speed circuits

2. 1.5 – 2x faster than static CMOS

3. Widely used in high-performance microprocessors

Disadvantages: Leakage, Charge sharing, Noise

4. Explain 2 inputs X-NOR gate in pass transistor logic

(MAY JUN 10) (05 marks)

• The complexity of CMOS pass-gate logic can be reduced by dropping the PMOS

transistors and using only NMOS pass transistors (named CPL)

– In this case, CMOS inverters (or other means) must be used periodically to

recover the full VDD level since the NMOS pass transistors will provide a VOH

• The CPL circuit requires complementary inputs and generates complementary outputs to

pass on to the next CPL stage

• Pass-transistor logic gate can implement Boolean functions NOR, XOR, NAND, AND,

and OR depending upon the P1-P4 inputs, as shown below

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 17

5. Discuss the merits and demerits of the following CMOS logic structures with a two

input NAND gate realization as an example

(DEC08, JUN JUL 11, JUN12) (15 marks)

i) Complementary CMOS logic ii) PseudoNMOS logic iii) Dynamic CMOS logic

Pseudo NMOS Logic: In the old days, nMOS processes had no pMOS. Instead, use pull-up

transistor that is always ON. In CMOS, use a pMOS that is always ON

PMOS acts as a load device,since Gate is grounded and it also works as a constannt current

source.( Because source is connected to Vdd). Since Gate is grounded it is always Biased Logic

is controlled by NMOS which acts as a switch.If switch is open ,Vo= VDD and therefore Vout=

Voh.If switch is closed ,Vo= low(0) and therefore Vout= Vol {Vout can never be low} because

PMOS is always ON. The ratio is made consistent by keeping the ratio of transistors sizes

standard,however if there is variation in transistor sizes,ß will vary.

Working: The clock drives both P and N transistors, which control and synchronise the

operation. When clk=0, the circuit is in Precharge mode and P is ON and N is OFF. Therefore

conducting path between Vdd and Vo is established and hence Vo=Vdd Capacitor is charged.

Since N is OFF ,no effect of inputs are there. When clk=1, the circuit is in evaluation mode i.e

P is OFF and N is ON Now the inputs control the switching of NMOS. The discharging action of

capacitor takes place and Vo=0(GND). Nonratioed - sizing of the devices is not important for

proper functioning (only for performance) Faster switching speeds reduced load capacitance due

to lower number of transistors per gate.

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 18

6. Explain the operation of CMOS Transmission gate

(DEC08) (05 marks)

Transmission Logic: N-Channel MOS Transistors P-Channel MOS Transistors

pass a 0 better than a 1 pass a 1 better than a 0

This is the reason that N-Channel transistors are used in the pull-down network and P-

Channel in the pull-up network of a CMOS gate. Otherwise the noise margin would be

significantly reduced. A transmission gate is a essentially a switch that connects two points.

In order to pass 0’s and 1’s equally well, a pair of transistors (one N-Channel and one P-

Channel) are used as shown below. When s = 1 the two transistors conduct and connect x and

y. The top transistor passes x when it is 1 and the bottom transistor passes x when it is 0.

When s = 0 the two transistor are cut off disconnecting x and y. Transmission gates pass both

0 and 1 well.

Precharge Evaluate

Y

Precharge

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 19

UNIT IV

1. Narrate the steps involved in calculating the sheet resistance of: (06 marks)

i) transisitor channels ii) nMOS inverter iii) CMOS inverter (DEC JAN 09)

Transistor channel

CMOS INVERTER

• Pull-down delay = Rpd x 2 •Cg Pull-up delay = Rpu x 2•Cg

• Asymmetry in rise and fall due to resistance difference between pull-up and pull-down

(factor of 2.5) (due to mobilities of carriers)Delay through a pair of CMOS inverters is

therefore 7 τReduce resistance of pull - up by increasing channel width ( typically by a

factor of 2.5)

• Note that increasing channel width also increases the capacitance

• The overall delay (after increasing channel width by 2.5) will be the same 7 τ

2. Derive expressions for rise time and fall time for 1:1 CMOS inverter (06 marks)

CMOS Inverter Delay

• Pull-down delay = Rpd x 2 •Cg

• Pull-up delay = Rpu x 2•Cg

• Asymmetry in rise and fall due to resistance difference between pull-up and pull-down

(factor of 2.5) (due to mobilities of carriers)

• Delay through a pair of inverters is 2 τ (fall time) + 5 τ (rise time)

• Delay through a pair of CMOS inverters is therefore 7 τ

CMOS Inverter Delay

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 20

• Asymmetry can be improved by reducing resistance of pull - up

• Reduce resistance of pull - up by increasing channel width ( typically by a factor of 2.5)

• Note that increasing channel width also increases the capacitance

• The overall delay (after increasing channel width by 2.5) will be the same 7 τ

CMOS Inverter Rise and Fall Time Estimation

• Tf ~ 3CL / βVDD

• Τr ~ 3CL / βVDD

• (Derivations for the above are in Pucknell and Eshraghian Pages 105 - 107)

• So, τ r/ τf = βn/βp

Given that (due to mobilities) βn = 2.5 βp, rise time is slower by a factor of 2.5 when

using minimum dimensions of n and p transistors

3. Define sheet resistance and standard unit of capacitance Cg

( JUN JUL09) (06 marks)

Sheet Resistance

• Resistance of a square slab of material

• RAB = ρL/A

• => R = ρL/t*W

• Let L = W (square slab)

• => RAB = ρ/t = Rs ohm / square

4. Obtain the expression for total delay for N stages of nmos and cmos inverters in

terms of width factor

( JUN JUL 09) ( 08 marks)

. Delay is one of the most important properties of a logic gate—the majority of chip designs are

limited more by speed than by area. An analysis of logic gate delay not only tells us how to

compute the speed of a gate, it also points to parasitics that must be controlled during layout

design to minimize delay. Later, in Section 3.3.7, we will apply what we have learned from delay

analysis to the design of logic gate layouts. There are two interesting but different measures of

combinational logic effort:

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 21

• Delay is generally used to mean the time it takes for a gate’s output to arrive at 50% of its final

value.

• Transition time is generally used to mean the time it takes for a gate to arrive at 10% (for a

logic 0) or 90% (for a logic 1) of its final value; both fall time tf and rise time tr are transition

times.

We will analyze delay and transition time on the simple inverter circuit shown in Figure 3-16;

our analysis easily extends to more complex gates as well as more complex loads. We will

assume that the inverter’s input changes voltage instantaneously; since the input signal to a logic

gate is always supplied by another gate, that assumption is optimistic, but it simplifies analysis

without completely misleading us.

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 22

UNIT V

1. Describe switch and CMOS logic implementtaion for two input X-Or gate

(DEC 08, MAY JUN 10) (08 marks)

Switch Logic:

• Based on pass transistors or transmission gates

• Fast for small arrays

• No static current from supply lines

• Logic based on relay logic

• Easy implement basic AND / OR connections

• Pass transistor logic levels get degraded by Vt effects

• Transmission gates do not suffer from Vt effects but

– more complex

– more area

– potential fabrication problems

– requires true and complement of gate signal

• No pass transistor gate may be driven through one or more pass transistors

– Logic 1 degraded for n-type pass

– Logic 0 degraded for p-type pass

– Transmission gates - good logic levels

– Loss of logic level 1 if the gate of a pass transistor is driven from another pass

transistor

CMOS ExOR Gates

– pull-up resistance effect aggravated by number of transistors connected in series

(p-type) -> rise and fall time asymmetries increased

– shift in transfer function -> noise immunity decreased

– will need L:W ratio adjustments

2. Design a parity generator with the following specifications and draw the stick

diagram for one basic cell.

(DEC 08, JUN JUL 09, JUN JUL 11) (08 marks)

Parity Generator Cell: The cell is implemented mainly in NMOS pass logic. From a circuit

diagram, you will generate a suitable stick diagram, simulate it using SPICE and produce full

custom layout.Parity bits are extra signals which are added to a data word to enable error

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 23

checking. There are two types of Parity - even and odd. An even parity generator will produce a

logic 1 at its output if the data

word contains an odd number of

ones.

The table shows the parity

generator outputs for various 8-

bit data words.

This shows the block diagram of

parity generator circuit. The inputs are shown as which may be a 16 bit or 32 bit number. If P=1

, even number of 1’s are at the input. If P=0, odd number of 1’s are at the input

i.e If Ai=1, parity is changed else if Ai =0 , parity is unchanged

3. Discuss the architectural issues to be followed in the design of a VLSI subsystem

( DEC JAN 09,) (06 marks)

The different architectural issues are:

Define the requirement

Partition into appropriate subsystems

Communication path should be done properly between sub system

The floor plan of the system to be done

If necessary duplication has to be dine

Proper diagram of leaf cells should be drawn

Convert the cell into layout

DATAWORD EVEN O/P ODD O/P

00000000 0 1

10000000 1 0

00010000 1 0

11101001 1 0

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 24

Check for each cell’s design

Simulate the performance of cell/subsystem

4. Design 4:1 MUX using transmission gates

( DEC JAN 09,JUN 12, JUN JUL 09, MAY JUN 10) (06 marks)

MUX and DEMUX circuits using a photo gate transistor having a pair of thin film electrodes

respectively serving as emission and collector electrodes. When photons with at least critical

energy are irradiated onto the emission electrode, electrons are emitted from the emission

electrode, so that the associated photo gate transistor can carry out a gating operation. The MUX

circuit divides a plurality of electrical signals in a time division manner so that the transmission

of those signals can be carried out through a single transmission line. The DEMUX circuit

recovers an original signal from signals transmitted in a time division manner via a single

transmission line. Input signals are received to emission electrodes while being limited in voltage

level by input resistor pairs. An optical source irradiates photons to an emission electrode in sync

with the application of an input signal. By the irradiation of photons, the emission electrode

emits electrons which are transmitted to a collector electrode. As a result, output voltage is

output. The output voltage corresponds to the quantity of current of the transmitted signal which

is determined by an output resistor in accordance with voltage from a voltage source and the

intensity of the irradiated photons.

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 25

5. Explain the 4X4 cross bar switch operation. Mention the salient features of

subsystem design process.

( MAY JUN 10,JUN JUL 11) (08 marks)

6. What are the properties of NMOs and PMOs switches? ( JUN JUL 09)

These are the devices that pass the signal between drain and source. Usually Pass transistors

are made of NMOS rather that PMOS because of mobility being more in NMOS. If only N

type transistor is used then it is called as Pass Transistor and it is in NMOS design style. If

Both PMOS and NMOS are used then it is called as Transmission Gate and it is in CMOS

design style. Pass-transistor circuits are formed by dropping the PMOS transistors and using

only NMOS pass transistors. In this case, CMOS inverters (or other means) must be used

periodically to recover the full VDD level since the NMOS pass transistors will provide a

VOH of VDD – VTn in some cases The pass transistor circuit requires complementary inputs

and generates complementary outputs to pass on to the next stage. When s = 1 the two

transistors conduct and connect x and y The top transistor passes x when it is 1 and the

bottom transistor passes x when it is 0 When s = 0 the two transistor are cut off disconnecting

x and y Pass transistors produce degraded outputs. Transmission gates pass both 0 and 1 well

7. Design bus arbitration logic for n line bus. ( DEC 11) (10 marks)

A 4-bit priority encoder (also sometimes called a priority decoder). This circuit basically

converts the 4-bit input into a binary representation.

The circuit operation is simple. Each output is driven by an OR-gate which is connected to the

NAND-INV outputs of the corresponding input lines. The NAND gate of each stages receives its

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 26

input bit, as well as the NAND gate outputs of all higher priority stages. This structure implies

that an active input on stage n effectively disables all lower stages n-1A common use of priority

encoders is for interrupt controllers, to select the most critical out of multiple interrupt requests.

Due to electrical reasons (open collector outputs), priority encoders with active-low inputs are

also often used in practice.

Priority Encoder (8:3 bits)

Circuit Description

An 8-bit priority encoder. This circuit basically converts a one-hot encoding into a binary

representation. If input n is active, all lower inputs (n-1 .. 0) are ignored. Please read the

description of the 4:2 encoder for an explanation.

x7 x6 x5 x4 x3 x2 x1 x0 y2 y1 y0

----------------------------------

1 X X X X X X X 1 1 1

0 1 X X X X X X 1 1 0

0 0 1 X X X X X 1 0 1

0 0 0 1 X X X X 1 0 0

0 0 0 0 1 X X X 0 1 1

0 0 0 0 0 1 X X 0 1 0

0 0 0 0 0 0 1 X 0 0 1

0 0 0 0 0 0 0 X 0 0 0

8. What are the scaling factors for Gate capacitance, Max frequency, current density,

power speed product ? ( JUN JUL 09) (08 marks)

The only constant in VLSI is constant change Feature size shrinks by 30% every 2-3 years.

Transistors become cheaper. Transistors become faster. Wires do not improve (and may get

worse)

Scale factor S Typically

2S

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 27

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 28

UNIT VI

1. Discuss the timing constraints for both flipflops and latches (DEC JAN 09)

(08 marks)

2. Discuss Baugh- Worley method used for two’s complement multiplication

(DEC JAN 09) (12 marks)

FA

FA

FA

FA

y0 y1 y2

y3

y4

y5

S

Ci-1

Ci-1

Ci-1

Ci

Ci

Ci

FA

y0 y1 y2

FA

y3 y4 y5

FA

FA

CC S

Ci-1

Ci-1

Ci-1

Ci

Ci

Ci

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 29

3. Explain the design steps for a 4 bit adder. (06

marks)

A Generic Digital Processor

4. How can 4 bit ALU architecture be used to implement an adder

( MAY JUN 10, JUN JUL 09) (06 marks)

Bit-Sliced Design

MEM ORY

DATAPATH

CONTROL

INP

UT

-OU

TP

UT

Bit 3

Bit 2

Bit 1

Bit 0

Reg

iste

r

Ad

der

Sh

ifte

r

Mu

ltip

lexe

r

Control

Dat

a-In

Dat

a-O

ut

Tile identical processing elements

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 30

Complimentary Static CMOS Full Adder

Inversion Property

Bit 3

Bit 2

Bit 1

Bit 0

Reg

iste

r

Ad

der

Sh

ifte

r

Mu

ltip

lexer

Control

Data

-In

Da

ta-O

ut

Tile identical processing elements

VDD

VDD

VDD

VDD

A B

Ci

S

Co

X

B

A

Ci A

BBA

Ci

A B Ci

Ci

B

A

Ci

A

B

BA

28 Transistors

A B

S

CoCi FA

A B

S

CoCi FA

S A B Ci

S A B Ci

=

Co

A B Ci

Co

A B Ci

=

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 31

Minimize Critical Path by Reducing Inverting Stages

5. Draw the basic form of twp phase clock generator and explain.

( JUN JUL 09) (07 marks)

Dynamic Registers with Two Phase Clocks

Dynamic register with pass gates and two phase clocking is shown. Clocks phi1 and phi2

are non-overlapping. When phi1 is high & phi2 is zero, 1st pass gate is closed and D data charges

gate capacitance C1 of 1st inverter 2

nd pass gate is open trapping prior charge on C2. When phi1

is low and phi2 is high, 1st pass gate opens trapping D data on C1 2

nd pass gate closes allowing

A0 B0

S0

Co,0Ci,0

A1 B1

S1

Co,1

A2 B2

S2

Co,2 Co,3FA’ FA’ FA’ FA’

A3 B3

S3

Odd CellEven Cell

Exploit Inversion Property

Note: need 2 different types of cells

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 32

C2 to charge with inverted D data. If clock skew or sloppy rise/fall time clock buffers cause

overlap of phi1 and phi2 clocks, Both pass gates can be closed at the same time causing mixing

of old and new data and therefore loss of data integrity!

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 33

UNIT VII

1. Explain the dynamic 2 bit shift register circuit using NMOS and CMOS logic

(DEC08) (10 marks)

2. Discuss the various system timing constraints. (DEC08) (05 marks)

3. Explain the transistor Dynamic RAM cell (DEC08) (10 marks)

DRAM is usually arranged in a square array of one capacitor and transistor per data bit storage

cell. The illustrations to the right show a simple example with only 4 by 4 cells (Modern DRAM

matrix are many thousands of cells in height and width). The long horizontal lines connecting

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 34

each row are known as Word Lines. Each column of cells is actually composed of two bit lines,

each one connected to every other storage cell in the column. (The illustration to the right does

not include this important detail). This is an example of positive feedback, and the arrangement

is only stable after one bit line is high and one bit line is low.

4. Explain the working of 3TD RAM cell (DEC JAN 09) (08 marks)

Dynamic random-access memory (DRAM) is a type of random access memory that stores

each bit of data in a separate capacitor within an integrated circuit. The capacitor can be either

charged or discharged; these two states are taken to represent the two values of a bit,

conventionally called 0 and 1. Since capacitors leak charge, the information eventually fades

unless the capacitor charge is refreshedperiodically. Because of this refresh requirement, it is

a dynamic memory as opposed to SRAM and other static memory.

The main memory (the "RAM") in personal computers is dynamic RAM (DRAM). It is the

RAM in laptop and workstation computers as well as some of the RAM of video game consoles.

The advantage of DRAM is its structural simplicity: only one transistor and a capacitor are

required per bit, compared to four or six transistors in SRAM. This allows DRAM to reach very

high densities. Unlike flash memory, DRAM is volatile memory (cf. non-volatile memory), since

it loses its data quickly when power is removed. The transistors and capacitors used are

extremely small; billions can fit on a single memory chip.

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 35

5 Explain the read and write operations in dynamic memory cell

( MAY JUN 10) (06 marks)

6. What is structured design process? Explain.( JUN JUL 09) (08 marks)

Structured VLSI design is a modular methodology originated by Carver Mead and Lynn Conway

for saving microchip area by minimizing the interconnect fabrics area. This is obtained by

repetitive arrangement of rectangular macro blocks which can be interconnected using wiring by

abutment. An example is partitioning the layout of an adder into a row of equal bit slices cells. In

complex designs this structuring may be achieved by hierarchical nesting. Structured VLSI

design had been popular in the early 1980s, but lost its popularity later because of the advent of

placement and routing tools wasting a lot of area by routing, which is tolerated because of the

progress of Moore's Law.As microprocessors become more complex due to technology scaling,

microprocessor designers have encountered several challenges which force them to think beyond

the design plane, and look ahead to post-silicon:

Power usage/Heat dissipation – As threshold voltages have ceased to scale with advancing

process technology, dynamic power dissipation has not scaled proportionally. This has given

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 36

rise to techniques such as dynamic voltage and frequency scaling (DVFS) to minimize

overall power.

Process variation – As lithography techniques tend closer to the fundamental laws of optics,

achieving high accuracy in doping concentrations and etched wires is becoming more

difficult and prone to errors due to variation.

Stricter design rules – Due to lithography and etch issues with scaling, design rules for layout

have gotten much more stringent. The overhead for custom design is now reaching a tipping

point, with many design houses now opting to switch to electronic design automation (EDA)

tools to automate their design process.

Timing/design closure – As clock frequencies tend to scale up, designers are finding it more

difficult to distribute and maintain low clock skewbetween these high frequency clocks

across the entire chip. This has led to a rising interest in multicore and multiprocessor

architectures, since an overall speedup can be obtained by lowering the clock frequency and

distributing processing.

First-pass success – As die sizes shrink (due to scaling), and wafer sizes go up (to lower

manufacturing costs), the number of dies per wafer increases, and the complexity of making

suitable photomasks goes up rapidly. Several design philosophies have been developed to aid

this new design flow, including design for manufacturing (DFM), design for test (DFT), and

many others.

7. What are the system timing considerations? ( JUN JUL 09) ( 06 marks)

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 37

UNIT VIII

1. Write short note on Level sensitive scan (DEC 08) (05 marks)

a. Level sensitive scan

Scan-Path Register Scan-based Test —Operation

Scan-Path Testing

SCANIN

IN

LOAD

SCAN PHI2 PHI1

KEEP

OUT

SCANOUT

Test

ScanInTest

Latch

In0

Out0

Test Test

Latch

In1

Out1

Test Test

Latch

In2

Out2

Test Test

Latch

In3

Out3

ScanOut

Test

1

2

N cycles 1 cycleevaluationscan-in

N cyclesscan-out

Logic

Combinational

Logic

Combinational

Register

Register

OutIn

ScanOutScanIn

A B

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 38

b. Built in self test

RAPIDLY BECOMING MORE IMPORTANT WITH INCREASING CHIP-COMPLEXITY AND LARGER

MODULES

MEMORY SELF-TEST

2. Narrate the meaning of controllability and observability in VLSI chip testing

(Dec Jan 09) (08 marks)

Controlability: The input buffer usually has very low Vinv to accommodate TTL logic levels

(0.8V, 2.0V). Note that the input pad and buffer present a capacitive load to the outside world.

This is good for preventing any DC load current, but it is bad because large voltages may build

up on the input pad from static electricity until the chip circuitry is damaged. Voltages up to

1000V can be put on the input pin merely by touching an unprotected input with your finger.

Also, the peak electrostatic discharge (ESD) current can be as much as an amp.

Observability: Some way must be provided to get signals to and from the chip. The usual method

is to solder very thin wires directly to the chip. In order to make good electrical contact between

the chip circuitry and the bonding wires, a metal bonding pad must be designed into the chip

REG[5]

REG[4]

REG[3]REG[2]

REG[0]REG[1]

+

COMP

OUT

SCANIN

COMPIN

SCANOUT

A B

(Sub)-Circuit

Under

Test

Stimulus Generator Response Analyzer

Test Controller

FSMMemory Signature

AnalysisUnder Test

data

address &

R/W control

-in

data-out

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 39

circuitry. The bonding pads are usually about 0.1mm on a side and spaced about 0.1mm between

pads. These sizes and spacing are about the same for all processes regardless of line width since

it is extremely difficult to make physical solder joints on pads that are any smaller.

3. Explain different types of I/O pads (May JUN 10) (06 marks)

I/O Pads:

Some way must be provided to get signals to and from the chip. These sizes and spacing are

about the same for all processes regardless of line width since it is extremely difficult to make

physical solder joints on pads that are any smaller. A cutaway of a typical wire bonded package

is shown.

An alternate method of bonding to the pads is to use solder bumps. Pad frames can be designed

for any size chip and any desired number of pads. A pad frame has been laid out in our 0.6 μm

pad library which looks like the following.

All the pads are bidirectional Input/Output pads except for the VDD and GND. This pad frame

has 2 power/ground pads and 38 signal pads for a total of 40 pads. All power and ground lines in

your design must be connected to the VDD and GND pads.

The input buffer usually has very low V inv to accommodate TTL logic levels (0.8V, 2.0V).

Input pads must be provided with special circuitry to protect the internal circuitry from these

large voltages and currents.

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 40

4. Write a note on testability and testing (May JUN 10) (10 marks)

Test structures similar to those described in the following subsections are usually employed by

the manufacturer. It is important that these test structures be understood by the user for their

value in validating the level of expected quality and reliability of the MMIC. The technology

characterization vehicle (TCV) is a structure that can be used to characterize a technology’s

susceptibility to intrinsic reliability failure mechanisms such as electromigration, interlayer

dielectric integrity, and metal diffusion. The accelerated life tests are usually performed on

packaged TCV structures.

Testability

Testability is the ability to measure defined parameters associated with the MMIC

fabrication process. These measurements can be used to validate the MMIC design, to evaluate

the technology in terms of reliability. The following subparagraphs give information on the

levels of testability and typical parameters measured on test structures and MMIC devices.

Wafer-Level Testability

Usually dc on-wafer testing is performed on the test structures and MMICs with

traceability and wafer mapping included in the measurement documentation. These tests are

usually done with an autoprobing instrument. The tests are a key screening procedure and are

used to ensure that all parts delivered have fully dc functional FETs, resistors and capacitors, and

that the parameters for these components are within standard or desired specifications. RF

measurements are made after both front side and backside processing is complete but prior to

chip separation and normally under the same bias conditions used in the application of the

device. The technique generally used in RF probing is to place pads or ―footprints‖ for signal

connection at each RF port. This problem can be minimized by pulsing the dc bias to the device,

but it is still a difficult measurement.

5. Explain the ground rubs for a system design (May JUN 10) (10 marks)

Ground Rules for design:

• Optimization requirements for high performance

• Time-to-market competition

• Cost

Physical Design

Converts a circuit description into a geometric description.

– This description is used for fabrication of the chip.

Fundamentals of CMOS VLSI 10EC056

SJBIT, Dept. of ECE Page 41

• Basic steps in the physical design cycle:

1. Partitioning

2. Floor planning and placement

3. Routing

4. Compaction