EE365 Adv. Digital Circuit Design Clarkson University Lecture #4 Transistor Level Logic CMOS vs....

EE365Adv. Digital Circuit Design

Clarkson University

Lecture #4

Transistor Level Logic

CMOS vs. TTL

Topics

• CMOS Logic Devices

• Bipolar Logic Devices

Rissacher EE365Lect #4

MOS Transistors

NMOS

PMOS

Voltage-controlled resistance


Switch Model


CMOS Inverter


Alternate transistor symbols


CMOS Gate Characteristics • No DC current flow into MOS gate terminal

– However gate has capacitance ==> current required for switching (CV2f power)

• No current in output structure, except during switching– Both transistors partially on– Power consumption related

to frequency– Slow input-signal rise times

==> more power• Symmetric output structure

==> equally strong drive in LOW and HIGH states


CMOS Gate Operation• Java applet showing CMOS gates

– visit:

tech-www.informatik.uni-hamburg.de/applets/cmos/

– illustrates gate operation, including power drain during switching

– Link is on class website


Pull-up / Pull-down Model• Typical CMOS gate can be viewed as

consisting of two parts– pull-up network and pull-down network

VDD

ABC

Pull-up

GND

output

ABC

Pull-down


Pull-up / Pull-down Model

• High level inputs to the PDN cause switches to close

• If there is a closed switch path thru PDN, then output is low

• Low level inputs to the PUN cause switches to close

• If there is a closed switch path thru PUN, then output is high



A

B C

A and ( B or C)

Since hign level signals on the inputs cause the PDN toclose switches, we get aBoolean expression for theinput which creates a closedpath thru PDN

If a closed path exists in PDN, then the output is pulled low.Thus the logic function realized is the complement (inverted)version of the Boolean expression.

GND

output

ABC

Pull-down

not (A and ( B or C))


What happens when the Boolean expression is false?

Since there is no path thru PDN, the output could float.

In order to make the output high, the PUN must have a path which connects VDD to the output.

Observe: take the expression for PDN and use DeMorgans Law to write it in terms of complemented input variables. Complemented variables are true when the input level is low. Thus, this gives exactly the form of the PUN

In this case: not A or ( not B and not C)


Vdd

B

C

A


CMOS NAND Gates• Use 2n transistors for n-input gate


CMOS NAND -- switch model


CMOS NAND -- more inputs (3)


CMOS – non-inverting buffer


CMOS – 2-input AND gate

• Note the number of transistors compared to NAND (6 vs. 4)


In-Class Practice Problem

• Design a CMOS NOR circuit

• Hint: Like NAND shown earlier, NOR circuits have 2n transistors for n-input gate (this one has 4)


CMOS NOR Gates

• Like NAND -- 2n transistors for n-input gate


NAND vs. NOR• NMOS has lower “on” resistance than PMOS

(important when multiple transistors are in series)NAND NOR

• Result: NAND gates are preferred in CMOS due to speed


Cascade Structure for Large Inputs

• 8-input CMOS NAND


Complex Logic Functions

• CMOS AND-OR-INVERT gate


Tri-State

• We lied - “binary” outputs have more than two values

• Some gates are designed to have a third value - a high impedance

• Effectively disconnects the gate output from the circuit


Tri-State Application

A FEn

If EN = 1, then F = A'if En = 0, then F is open circuited,

denoted Hi-Z B

AEn_ A

En_ A * A' + En_A' * B '


Open Drain

• Device without the internal active pull-up network on the output

• Why ?– Allows for two or more outputs to be

connected together– Produces a “wired” AND function

• Requires a pull-up resistor


Open Drain Application

+ 5 v

A

FEDCB (AB)' (CD)' (EF)'

=[AB + CD + EF] '


CMOS Families

• 4000 series - mostly obsolete

• HC

• HCT (input levels compatible with TTL)

• AC

• ACT (input levels compatible with TTL)

• FCT and FCT-T (both TTL compatible)


Bipolar Logic Families


TTL Digital Circuits

• Designed using “transistor-transistor logic” (remember EE341 ?)– npn bipolar junction transistors

• Transistors operate in either– cut-off mode

• no base current => no collector current

– saturated mode• base current pulls VCE to ~ 0.2 v


A Simplified TTL NAND Gate+ 5 V

AB

Vout


Schottky Transistors

• Addition of Schottky diodes between base and collector prevent saturation

• Schottky diode has lower forward bias voltage drop (0.25 v).

• Resulting design is called a Schottky transistor

• Speeds switching time by reducing charge storage in saturation


TTL NAND Gate


Special TTL outputs

• Standard output stage is called “totem pole” output

• Tri-state outputs

• Open collector (or CMOS open drain)– requires external pull-up resistor– allows wired-AND function


TTL differences from CMOS• Asymmetric input and output characteristics.• Inputs source significant current in the LOW

state, leakage current in the HIGH state.• Output can handle much more current in the

LOW state (saturated transistor).• Output can source only limited current in the

HIGH state (resistor plus partially-on transistor).

• TTL has difficulty driving “pure” CMOS inputs because VOH = 2.4 V (except “T” CMOS).


TTL Families

• 7400 series (5400 “mil spec”)

• 74 S - Schottky

• 74 LS - low power Schottky

• 74 AS - advanced Schottky

• 74 ALS - advanced low power Schottky

• 74 F - Fast TTL


9/10/98

TI’s Logic Products


Comparison of Signal LevelsCMOS

(HC, AC)

0 v

5 v

TTL (S, LS, AL, ALS, F)

0 v

5 v

CMOS (HCT, ACT)

0 v

5 v

0.5 v

1.5 v

3.5 v

4.4 v

VOL

VIL

VIH

VOH

VOL VOL

VIL VIL

VIH VIH

VOH VOH

0.4 v0.8 v

2.0 v

2.4 v

0.4 v0.8 v

2.0 v

2.4 v


Another Practice Problem


A

B

C

D

• Attempt to draw a truth table for the following circuit. Hint: List each transistor in the truth table and show whether it is on of off for each input combination

Another Practice Problem


ZHHHHHLLLHLLLHLLL

• OR-AND-INVERT

Next Classes

• Memorial Day – NO CLASS !

• Tues. - Help Day for Project #

• Wed. – Class Postponed

• Thur. - Electrical Behavior, Power & Timing

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EE365 Adv. Digital Circuit Design Clarkson University Lecture #4 Transistor Level Logic CMOS vs....

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