Ehud tzuri 3 d challanges new

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The Shift to 3D IC Structures - Manufacturing and

Process Control Challenges

Ehud Tzuri Chief Marketing Officer

ChipEx-2012, May 2012

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15 YEARS LAST

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5 YEARS NEXT

MORE INFLECTIONS

IN

THAN

Deep-UV Laser Lithography

Double Patterning

Epi Patterning Films

Lamp-based Processing Hi-K ALD Reflow HPD DPN SiON gate

Cu damascene Low-k dielectric

CMP 450mm

Advanced transistor

3D NAND

Sacrificial films

High aspect ratio Etch Laser-based processing

Interface management

Universal ALD

NOR NAND

DRAM 8F2 6F2

300mm Single-wafer Processing

Bumping

E-beam inspection

PVD Metal CVD

Atomic precision CMP CVD: hidden films

Wafer-level packaging

Advanced interconnect

Advanced patterning

Deposited resist

Flowable films

New materials: III-V, Ge

Dry chemical cleans

22nm 32nm 45nm 65nm 90nm 130nm 180nm 250nm 350nm 14nm 10nm

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Moore’s Law

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“In 1965, Gordon Moore sketched out his prediction of the pace of silicon technology. Decades later, Moore’s Law remains true, driven largely by Intel’s unparalleled silicon expertise.” (Source: Intel; Copyright © 2005 Intel Corporation)

The number of transistors on integrated circuits doubles every two years

How to maintain cost-performance ?

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Complying with Moore’s Law Maintaining Cost-Performance

Shrink the feature size: ArF Immersion EUV Increase wafer size: 200mm 300mm 450mm Build vertically: 2D 3D

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Where is 3D Architecture Implemented?

3D

Memory

V-NAND

Transistor

FinFET

Wafer level packaging

TSV

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3D

Memory

V-NAND

Transistor

FinFET


TSV

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Flash Roadmap*

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* The future is coming sooner than we thought

Source: J.Choi, Samsung, The 2nd International Memory Workshop, May.16, 2010


From 2D to 3D Flash NAND

A folded, vertically stacked NAND string Cells are generated inside a high-aspect-ratio (HAR) contact hole Benefits:

– Memory density is less dependent on patterning – Reduced coupling between memory cells – Cost scalability

Image Sources: Left:IMFT 25-nm MLC NAND: technology scaling barriers broken, DONG YI Technology Group, Published Date:2010-3-23 Right: Pipe-shaped BiCS Flash Memory with 16 Stacked Layers…/Ryota Katsumata - 2009 Symposium on VLSI Technology

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Sourceline

Select gate

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Complex multi-stack requires precise process monitoring –

thickness, RI, etch profile and defects

3D NAND Process Challenges TEM Image of 69-Layer Oxide/Nitride Stack

Source: Pipe-shaped BiCS Flash Memory with 16 Stacked Layers…/Ryota Katsumata - 2009 Symposium on VLSI Technology

Top

Bottom

Surface / interface roughness

Film stress control for low wafer bow

Fastest cycle time

Excellent stacked particle performance

Etch profile - ability to open HAR stacks

SEM X-section of double etched stack

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3D NAND Metrology & Inspection Challenges

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Imaging of HAR contact hole

along its depth

Charge Trap material thickness & uniformity along

contact depth

Embedded defects: Deep in the stack

Slit & plate etch inspection &

imaging



3D

Memory

V-NAND

Transistor

FinFET


TSV

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Planar vs. Trigate (FinFET) Transistor

Benefits – Gate surrounds Si from 3 directions, thus,

increasing control of over channel reduced leakage

– Can operate at lower voltage with good performance, reducing active power by >50%

Source: Intel 22nm Trigate announcement , 4/19/2011

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FinFet – Process Challenges

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STI Oxide

Fin

Spacer • Complete spacer removal from fin area

Fin Formation: • Precision etch • Structural integrity (collapse,

erosion, thermal shock) • Precise Recess to control fin

height • Channel materials to increase

mobility

Gate Stack (high-k & metal gate) • Material selectivity • Material deposition thickness

uniformity on vertical walls • Metal gate composition uniformity/stability

Fin Junctions: • Conformal doping

on sidewalls

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FinFET – Process Control Challenges

Lg

Lg

Lg

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Measurement of gate CD across the

Fin height

Detection & Review of defects on Fin sidewalls after

gate etch

Measurement of Fin sidewall angle to

control the 3D transistor width


Transistor Roadmap: Applied Materials View

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New Fin Material

STI Oxide

No end in sight for Moore’s Law – for the next decade

III-V FinFET

Gate

STI Oxide

Fin

Planar CMOS FinFET



3D

Memory

V-NAND

Transistor

FinFET


TSV

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3D Integration & TSV

TSV is a process in which wafers are: thinned, stacked & interconnected All flows include creation of deep holes and filling them with Cu

interconnect

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Source: DAC, 2½D Integrated Circuits, Wednesday, January 26, 2011 , Paul McLellan / Source: “Through-Silicon Via (TSV)””, Vol. 97, 0018-9219/$25.00 2009 IEEE No. 1, January 2009 | Proceedings of the IEEE

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TSV – Process Control Challenges

Handle wafer

Si substrate

CVD-SiO2

Interlayer Passivation layer

Bonding pad Adhesive

Ta/TaN/Au Wafer inspection for surface defects on TSV sidewalls and

bottom

HAR SEM-based defect review for sidewall and bottom defects;

including over-etch

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Common Challenges Defects of importance are located in the 3rd dimension;

they need to be found & imaged Measurements of the 3rd dimension (HAR, SWA) need to

be performed Current state of the art M&I tools have limitations to do so

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Possible Solutions

SEM-based imaging

Optical metrology

X-ray

Destructive technologies

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Possible Solutions – The Leading Candidate

SEM-based imaging

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3D imaging techniques with SEM

(Resolution)

E-beam inspection (Voltage Contrast)


Summary

The future is here… 3D transistors and TSV are already a reality, VNAND is just around the corner

3D Key challenges are related (mainly) to process integration and process control

Traditional process control solutions might not be sufficient

E-Beam based techniques have the potential to become the process control enablers

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Thank You

Date post:	25-May-2015
Category:	Business
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Ehud tzuri 3 d challanges new

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