ESE 570: Digital Integrated Circuits and VLSI … › ~ese570 › spring2019 › handouts › ...ESE...

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Lec 13: February 28, 2019 Combination Logic: CMOS

Penn ESE 570 Spring 2019 – Khanna

Lecture Outline

!  CMOS Gates "  1st order delay of Gates "  Gate design

"  Sizing, fanin

!  CMOS Worst Case Analysis

2 Penn ESE 570 Spring 2019 – Khanna

Review: 1st Order RC Delay Models

3

!  Equivalent circuits used for MOS transistors "  Ideal switch + “effective” ON resistance + load

capacitance "  Define unit resistance, Ru: “effective” ON resistance of unit transistor

with min length and W=Wu (usually min width) "  Define Run and Rup for nMOS and pMOS respectively

"  Cgb = Cg and Cdb = Csb = Cd for the unit n/pMOS transistors "  For scaled MOS device with scale factors κn, κp ≥ 1, i.e. Wn = κnWun

(Wp = κpWup) "  “effective” ON resistance Rn= Run/κn (Rp= Rup/κp) "  capacitances κnCd, κnCg (κpCd, κpCg)

τ PHL ≈ 0.69 ⋅Cload ⋅Rn Cload ≈ Cdbn + Cdbp + Cint + Cgb


Review: 1st Order Switch-RC MOS Models

4

nMOS

Rn = Run/κn

Assume: bulk at GND

κnCg

κnCd

κnCd

ON/OFF

(W/L)n

pMOS VDD

VDD VDD Rp = Rup/κp

Assume: bulk at VDD κpCd

κpCd ON/OFF

(W/L)p

κpCg

Rup ≈VDDLup

0.69µpCoxWup(VDD− |VT 0 p |)2

Run ≈VDDLun

0.69µnCoxWun (VDD −VT 0n )2

(W/L)n = κn (W/L)un

(W/L)p = κp (W/L)up

Rup= µn/µp Run


Review: Elmore Delay: Distributed RC network

!  The delay from source to node i "  N = number of nodes in circuit

5

Rik = Rj∑ ⇒ (Rj ∈ [path(s→ 4)∩ path(s→ k)])

τ Di = CkRikk=1

N

∑

τ Di =C1(R1)+C2 (R1)+C3(R1 + R3)+C4 (R1 + R3)+Ci (R1 + R3 + Ri )

(0 # 50%)

τ D = RpCload (0 # 63%)

NOTE:

τ p = 0.69τ DPenn ESE 570 Spring 2019 – Khanna

Combinational Logic

CMOS


CMOS Combinational Logic

!  Complimentary MOSFET "  Pull-up/pull-down complimentary networks

7

pMOS Net = dual (nMOS Net)


Two-Input NOR Gate (NOR2)

8

For Complimentary CMOS: Pull-up Net = dual (Pull-down Net)

F (VF) A (VA)

Z (VZ)

B (VB)

A (VA)

B (VB)

(A . B)

F (VF)

(A + B)

(A . B) (A + B) = Penn ESE 570 Spring 2019 – Khanna

Data Dependent Delay

!  Drive resistance depends on input values "  Delay depends on input data "  Analyze using worst case delay




!  Reminder: "  Rn= Run/κn

"  Rp= Rup/κp

"  Assume: µn=2µp

"  What is Rout? "  Output drive resistance





"  Rp= Rup/κp


"  What is Rout? "  Depends on input

"  What is worst case Rout?





"  Rp= Rup/κp



"  What is worst case Rout? "  Choose κp and κn, such that worst-case Rout=Run/2





"  Rp= Rup/κp



"  What is worst case Rout? "  What is input capacitance?


NAND2 – 1st Order Models


"  Rp= Rup/κp


"  Choose κp and κn, such that worst-case Rout=Run/2 "  What is input capacitance?


Transistor Sizing

!  What gate is this? !  Size (κp and κn) equalize rise/fall

times Rout=Run/2? !  Input Capacitance?


Transistor Sizing

!  NAND2 sized for Rout=Run/2 "  κp=4 and κn=4 "  Cin=8Cg

!  NAND3 sized for Rout=Run/2 "  κp=4 and κn=6 "  Cin=10Cg


Increasing Fanin

!  What happens to input capacitance as fanin (k) increases "  Keeping output drive the same

"  E.g. Rdrive=R0/2

!  k-input nand gate has what input capacitance?


Fanin

!  Conclude: gates slow down with fanin "  Less drive per input capacitance "  CInLoad/Ids increases


Transistor Sizing: INV

!  Size (κp and κn) equalize rise/fall times Rout=Run/2?

!  Input Capacitance?


Increasing Fanin

!  What happens to input capacitance as fanin (k) increases "  Keeping output drive the same

"  E.g. Rdrive=R0/2

!  k-input nand gate has what input capacitance?

!  Delay of Nand32 with output load 6Cg? "  Inputs driven with Run/2


Which is Faster?

!  nand32 Assume: -  Rup=2Run and gates are sized for Rout=Run/2 -  Input also driven by Rdrive = Run/2 -  Output load is 6Cg

nand4-inv-nand4-inv-nand2 (nand2-inv)4-nand2


Lesson

!  Large gates are slow / inefficient "  High capacitive load / drive current

!  Small gates can be inefficient "  Need many stages

!  Staging over moderate size gates minimizes delay !  Exact size will be technology dependent


23

And-Or Chain


Assume: -  Rup=2Run and gates are sized for Rout=Run/2 -  Input also driven by Rdrive = Run/2 -  Output load is 6Cg

Delay of each implementation?


Take Away?


CMOS NOR2 VTC

26

Kenneth R. Laker, University of Pennsylvania,

updated 26Feb15


CMOS NOR2 VTC

27


updated 26Feb15

3 VTC Cases V1 = 0 V; V2 = 0 → VDD V1 = 0 → VDD; V2 = 0 V1 and V2 = 0 → VDD simultaneously

Vout

Vin 0

simultaneous switching

only one input

switches

VDD

Switching Threshold Voltage: V1 = V2 = Vout = Vth


CMOS NOR2 Vth

28


updated 26Feb15


k pEQV= k p/2

k nEQV= 2k n

k p

k p

k n k n

CMOS NOR2 Vth

29

k pEQV= k p/2

k nEQV= 2k n

k p

k p

k n k n

Vth =VDD2

kR =kpEQVknEQV

=1

Symmetric ‘Inv’

&

kp = 4knPenn ESE 570 Spring 2019 – Khanna

Parasitic Caps for NOR2 (worst case)

30

Vx

2Cg

Cdbn1 = Cdbn2 = Cd

Cdbp1 = Cdbp2 = Cd

Csb1p = Csb2p = Cd Cd

Cd

Cd

Cd Cd



31

Vx

2Cg

Cdbn1 = Cdbn2 = Cd

Cdbp1 = Cdbp2 = Cd


Cd

Cd

Cd Cd

V1 = 0, V2 = VDD-> 0 @t=0 & Vx ≈ Vout = 0 -> VDD



32

Vx

2Cg

Cdbn1 = Cdbn2 = Cd

Cdbp1 = Cdbp2 = Cd


Cd

Cd

Cd Cd




33

Vx

2Cg

Cdbn1 = Cdbn2 = Cd

Cdbp1 = Cdbp2 = Cd


Cd

Cd

Cd Cd

V1 = 0, V2 = VDD-> 0 @t=0 & Vx ≈ Vout = 0 -> VDD Cload-NR2 ≈ 2Cd + 3Cd + Cint + 2Cg

RpEQV = Rp2+Rp1 Lumped Model Penn ESE 570 Spring 2019 – Khanna


34

Vx

2Cg

Cdbn1 = Cdbn2 = Cd

Cdbp1 = Cdbp2 = Cd


Cd

Cd

Cd Cd


Elmore Model? Cload-NR2 ≈ 2Cd + 3Cd + Cint + 2Cg

RpEQV = Rp2+Rp1



35

Vx

2Cg

Cd

Cd

Cd

Cd Cd



36

Vx

2Cg

Cd

Cd

Cd

Cd Cd


τ = (2Cd)(Rp2)+(3Cd+Cint+2Cg)(Rp1+Rp2)


37

Vx

2Cg

Cdbn1 = Cdbn2 = Cd

Cdbp1 = Cdbp2 = Cd


Cd

Cd

Cd Cd



38

Vx

2Cg

Cdbn1 = Cdbn2 = Cd

Cdbp1 = Cdbp2 = Cd


Cd

Cd

Cd Cd

V1 = 0, V2 = 0 ->VDD @t=0 & Vx ≈ Vout=VDD-> 0



39

Vx

2Cg

Cdbn1 = Cdbn2 = Cd

Cdbp1 = Cdbp2 = Cd


Cd

Cd

Cd Cd




40

Vx

2Cg

Cdbn1 = Cdbn2 = Cd

Cdbp1 = Cdbp2 = Cd


Cd

Cd

Cd Cd


Elmore Model? Penn ESE 570 Spring 2019 – Khanna


41

Vx

2Cg

Cd

Cd

Cd

Cd Cd



42

Vx

2Cg

Cd

Cd

Cd

Cd Cd


τ = (2Cd)(Rp1+Rn2)+(3Cd+Cint+2Cg)(Rn2)

43

Vx

V1

V2

2Cg

Cdbp1 = Cdbp2 = Cdbp

Cdbn1 = Cdbn2 = Cdbn

Csb1n = Csb2n = Csbn = Cdbn

Parasitic Caps for NAND2 (worst case)


44

Vx

V1

V2

2Cg






45

Vx

V1

V2

2Cg





V1 = VDD, V2 = VDD-> 0 @t=0 & Vx ≈ Vout= 0 ->VDD


46

Vx

V1

V2

2Cg






47

Vx

V1

V2

2Cg





V1 =VDD, V2 = 0 ->VDD @t=0 & Vx≈ Vout=VDD-> 0


Idea

!  CMOS Logic "  Complimentary dual pull-up/down networks

!  Gates have different efficiencies "  Drive strength per unit input capacitance "  Reason to prefer nand over nor

!  Large fanin and fanout slow gates "  Decompose into stages "  …but not too much

!  Delay "  1st order model on gates "  Size for worst case delay with Elmore delay


Admin

!  HW 5 due Friday, 3/1 !  Quiz Tuesday 3/12 after spring break

"  Lecture 1-12


Date post:	25-Jun-2020
Category:	Documents
Upload:	others
View:	1 times
Download:	0 times

ESE 570: Digital Integrated Circuits and VLSI … › ~ese570 › spring2019 › handouts › ...ESE...

Documents