IC Packaging 2008

CMP annual users meeting, January 10th 2008, PARIS

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IC Packaging ServiceIC Packaging Service

CMP offers a Complete Packaging Service:

Ceramic / Plastic / Plastic Open Cavity

Prototyping / Low volume / Add. packaging

Wide Range of Packages


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Ceramic PackagesCeramic Packages

SOIC 8 SOIC 16SOIC 20SOIC 24SOIC 28

Small Outline

PGA 68 PGA 84 PGA 100PGA 120PGA 144PGA 160PGA 180PGA 208PGA 224PGA 256

Pin Grid Array

LCC 16LCC 20LCC 28LCC 32LCC 44LCC 68LCC 84

JLCC 28JLCC 44JLCC 52JLCC 68JLCC 84

Leadless & J-Leaded Chip Carrier

CQFP 20CQFP 28 CQFP 44CQFP 64 CQFP 68 CQFP 84 CQFP 100CQFP 120CQFP 128CQFP 144CQFP 160CQFP 208CQFP 256

CerQuad Flat Pack.

DIL 8 DIL 14DIL 16DIL 18DIL 20DIL 24DIL 28DIL 40DIL 48

DualIn-Line

Sealed or Removable LidsSealed or Removable Lids


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Plastic Packages Plastic Packages ( 1 / 2 )( 1 / 2 )

SOIC 8 SOIC 14SOIC 16SOIC 20SOIC 22SOIC 24SOIC 28

Small Outline

TQFP 32TQFP 44TQFP 48.

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.

TQFP 160TQFP 176

Thin Quad Flat Package

PLCC 20PLCC 28PLCC 44PLCC 68

Plastic Leaded Chip Carrier

MQFP 80MQFP 100MQFP 128 .

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.

MQFP 240MQFP 256

Metric Quad Flat Package

Leaded Leaded

LQFP 32LQFP 44LQFP 48.

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.

LQFP 160LQFP 176

Low Quad Flat Package

QFP FamilyQFP Family


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PBGA 204PBGA 217PBGA 225PBGA 250PBGA 313PBGA 352PBGA 420PBGA 456

Plastic Ball Grid Array

QFN 8QFN 10QFN 12QFN 16

.

.

.

QFN 64QFN 72QFN 80

Quad Flat No lead

FBGA 81FBGA 108FBGA 144FBGA 160FBGA 196FBGA 208FBGA 225FBGA 256FBGA 280

Fine pitchBall Grid Array

TSSOP 20TSSOP 24TSSOP 28TSSOP 38

Thin Shrink SmallOutline Package

Plastic Packages Plastic Packages ( 2 / 2 )( 2 / 2 )

Thin, Array, Leadless Thin, Array, Leadless


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Plastic Packages : Open CavityPlastic Packages : Open Cavity

Advantages:Advantages:-- Open cavity packages enable smooth transfer to plastic packaginOpen cavity packages enable smooth transfer to plastic packaging processg process-- Price for small quantities up to 20Price for small quantities up to 20--40 dies40 dies-- Open cavity process is universal and can be applied to any plasOpen cavity process is universal and can be applied to any plastic IC package:tic IC package:BGA, QFP, QFN, PLCC, SOIC, TSSOP and moreBGA, QFP, QFN, PLCC, SOIC, TSSOP and more

STEP 1 STEP 2 STEP 3 STEP 4

Dummy Package Open Cavity Wire Bonding Remolding or Lid& Marking


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Package GuidelinesPackage Guidelines

Ceramic or Plastic ?Ceramic or Plastic ?

Prototyping:Prototyping:CMP recommends to use ceramic packagingCMP recommends to use ceramic packaging

Advantages:Advantages: Price for small quantitiesPrice for small quantitiesRemovable lidsRemovable lidsFlexible constraint (wire length, ground bonds, die thicknessFlexible constraint (wire length, ground bonds, die thickness))Thermal, HighThermal, High--Reliability (Space qualification)Reliability (Space qualification)

Low volumeLow volume::CMP recommends to choose the plastic packageCMP recommends to choose the plastic packageAdvantagesAdvantages: Low cost from 20: Low cost from 20--40 packaging (open tool only)40 packaging (open tool only)

Access to density solutions for low price (QFN, PBGA)Access to density solutions for low price (QFN, PBGA)


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Pads and Pads and PadringPadring rules rules

Standard Rules Non Standard Rules(available on request)Bonding PAD width

Absolute minimum (m) 76 x 76 -Recommended (m) 85 x 85 55 x 55

Bonding PADS spacingAbsolute minimum (m) 10 -Recommended (m) 15 10

Bonding PADS pitch

Absolute minimum (m) 86 -Recommended (m) 100 65


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CMP packaging process flowCMP packaging process flow

CMP users choose the package (CMP can help)

before the submission.CMP propose to the users the most

convenient package. (die size vs cavity size)CMP standardize all bonding diagrams.

Packaging is managed by MPW run.

CMP order the packages to the packaging house.

CMP ask the users for bonding diagram

and datasheet confirmation during the wafer fabrication.

CMP bonding diagram


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Data Sheet (Ceramic & Plastic Package)Data Sheet (Ceramic & Plastic Package)

Files Extension: .pdf, .dwg

Available Data to CustomersBlank Bonding Diagram Blank Bonding Diagram Package Data Package Data SheetSheet

Soon: Data sheets available for customers throught the web customer interface


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Packaging TechnologiesPackaging Technologies

CQFP,

QFN.

CQFP,

QFN.

Wire Bonding

Flip-Chip

Stacked dies

Stacked dies

MultiMulti--Stacked dies

Stacked dies

Wafer Bum

ping

Wafer Bum

ping

Die Bumping

Die Bumping


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Ultra-Sonic Method : Wedge-Bonding Aluminium wires with diameter up to 50 mAluminium wires with diameter up to 50 m Allow high voltage applicationsAllow high voltage applications Interconnection density smallerInterconnection density smaller

Wire bonding solutionsWire bonding solutions

Thermo-Sonic Method: Ball-Bonding Pure and hardened Gold wiresPure and hardened Gold wires Diameter wires from 18 m up to 50 m Diameter wires from 18 m up to 50 m Few packaging constraintsFew packaging constraints


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Wire bonding Limits Wire bonding Limits

Pad opening need to be about 3 times larger than the wire diametPad opening need to be about 3 times larger than the wire diameterer


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FlipFlip--Chip using Stud Bump Chip using Stud Bump -- Die LevelDie Level

Minimum pitch between bumps: 65 m

Gold wire (with Pd): 18-20 m

Standard machine for tooling

Die down electrical connection (over a substrate or circuit)

Available at die level

Limited to 32 I/O


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FlipFlip--Chip Chip vsvs Wire bondingWire bonding

Size reduced, smaller pitch

Higher integration (I/Os)Shorter connection length

Efficient heat dissipation

Moderate cost

Reliability

Compatibility housings

FLIP CHIP WIRE BONDING


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Density Solutions

Chip Scale Package (CSP)Chip Scale Package (CSP)

CSP package => Naked die occupies 80% or more of the package

Electrical performance is enhanced due to shorter interconnections

Package features Package features (1/3)(1/3)


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CNRS INPG UJF Quad Flat No lead (QFN) Quad Flat No lead (QFN)

QFN advantages:QFN advantages:

Thermal PerformanceThermal Performance Low Inductance; High FrequencyLow Inductance; High Frequency Thin; Low ProfileThin; Low Profile

Die thickness between 200 and 300 m

Copper Lead Frame

Solder PlatingSilver Ground Bond pad

DIE0.9 mm

Mold Compound

Lead



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Ball Grid Array (BGA)Ball Grid Array (BGA)

BGA advantages:BGA advantages:I/OI/Os: up to 456s: up to 456Shorter interconnections (density) Shorter interconnections (density) 1 up to 4 routable layers1 up to 4 routable layersHigh FrequencyHigh Frequency

Die thickness between 200 and 300 m



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BGA example realized with CMP BGA example realized with CMP (1/2)(1/2)

Body size: 35 mm x 35 mm

Ceramic BGA

420 I/OsThickness: 1.8 mmBall pitch: 1.27 mm


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BGA example realized with CMP BGA example realized with CMP (2/2)(2/2)

Body size: 31 mm x 31 mm

Organic BGA

304 I/OsPad size: 34 um x 108 umPad pitch: 78 umBall pitch: 1.27 mm


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0

10

20

30

40

50

2004 2005 2006 2007

DIL PGA LCC JLCC QFN QFP SOIC BGA

Choice of the packages per yearChoice of the packages per year%


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05

101520253035404550

DIL PGA LCC JLCC QFN QFP SOIC

2004200520062007

Packages choice evolutionPackages choice evolution

%


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Packaging AnalysisPackaging Analysis

Naked dies are visually inspected Naked dies are visually inspected accordingaccording to to thetheMILMIL--STDSTD--883 883 normnorm, method 2010 condition A or B , method 2010 condition A or B

Plastic Bonding Checking:Plastic Bonding Checking:XX--Ray TestRay Test

Ceramic Bonding Checking:Ceramic Bonding Checking:Visual InspectionVisual Inspection


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Packaging Process Flow for MPW RunPackaging Process Flow for MPW Run

Naked Dies

on Sticking filmSawing8 or 12 Wafer

PackagingLoading in Waffle Pack

PlasticPackaging

Ceramic Packaging

Turnaround: 2 weeks

Visual

Inspection

Extracted Extracted circuitscircuits


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Back lappingBack lapping8 wafers 8 wafers (200 mm)(200 mm): 725 : 725 mm (+/(+/-- 2020m)m) standard thicknessstandard thickness12 wafers 12 wafers (300 mm)(300 mm): 780 : 780 mm (+/(+/-- 2020m)m) standard thicknessstandard thickness

Wafer level back lappingWafer level back lappingaustriamicrosystems:austriamicrosystems:0.35 0.35 m (8m (8)) => standard => standard backback lapping to 480 mlapping to 480 m

=> => backback lapping to 380 m on lapping to 380 m on requestrequest

STMicroelectronics:STMicroelectronics:0.25 0.25 m (8m (8)) => standard => standard backback lapping to 375 mlapping to 375 m0.12 0.12 m (12m (12)) => standard => standard backback lapping to 375 m lapping to 375 m 90 n90 nm (12m (12)) => standard => standard backback lapping to 375 mlapping to 375 m65 n65 nm (12m (12) ) => standard => standard backback lapping to 250 mlapping to 250 m

OMMIC:OMMIC:ED02AHED02AH => => backback lapping to 100mlapping to 100m

Die level back lappingDie level back lappingDown to 150 m (absolute limit 100 Down to 150 m (absolute limit 100 m)m)


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ElectroStaticElectroStatic Discharge (ESD) packing Discharge (ESD) packing

Conditioning & Shipment: Antistatic Tubes:

Antistatic Bags: Protection against the electrostatic discharge

Surface Resistance (ohms) :108-109

Antistatic Boxes:


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Others Packaging Solution Others Packaging Solution

Case by case solutions Optical resin Hybrid Chip On Board (COB) Metallic package Conditioning of wafers and naked dies (vacuum or nitrogen atmosphere)

Service for additional packaging from previous run

[email protected]@imag.fr

http://cmp.imag.frhttp://cmp.imag.fr

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IC Packaging 2008

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