Abstract—A novel H-bridge multilevel pulsewidth modulationconverter topology based on a series connection of a high-voltagediode-clamped inverter and a low-voltage conventional inverteris proposed in this paper. A dc link voltage arrangement for thenew hybrid and asymmetric solution is presented to have a max-imum number of output voltage levels by preserving the adjacentswitching vectors between voltage levels. Hence, a 15-level hybridconverter can be attained with a minimum number of power com-ponents. A comparative study has been carried out to present highperformance of the proposed configuration to approach a verylow total harmonic distortion of voltage and current, which leadsto the possible elimination of the output filter. Regarding the pro-posed configuration, a new cascade inverter is verified by cascadingan asymmetrical diode-clamped inverter, in which 19 levels can besynthesized in output voltage with the same number of compo-nents. To balance the dc link capacitor voltages for the maximumoutput voltage resolution as well as synthesize asymmetrical dc linkcombination, a new multi-output boost converter is utilized at thedc link voltage of a seven-level H-bridge diode-clamped inverter.Simulation and hardware results based on different modulationsare presented to confirm the validity of the proposed approach toachieve a high-quality output voltage.
Index Terms—Asymmetrical diode-clamped inverter, hybridcascade converter, predictive current control.
I. INTRODUCTION
MULTILEVEL power conversion has achieved wide ac-ceptance for its capability of high-voltage (HV) and
high-efficiency operation. The most popular advantages of themultilevel inverter compared with the traditional voltage sourceinverter are high-power-quality waveforms with lower distor-tion and a low blocking voltage by switching devices. As thenumber of levels increases, these advantages will be enhanced;however, it can impose a significant expense of the increasein circuit complexity, which reduces the reliability and effi-ciency in such a converter. Three prominent five-level invertertopologies, i.e., diode-clamped [1], flying capacitor [2], andcascade [3], are shown in Fig. 1. An extensive comparison be-tween the multilevel topologies have been performed in [4] in
Manuscript received March 7, 2009; revised May 21, 2009 and July 23, 2009.Date of current version December 27, 2010. This work was supported by theAustralian Research Council (ARC) under ARC Discovery Grant DP0774497.Recommended for publication by Associate Editor B. Wang.
A. Nami, F. Zare, and A. Ghosh are with the School of Electrical Engineering,Queensland University of Technology, Brisbane, Qld. 4001, Australia (e-mail:[email protected]; [email protected]; [email protected]).
F. Blaabjerg is with the Institute of Energy Technology, Aalborg University,DK-9220 Aalborg, Denmark (e-mail: [email protected]).
Digital Object Identifier 10.1109/TPEL.2009.2031115
Fig. 1. Three multilevel topologies.
terms of their applications, circuit modeling, modulation tech-niques, and technical issues. Among these topologies, cascadeconfiguration has been utilized for medium-voltage and HV re-newable energy systems such as photovoltaic due to its modularand simple structure. Application of the cascade inverter forrenewable energy systems is reviewed in [5] and [6]. Higherlevel can be implemented easily by adding classical H-bridgecells to this configuration. However, it needs additional dc volt-age sources and switching devices. Proposition of a cascadeconverter using a single dc source and capacitors is proposedin [7], which can save the extra dc sources for higher level con-verters; however, a capacitor voltage balancing algorithm is re-quired [8]. Typically, different types of multilevel converters areutilized with the same rating of the dc link voltages and powerdevices due to modularity and simplicity of the control strat-egy. Recently, asymmetrical multilevel inverters with unequaldc source voltages have been addressed in literature [9]–[30].Therefore, based on different switching states, it is possible toachieve more voltage levels on output voltage by adding andsubtracting dc link voltages compared with conventional mul-tilevel inverters with the same number of components [9]. Bydoing so, output voltage with superior quality can be obtainedwith less circuit and control complexity, and also, increasing theharmonic characteristic of the output voltage can decrease the
52 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 1, JANUARY 2011
Fig. 2. Topology of the cascaded multilevel H-bridge converter.
size of the filter. The hybrid converters have been the main fo-cus of the literature with regard to asymmetrical configurationof multilevel inverters as they have shown their abilities andstrengths in medium- and high-power applications [9], [12].Diverse topologies have been studied based on a variety ofH-bridge cascaded cells and dc voltage ratio to enhance the out-put voltage resolution compared with the same dc voltage ratioof the cells [12]–[30]. However, due to the different voltage ratesof switching devices in hybrid configuration, it loses its mod-ularity compared with symmetrical cascade inverters. Variouspulsewidth modulation (PWM) strategies for symmetrical cas-cade inverters with high and fundamental switching frequencyhave been presented [14]–[16]. To reduce switching losses andimprove the converter efficiency, hybrid modulations for cas-cade converters with unequal dc sources are proposed, whichallows use of the slow switching device in the higher voltagecells and fast switching devices in lower voltage cells [17]–[19].
Since more voltage levels correspond to the increasing num-ber of components, recent research in this area has focused on aseries of connected multilevel converters in a cascaded H-bridgestructure [28]–[30]. The structure of the cascaded multilevel in-verter is demonstrated in Fig. 2, where the configuration con-sists of m-level multilevel H-bridge cells (either diode-clampedor flying capacitor inverter), each with an isolated dc source.
The number of cells depends on the desired output volt-age level, which is synthesized by adding up all the H-bridgecells output voltage as vout(t) = vout1(t) + vout2(t) + vout3(t)+ · · ·+ voutN (t). In a system that utilizes equal sets of dcsources (Vdc1 = Vdc2 = Vdc3 = · · · = VdcN ), the number ofoutput voltage levels is N× (m−1) + 1, where N is the numberof cascaded cells and m is the number of output voltage levels ineach multilevel H-bridge cells. The main advantage of this ar-rangement is the simplicity to cascade several H-bridge cells for
improvement of the output voltage resolution with reduced num-ber of components. However, capacitor voltage imbalance andcomplexity of the system can cause a critical problem that shouldbe taken into account in this configuration using either diode-clamped or flying capacitor topology [31], [35]. To address thislimitation, isolated dc sources or, alternatively, auxiliary con-verters can be used for capacitor voltage balancing. Utilizationof unequal dc sources on each series diode-clamped or flyingcapacitor cells can increase the number of output voltage fora given power circuit in Fig. 2, with the equivalent number ofcomponents. A different dc voltage ratio for H-bridge cells isproposed to achieve the maximum number of output voltage lev-els. However, along with possible maximization of obtainableoutput voltage levels based on the voltage ratio of dc sources, theexistence of adjacent switching vectors to move from one possi-ble voltage level to another with only one switch change shouldbe considered. Simultaneous switching of different switches isnot an immense problem when there are just a few of them hap-pening over one cycle; however, when switching between thenonadjacent switching vectors occurs frequently in modulationbetween adjacent levels, it becomes a critical issue to increasethe switching losses.
In this paper, a general idea of cascading multilevel H-bridgecells is used to propose different configurations using a seven-level symmetrical and asymmetrical diode-clamped H-bridgeconverter supplied with a multi-output boost (MOB) converter,cascaded with classical three-level inverters. The MOB con-verter can solve the capacitor voltage imbalance problem aswell as boost the low output voltage of renewable energy sys-tems such as solar cells to the desired value of the diode-clampeddc link voltage. DC voltage ratio of cells will be presented toobtain maximum voltage levels on output voltage with adjacentswitching vectors between all possible voltage levels, whichcan minimize the switching losses. Using a triple-output dc–dcconverter offers asymmetrical dc link capacitor voltage arrange-ment for the seven-level H-bridge diode-clamped converter, inwhich nine voltage levels can be obtained with the same num-ber of components. Using an asymmetrical diode-clamped con-verter in the proposed cascaded H-bridge cells achieves fourmore voltage levels in the output compared with the symmet-rical configuration. Performance of the proposed asymmetricalH-bridge diode-clamped inverter has been verified by simula-tion and hardware results. Finally, two different PWM methodsbased on predictive current control have been presented to vali-date the proposed approach.
II. SYMMETRICAL AND ASYMMETRICAL DIODE-CLAMPED
CONVERTERS (SDCC AND ADCC) USING THE MOBCONVERTER
A new dc–dc boost converter with multiple outputs, which canbe used as a front-end converter to boost the inverter’s dc linkvoltage for grid connection systems based on a diode-clampedconverter, is analyzed in [35]. Using this MOB converter, thedc voltage across each capacitor can be adjusted to a desiredvoltage level, thereby solving the main problem associated withbalancing the capacitors’ voltages in such converters. In [11],
NAMI et al.: HYBRID CASCADE CONVERTER TOPOLOGY 53
Fig. 3. H-bridge proposed diode-clamped inverter with three dc link capacitorsjoint with a triple-output boost converter.
TABLE IPOSSIBLE SWITCHING STATES IN ONE LEG OF A SEVEN-LEVEL
DIODE-CLAMPED INVERTER
a new modulation technique has been presented for a diode-clamped inverter when voltages across capacitors are unequal.Fig. 3 shows a configuration for an H-bridge seven-level diode-clamped inverter joint with the front-end MOB converter. Anunequal dc link arrangement is applied instead of identical dclink capacitor voltages. The bottom capacitor’s voltage is keptat twice the level of other capacitors during operation, so thatthe configuration has asymmetrical behavior with respect to theneutral point (Vc1 = 2Vc2 = 2Vc3). As shown in Fig. 3, it is sup-posed that the low input voltage (E) is boosted to Vdc at the dclink of the seven-level diode-clamped H-bridge inverter (VNM ).Therefore, in the SDCC configuration, dc link capacitors voltageratios are Vc1 = Vc2 = Vc3 = Vdc/3; however, in ADCC con-figuration, capacitors’ voltages are maintained at Vc1 = Vdc/2and Vc3 = Vc2 = Vdc/4 (with respect to the neutral point).
According to the structure of the seven-level diode-clampedconverter, there are four possible switching states in each legof the inverter that can be derived from four switch combina-tions to obtain different dc link voltage levels. The “ON” and“OFF” switching states of each switch are defined as “1” and“0,” respectively. Four switching states in one leg of the diode-clamped H-bridge inverter are distinguished by four switchingfunction states that are summarized in Table I. For example,(011) means that S1 = 0 (OFF), S2 = 1 (ON), and S3 = 1 (ON),which is defined as switching function state “2.”
All possible switching states associated with different outputvoltage levels in SDCC and ADCC are shown in Table II. Ex-ploring the output voltage levels, nine different voltage levelscan be generated in asymmetrical dc link arrangement basedon different switching states, in which two more voltage lev-els can be synthesized in the output voltage compared with the
TABLE IIOUTPUT VOLTAGE LEVELS ASSOCIATED WITH DIFFERENT SWITCHING
FUNCTION STATES FOR SDCC AND ADCC CONFIGURATIONS
Fig. 4. Adjacent switching vectors for a seven-level diode-clamped inverterwith symmetrical and asymmetrical dc link configurations.
symmetrical arrangement with the same number of switchingdevices.
From the possible switching function states defined in Table I,Fig. 4 shows the adjacency diagram of SDCC and ADCC config-urations. As shown, the adjacent vectors are available betweenall voltage levels in both configurations, so that all voltage levelscan be achieved with one switch change. However, nonadjacentswitching transitions are required between the following switch-ing transitions in the ADCC configuration, which are depictedby dashed lines in Fig. 4:
1) (20) and (31)2) (02) and (13).This transition requires two switch changes in the ADCC. To
remove nonadjacent voltage vector in positive voltage levels,
54 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 1, JANUARY 2011
TABLE IIIMAXIMUM VOLTAGE RATE ACROSS SWITCHING COMPONENTS IN ONE LEG OF
A SEVEN-LEVEL H-BRIDGE DIODE-CLAMPED INVERTER WITH SYMMETRICAL
AND ASYMMETRICAL DC LINK ARRANGEMENTS
when the controller increases the voltage level from Vdc/2 to3Vdc/4, transition occurs from switching function states (31)to (20). Then, the controller uses switching function state (10)for modulation between Vdc/2 and 3Vdc/4. Also, after the oc-currence of the transition from 3Vdc/4 (20) to Vdc/2 (31), thecontroller uses state (21) for the modulation between Vdc/2 andVdc/4. The same situation happens when the output voltageis negative. Therefore, these nonadjacent switching transitionsoccur only four times during one cycle. It is apparent that byassuming that switching losses are proportional to the number ofswitching per cycle, the switching loss associated with the extraswitching is negligible at high switching frequency. As a re-sult, improved voltage waveforms can be obtained using ADCCtopology compared with SDCC topology with the same numberof components and almost the same number of switchings.
Although the output voltage of the asymmetrical dc link ar-rangement benefits from two more voltage levels with the samenumber of components compared with the symmetrical dc linkarrangement, extra voltage rates should be taken into accountfor two switches in each leg of the inverter. Maximum voltageacross switching components during different switching statesis derived in Table III to have a comparison between the volt-age rating in the symmetrical and asymmetrical dc link arrange-ments. In the asymmetrical configuration, the maximum voltagerating of switches (S3 and S6) in each leg is Vdc/6 more than theswitches in the symmetrical configuration for the same dc linkvoltage. By investigating the voltage ratings, maximum voltagerating of diodes (Dc1 and Dc3) decreased by Vdc/12 and Vdc/6;however, the maximum voltage tolerated by another two diodes(Dc2 and Dc4) increased by Vdc/12 and Vdc/6, which showsthat the maximum voltage across diodes has not changed in bothconfigurations.
The output voltage of the symmetrical and asymmetricalsingle-phase diode-clamped inverters for the same circuit pa-rameters is shown in Fig. 5. Herein, at the dc–dc side, input volt-age (E) is assumed to be 100 V; switching frequency of the dc–dcconverter (fsw ) is 10 kHz, L = 2 mH, and C1 = C2 = C3 = 1mF, while at the inverter side, fundamental and switching fre-quencies are f = 50 Hz, fsw = 4 kHz, and the dc link ofthe seven-level diode-clamped inverter (VNM ) is boosted to300 V using a triple-output boost converter. Midpoint voltage
regulation for symmetrical and asymmetrical configurations forhigh modulation index (ma = 1) and unity power factor (PF)has been shown in Fig. 5(a). It is clear that the MOB converteris able to boost the low input voltage for dc link capacitors aswell as balance the capacitors voltage to the desired level forma = 1 and pure resistive load, which is impossible in morethan five-level single-phase diode-clamped topology without anactive front-end converter. In order to generate the output volt-age, based on the duty cycle of switches, the controller choosesthe next suitable switching function state using the adjacentvectors in Fig. 4. To show the performance of the proposedstructure for inductive load, Fig. 5(b) illustrates the dc linkcapacitor voltage control and output voltage for ma = 1 andPF = 0.5. In order to synthesize an equal dc link capacitorvoltage arrangement in the conventional configuration, whilethe total voltage of an inverter dc link is boosted at 300 V,midpoint voltages (Vc1 and Vc1 + Vc2) are controlled at 100and 200 V. However, to have an asymmetrical dc link config-uration, midpoint voltages are controlled at 150 and 225 V,respectively.
A laboratory prototype of a symmetrical and an asymmetricalseven-level H-bridge inverter has been implemented to practi-cally verify the proposed configuration. The laboratory proto-type has been tested for the following specifications: Vdc = 90V, Iut-peak = 5 A, f = 160 Hz, and fsw = 6 kHz under pure in-ductive load L = 16 mH. A predictive current control has beendeveloped in a V850E/IG3 microcontroller to force the load cur-rent to follow the for the H-bridge seven-level diode-clampedinverter with symmetrical and asymmetrical dc link arrange-ments. Switching states to generate the desired voltage levelbased on the amount of current reference is chosen by the mi-crocontroller according to adjacent switching vectors. Outputvoltage and current of the symmetrical and the asymmetricalseven-level diode-clamped inverter is demonstrated in Fig. 6.Regarding simulation and hardware results, two more voltagelevels can be synthesized in output voltage of the ADCC config-uration compared with the SDCC configuration with the samenumber of components and structure. Therefore, the seven-levelH-bridge inverter performs similarly to a nine-level inverter. Toexamine the performance of the asymmetrical configuration,harmonic spectrums associated with the output voltage of boththe SDCC and ADCC configurations are exposed in Fig. 6.Comparing harmonic spectrums, better harmonic performanceis obtainable using the asymmetrical dc link arrangement for thediode-clamped converter. This achievement allows, on one hand,an improvement in output voltage harmonic characteristics withthe same number of components compared with the symmetri-cal seven-level H-bridge configuration, and on the other hand,a decrease in cost and complexity of the inverter hardware lay-out structure with the same output waveforms quality comparedwith the symmetrical nine-level H-bridge inverter.
III. PROPOSED MULTILEVEL HYBRID CASCADE CONVERTERS
One of the aspects of this paper is to select dc input voltagesfor a topology based on a series connection of a symmetrical andan asymmetrical diode-clamped H-bridge cell with three-level
NAMI et al.: HYBRID CASCADE CONVERTER TOPOLOGY 55
Fig. 5. DC link capacitor voltages and output voltage for SDCC configuration and ADCC configuration with (a) resistive load (ma = 1, PF = 1) and(b) inductive load (ma = 1, PF = 0.5).
H-bridge inverters to achieve a maximum number of output lev-els by preserving the minimum switching losses. Simultaneousswitching of different switches is not a real problem when thereare just few of them happening over one cycle; however, repeat-edly switching between the nonadjacent switching vectors isnot acceptable, due to an increase in switching losses and com-mutation noise. The state of art in this topology can improvethe resolution of the output voltage with minimum power com-ponents, while keeping the adjacent switching vectors betweenall modulation voltage levels. Fig. 7 presents the schematic ofthis configuration for a two-cell hybrid cascade converter. TheMOB converter is utilized to supply dc input voltage of thediode-clamped multilevel H-bridge cell to regulate capacitorsvoltages and provide the desired voltage rate for the dc linkcapacitors.
To achieve maximum resolution in output voltage of theN-cell proposed topology, the dc voltage arrangement should
be considered as follows:
VdcN =Minimum voltage level of multilevel inverter
2N −1 (1)
where, for the proposed two-cell inverter in Fig. 7, we have
Vdc2 =Minimum voltage level of multilevel inverter
2. (2)
Based on this arrangement, the number of output voltagelevels can be derived from (1)
number of output levels = 2N −1 × (m + 1) − 1 (3)
where m is the number of output voltage levels of multilevelH-bridge inverters and N is the number of cells. Regarding (3),there are two possibilities to increase the obtainable voltage lev-els in the proposed configuration. One solution is by adding aclassical three-level H-bridge inverter in which the number ofvoltage levels will be doubled. This imposes four extra switches
56 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 1, JANUARY 2011
Fig. 6. Experimental results for output voltage and current with output voltage spectrum for pure inductive load in seven-level H-bridge with SDCC configurationand ADCC configuration. Vdc = 90 V, fsw = 6 kHz, C = 1 mF, load = 16 mH. (Scale: X-axis, 1 ms/division. Y-axis, vout (t): CH1: 50 V/division, iout (t): CH2:10 A/division.) (Scale: X-axis: frequency: 2.5 kHz/division. Y -axis: fast Fourier transform: 2 V/division.)
Fig. 7. Proposed topology of cascaded H-bridge inverter cells.
and one isolated dc source in regular configuration of the sys-tem. Although implementation of a three-level inverter by a dccapacitor saves the isolated dc source, it still requires four extraswitching devices, an extra dc link capacitor, and further ef-fort on capacitor voltage balancing [7], [8], [19]. Alternatively,the number of output voltage levels increases when the diode-clamped output voltage levels are increased, in which four extra
switches, four clamped diodes, and one dc link capacitor areneeded.
According to the ADCC configuration, using asymmetricalconfiguration in the diode-clamped dc link voltage leads to anincrease in the output voltage levels without increasing the num-ber of components in a diode-clamped H-bridge structure. Here,the realization of the asymmetrical configuration for H-bridgediode-clamped inverters in the proposed hybrid cascaded topol-ogy results in an increase in the number of output voltage levelswith the same number of components. This issue will be com-paratively discussed for two cells H-bridge cascade connectionwith seven-level SDCC and ADCC configurations in the fol-lowing sections.
A. Two-Cell Cascaded H-Bridge Converter With Seven-LevelH-Bridge SDCC
Fig. 8 illustrates 15-level cascade inverters assembled fromone module of an HV symmetrical H-bridge seven-level diode-clamped inverter and a low-voltage (LV) classical three-level H-bridge inverter. Herein, the dc link voltage of a diode-clampedinverter is boosted and regulated for the equal rate by a MOBconverter. To meet (2), where the dc link voltage of the classical
NAMI et al.: HYBRID CASCADE CONVERTER TOPOLOGY 57
Fig. 8. Proposed two-cell H-bridge cascaded inverter topology with SDCC.
inverter is half of the lower level of the diode clamped inverter,the dc link voltage of the diode-clamped inverter is regulatedto Vdc1 = 6Vdc2 using the MOB converter. Referring to (3), 15different voltage levels can be achieved on output voltage.
Possible switching states for both the seven-level H-bridgeSDCC and the three-level inverter with relevant output voltagelevels have been shown in Table IV. The adjacent switchingvectors of the different voltage levels for the proposed topologyassociated to switching states of H-bridge cells are depicted inFig. 9. The first two digits of each switching function states areallocated to the diode-clamped inverter in terms of Table I andthe other two digits belong to the three-level H-bridge inverterswitching function state, which is “1” when S13 = 0 and S14 =1 and “2” when S13 = 1 and S14 = 1.
According to the adjacent switching vector diagram, switch-ing transitions employ switches of only the LV cell for modu-lation between adjacent levels, so that it is possible to achievedifferent levels with just one switch change, except for in move-ment from a pair of modulated levels to another. Therefore, threeextra switching transitions take place in each half cycle betweennonadjacent voltage vectors. For a positive half cycle, extraswitching occurs when the voltage level is changed from Vdc/6(0021, 1121, 2221, 3321) to Vdc/3 (1011, 1022, 2111, 2122,3211, 3222), Vdc/2 (1021, 2121, 3221) to 2Vdc/3 (2011, 2022,3111, 3122), and 5Vdc/6 (2021, 3121) to Vdc (3011, 3022). Al-though these extra switching losses will be negligible at highswitching frequency, using a proper PWM method can avoidany extra switching losses in this configuration.
B. Two-Cell Cascaded H-Bridge Converters With Seven-LevelH-Bridge ADCC
A higher number of levels can be obtained easily using anasymmetrical diode-clamped inverter in the HV cell as the MOBconverter can constrain capacitors’ voltage to different volt-age rates. Fig. 10 presents a proposed hybrid cascade converterwhere the bottom capacitor voltage in the diode-clamped in-verter is twice the other capacitors, so that the minimum voltagelevel in this configuration is Vc2 = Vc3 = Vdc/4. To meet therequirement of (2) to have maximum output voltage levels with
TABLE IVOUTPUT VOLTAGE LEVELS FOR DIFFERENT SWITCHING STATES OF THE
SEVEN-LEVEL SDCC, A CLASSICAL THREE-LEVEL INVERTER, AND THE
adjacent switching vectors, the dc link of the diode-clampedinverter is controlled at Vdc1 = 8Vdc2 using a MOB converter,in which the dc link voltage of the three-level inverter is halfthat of the lower voltage of the diode-clamped inverter. Accord-ing to (3), 19 voltage levels can be achieved using ADCC ina multilevel H-bridge cell. Furthermore, there is no need for acontrol strategy to balance the capacitors’ voltage as MOB reg-ulates the capacitors voltage that reduces the complexity of thecontrol system in a higher number of levels. Table V presentsthe output voltage level corresponding to the possible switchingstates for both the seven-level ADCC H-bridge converter andthree-level inverters. As shown, using the asymmetrical config-uration for diode-clamped topology in the HV cell, the outputvoltage has 19 levels, which is four levels more than that inthe proposed cascade configuration with SDCC configuration.Therefore, increasing voltage levels of the cascaded H-bridge
58 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 1, JANUARY 2011
Fig. 9. Adjacent switching vectors for the 15-level proposed cascaded H-bridge inverter.
Fig. 10. Proposed two-cell H-bridge cascaded inverter topology with ADCC.
inverter can lead to a better output voltage quality and reductionor elimination of the output filter.
The adjacency of switching function states with regard toswitching states in Table V is shown in Fig. 11 for all outputvoltage levels of the proposed topology. As shown, adjacencyis available between all voltage levels and all the transitions be-tween adjacent voltage levels employ switches of only the LVcell, except for moving from a pair of modulated levels to an-other. Since these transitions do not occur repeatedly, four extraswitchings take place in each half cycle between nonadjacentvectors compared with a symmetrical configuration when thevoltage level is changed from Vdc/8 (0021, 1121, 2221, 3321)to 2Vdc/8 (2111, 2122, 3211, 3222), 3Vdc/8 (2121, 3221) toVdc/2 (1011 1022, 3111 3122), 5Vdc/8 (1021, 3121) to 6Vdc/8(2011, 2022), and 7Vdc/8 (2021) to Vdc (3023, 3011). Utiliza-tion of a proper PWM strategy is necessary to achieve high-performance output voltage with respect to adjacent switchingvectors to minimize extra switching losses in this configuration.
TABLE VOUTPUT VOLTAGE LEVELS FOR DIFFERENT SWITCHING STATES OF THE
SEVEN-LEVEL ADCC, A CLASSICAL THREE-LEVEL INVERTER, AND THE
To study the operation of the proposed cascaded H-bridgeconverters, the PWM converter scheme has been simulated usingMATLAB software. The main electric components of the powercircuit are given in Table VI. To confirm the validity of thesystem, a comparison study has been carried out for H-bridgecascaded converters with symmetrical and asymmetrical diode-clamped inverters. In order to achieve identical comparison,equal parameters are considered for both topologies. Total dclink voltage of two cells is assumed to be 270 V, where the dclink voltage of the classical three-level inverter is 39 V for the
NAMI et al.: HYBRID CASCADE CONVERTER TOPOLOGY 59
Fig. 11. Adjacent switching vectors for the 19-level proposed cascaded H-bridge inverter.
TABLE VIPARAMETERS USED IN SIMULATIONS
15-level converter and 30 V in a 19-level converter. To verifythe 15-level and the 19-level hybrid converters based on (2), thedc link voltage of the SDCC and ADCC should be controlled at231 and 240 V, respectively. Therefore, dc link capacitor voltageshould be regulated to have an equal (Vc1 = Vc2 = Vc3) or anunequal (Vc1 = 2Vc2 = 2Vc3) dc link arrangement.
Different PWM techniques have been proposed for single-phase and three-phase hybrid converters in order to have ahigh-quality load voltage and low switching losses [36]–[39].
A simple and generalized time-domain duty cycle computationtechnique for the single-phase multilevel inverters has been ex-tended for the hybrid converters in [37], where the referencevoltage is achieved as the averaged value between two nearestoutput voltage levels of the converter. However, the performanceof the proposed method for hybrid converters decreases com-pared with the cascade inverter as the calculations increase. Inaddition, adjacent switching vectors have not been consideredfor hybrid configuration, which can increase the losses. Cur-rent control is an essential part of the overall control systemthat allows instantaneous current waveform control with highaccuracy, as well as peak current protection and overload re-jection [38], [39]. A novel predictive current control based onadjacent voltage vectors has been proposed [38] for three-phasemultilevel converters, which can be applied easily for the multi-level converter with different voltage levels without significantchanges in the control system. In this paper, a general ideaof predictive current control is utilized to generate the desiredcurrent for asymmetrical and symmetrical H-bridge cascadedconfigurations based on adjacent switching vectors. Accordingto Fig. 8 or Fig. 10, the phase output voltage can be defined interms of the RL load component as follows:
vout = Riout + Ldiout
dt+ e (4)
where iout is the load current, vout the phase voltage, R the loadresistance, L the load inductance, and e is the back emf voltage.
Since the aim of this PWM is to justify the performance ofthe proposed cascade converters to synthesize all voltage levels,pure inductive load has been studied as a load (R = 0, e = 0).Thus, (4) can be rewritten as follows in each switching period:
vout = Liout,n+1 − iout,n
Tsw(5)
where iout,n+1 is the amount of current in the next switchingcycle, iout,n is the present current, and Tsw is the switchingperiod. Therefore, from (5), duty cycle to force the load currentto track the reference current in the next switching period canbe predicted by
d = LIref − iout,n
VdcTsw. (6)
According to (6), the duty cycle can be calculated easily bymeasuring the load current. Once the duty cycle of all switcheshas been calculated to generate the desired currents at the end ofeach switching cycle, the duty cycle of switches can be definedbased on the amount of total duty cycle from (7).
Defined voltage levels based on duty cycle for the 15-level andthe 19-level proposed hybrid converters are shown in Table VII:
0 <
n−1∑1
dj <1
(n − 1)
1(n − 1)
<
n−1∑1
dj <2
(n − 1)...
(n − 2)(n − 1)
<n−1∑
1
dj < 1 (7)
60 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 1, JANUARY 2011
TABLE VIIOUTPUT VOLTAGE BASED ON DIFFERENT DUTY CYCLES IN POSITIVE HALF
CYCLE OF THE 15-LEVEL AND 19-LEVEL HYBRID CONVERTERS
(Vdc = Vdc1 + Vdc2 )
where n is the number of nonnegative voltage levels per legand
∑n−11 dj is the sum of duty cycles of all switches per leg.
Based on the defined voltage levels in each switching cycle, thecontroller identifies relevant switching states of the particularvoltage level regarding adjacent switching vectors to minimizeswitching losses. However, according to the adjacent switchingvectors graph for the 15-level and 19-level converters (Figs. 9and 11), there are some nonadjacent switching states that occurin some voltage levels, in which extra switching losses lead tothe desired voltage levels. Based on the controller’s decisions atthese points to change the voltage levels, two different methodshave been proposed to achieve the proper switching states.
A. With Extra Switching
In the first method, switching states are chosen to achieve dif-ferent voltage levels regardless of adjacency between switchingtransitions. As is depicted for one nonadjacent point in Fig. 12,to increase the voltage from Vdc1/6 to Vdc1/3 in the 15-levelconverter or from Vdc1/8 to Vdc1/4 in the 19-level converter,the switching function states should be changed from (3321) to(3222). Then the controller uses (3222) and (3212) for modula-tion between these voltage levels. Therefore, one extra switchingtransition happens due to nonadjacent vectors. The same situa-tion happens for the other nonadjacent transitions that happen12 times in the 15-level converter and 16 times in the 19-levelconverter in each fundamental cycle.
Although it is possible to achieve sequenced voltage level bylocating the duty cycles in the middle of each switching cycle,extra losses should be paid. Extra switching can be determined
Fig. 12. Switching transition selection with extra losses.
Fig. 13. Extra switching in terms of switching frequency.
by the following equation:
Extra switching%
=Extra switching transition×Fundamental frequency
Switching frequency.
(8)
Fig. 13 shows the extra switching in terms of switching fre-quency. As shown, total extra losses will be negligible in higherswitching frequencies. Fig. 14 illustrates output voltage for the15-level and the 19-level hybrid converter with extra lossesmethod at fsw = 5 kHz. Output waveforms are nearly sinu-soidal and current tracks the reference current accurately. Totalharmonic distortion (THD) of the output voltage is calculated
NAMI et al.: HYBRID CASCADE CONVERTER TOPOLOGY 61
Fig. 14. Output voltage of 15-level and 19-level H-bridge cascaded inverterswith extra switching modulation.
as follows:
THD =
√∞∑
n=2(Vn )2
V1. (9)
However, to have a harmonic current distortion factor,weighted THD (WTHD) of the output voltage is compared forthe symmetrical and asymmetrical hybrid converters based on
WTHD =
√∞∑
n=2(Vn/n)2
V1. (10)
THD of the output voltage and current waveforms for oneswitching frequency sideband of the proposed hybrid cascadeconverter with the SDCC and ADCC in terms of differentswitching frequencies are depicted in Fig. 15. According toFigs. 13 and 15, as the trend of THD and extra losses decreasesat higher switching frequencies, the THD of the hybrid converter
Fig. 15. THD and WTHD of the output voltage for the proposed 15-level and19-level hybrid converters with extra switching modulation.
with ADCC is almost 1.7% less than the symmetrical one. Asshown in Fig. 15, once the switching losses are negligible at highswitching frequencies, the WTHD of the proposed configurationdecreases either for the 15-level or the 19-level converter. How-ever, configuration with the asymmetrical diode-clamped H-bridge shows better harmonic characteristics compared with theconfiguration with a symmetrical H-bridge converter. Based onthe proposed cascaded configuration, switches in the HV mul-tilevel cell work at the fundamental frequency, while switchesof an LV cell work with the switching frequency. Enhancedharmonic characteristics are expected for asymmetric configu-ration as the number of output voltages in configuration withthe symmetrical diode-clamped converter is lower than that inthe asymmetrical configuration.
62 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26, NO. 1, JANUARY 2011
Fig. 16. Switching transition selection without extra losses.
B. Without Extra Switching
In order to avoid any extra switching, a second method to se-lect the proper switching states is proposed, which is shown asa nonadjacent voltage vector in Fig. 16. Thus, to change voltagelevel from Vdc1/6 to Vdc1/3 in the 15-level converter and fromVdc1/8 to Vdc1/4 in the 19-level converter, switching transitionsoccur from (3322) to (3222). Then the controller uses (3222)and (3212) for modulation between these voltage levels. By do-ing so, no extra switching happens to increase the voltage levels.However, the voltage will jump two levels when these switchingfunction states are chosen. Therefore, 12 jumps of these voltagelevels occur in the output voltage of the 15-level inverter as ithas 12 nonadjacent switching transitions in each fundamentalfrequency. The same scenario happens for the 19-level hybridinverter as it has 16 nonadjacent switching vectors in each cycle.Setting the pulsewidth based on the defined duty cycle in themiddle of the switching cycle gives an opportunity to obtainupper voltage levels with a jump and without any extra switch-ing losses. However, a number of asymmetrical pulse patternsoccur in each fundamental frequency (12 times in the 15-levelinverter and 16 times in the 19-level inverter), and worse THD isexpected for this PWM method compared with the previous one.Fig. 17 demonstrates the output voltage waveforms at fsw = 5kHz in the proposed hybrid cascade converter with SDCC andADCC configurations.
To compare the quality of the waveforms of a hybrid cascadeconverter with symmetrical (15-level) and asymmetrical (19-level) diode-clamped inverters, THD and WTHD for one side-band of the switching frequency of the output voltage accordingto (9) and (10) are illustrated in Fig. 18. Although the qualityof output waveforms is less than that in the PWM strategy withextra switching due to the number of voltage jumps, configura-
Fig. 17. Output voltage of 15-level and 19-level H-bridge cascaded inverterswithout extra switching modulation.
tion with ADCC H-bridge provides better quality waveforms.In higher switching frequencies, as the number of voltage jumpsis negligible, harmonic characteristics of output waveforms areimproved.
The diversity of two methods either in the case of THD ofvoltage and current or extra switching losses is negligible athigher switching frequency (more than 8 kHz), which showsthe high performance of this proposed method to achieve morevoltage levels with minimum power components and losses.Nevertheless, at low switching frequency based on differentapplications, a proper PWM method can be chosen in order tohave a better quality or minimum losses.
To study the effect of the dc link variation on performanceof the proposed converters, two different ripples, 5% and 10%of the dc link voltage, have been taken into account in bothmodulation techniques for the inductive load at the switchingfrequency of 10 kHz. In the 15-level converter with the extraswitching, the THD rose to 7.2% and 9.8% at 5% and 10%ripples, respectively. However, in the 19-level converter, it isincreased to 5.82% and 8.37%, respectively. Also, in the mod-ulation without extra switching, the THD of the output voltage
NAMI et al.: HYBRID CASCADE CONVERTER TOPOLOGY 63
Fig. 18. THD and WTHD of the output voltage for the proposed 15-level and19-level hybrid converters without extra switching modulation.
for the 15-level converter at 5% and 10% ripples reached to7.91% and 8.22%, respectively, while in the 19-level converter,these were at 6.8% and 8%, respectively. It can be concludedthat, even by considering dc link ripple, the THD of the outputvoltage in the proposed hybrid converter with ADCC is stillless than the converter with SDCC configuration either with orwithout the extra switching modulation techniques.
According to simulation results, the following can be con-cluded.
1) Using ADCC instead of SDCC in the proposed hybridcascade converter can generate four more voltage levels inoutput voltage, which leads to better harmonic character-istics with the same number of components and switching.
2) By means of the first method of PWM (with extra switch-ing), although better THD can be achieved compared with
the second PWM method (without extra switching), extralosses should be taken into account.
3) The effect of extra losses or THD between the first andthe second method at higher switching frequency is negli-gible so that it shows the high performance of the pro-posed topology in this switching of such frequencies.However, at low switching frequencies, the first or thesecond method of switching could be selected based ondifferent applications.
V. CONCLUSION
This paper has presented the diode-clamped multilevel H-bridge cell cascaded with three-level conventional inverters toincrease efficiency of converters with high output voltage resolu-tion. A novel dc link voltage rating is proposed for the multileveldiode-clamped and three-level H-bridge inverters to improvethe output voltage and current quality by preserving the adja-cent switching vectors between all voltage levels. The MOBconverter has been applied as a dc link supplier of a diode-clamped inverter to boost and regulate the capacitors’ voltage tothe desired dc link rates. Using the MOB converter, a new cas-cade inverter is verified by cascading asymmetrical seven-levelH-bridge diode-clamped inverter. Inverter with nineteen outputvoltage levels performance was achieved, which has more volt-age levels as well as lower voltage, and current THD ratherthan using a symmetrical diode-clamped inverter with the sameconfiguration and equivalent number of power components. Pre-dictive current control was conducted to show the performanceof the proposed method. In this case, two different methods forthe switching states selection are proposed to minimize eitherlosses or THD of voltage in hybrid converters. Novel H-bridgecascaded cells will decrease the complexity of control and costof the system as well as diminish or remove the output filterswhen the configuration will be extended for more H-bridge cells.
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Alireza Nami (S’07) received the B.Sc. (Eng.) de-gree in electronic engineering and the M.Sc. degreein electrical engineering from Mazandaran Univer-sity, Babolsar, Iran, in 2004 and 2006, respectively.He is currently working toward the Ph.D. degree atthe School of Engineering Systems, Queensland Uni-versity of Technology, Brisbane, Qld., Australia.
He is currently a Research Assistant in the Schoolof Engineering Systems, Queensland University ofTechnology. His research interests include multi-level and dc–dc converters, new converter topologies,
pulsewidth modulation methods, and power electronics in renewable energysystems.
Firuz Zare (S’98–M’01–SM’06) received the B.E.degree in electronic engineering from Gilan Univer-sity, Gilan, Iran, in 1989, the M.S. degree in powerengineering from K. N. Toosi University, Tehran,Iran, in 1995, and the Ph.D. degree in power elec-tronics from Queensland University of Technology,Brisbane, Australia, in 2001.
He spent several years in industry as a teamleader and a development engineer, and was involvedin projects on electronics and power electronics. In2006, he joined Queensland University of Technol-
ogy, Brisbane, Qld., Australia, where he is currently a Senior Lecturer. He hasreceived three Australian Research Council grants collaborating with nationaland international research groups. He has authored or coauthored more than 52journal and conference papers and technical reports in the area of power elec-tronics. His current research interests include problem-based learning in powerelectronics, power electronics topologies and control, pulsewidth modulationtechniques, and electromagnetic compatibility (EMC)/electromagnetic interfer-ence in power electronics and renewable energy systems.
Dr. Zare won a student paper prize at the Australasian Universities Power En-gineering Conference in 2001 and was also awarded a Symposium Fellowshipby the Australian Academy of Technological Science and Engineering in 2001.He received Faculty Excellence Award in research as an early career academicfrom Queensland University of Technology in 2007. He presented a keynotetalk at the Annual Mathematics Symposium (Khayyam) in Iran in 2005. Hehas been invited as a reviewer and the technical chair for several national andinternational conferences, and has presented several seminars and workshops.He presented a half-day tutorial at the IEEE EMC Conference in Hawaii in June2007, the EMC Asia Pacific Workshop in Singapore in May 2008, and the IEEEEMC Conference in Detroit, MI, in August 2008.
NAMI et al.: HYBRID CASCADE CONVERTER TOPOLOGY 65
Arindam Ghosh (S’80–M’83–SM’93–F’06) re-ceived the Ph.D. degree in electrical engineering fromthe University of Calgary, Calgary, AB, Canada, in1983.
For 21 years, he was with the Department ofElectrical Engineering, Indian Institute of Technol-ogy Kanpur, India. In 2006, he joined QueenslandUniversity of Technology, Brisbane, Qld., Australia,where he is currently a Professor of power engineer-ing. His research interests include control of powersystems and power electronic devices.
Prof. Ghosh is a Fellow of the Indian National Academy of Engineering.
Frede Blaabjerg (S’86–M’88–SM’97–F’03) re-ceived the M.Sc. degree in electrical engineering fromAalborg University, Aalborg, Denmark, in 1987, andthe Ph.D. degree from the Institute of Energy Tech-nology, Aalborg University, in 1995.
From 1987 to 1988, he was with ABB-Scandia,Randers, Denmark. In 1992, he became an AssistantProfessor at Aalborg University, an Associate Pro-fessor in 1996, a Full Professor of power electronicsand drives in 1998, and has been the Dean of theFaculty of Engineering, Science and Medicine since
2006. He is involved in more than 15 research projects with the industry, andwas the Danfoss Professor Programme in Power Electronics and Drives. Heis the author or coauthor of more than 500 publications in his research fields,including the book Control in Power Electronics (Academic, 2002). Out ofthese, more than 300 papers are registered in IEEExplore with more than 130Institute of Scientific Information registered journal papers. His current researchinterests include power electronics, static power converters, ac drives, switchedreluctance drives, modeling, characterization of power semiconductor devicesand simulation, power quality, wind turbines, custom power systems, and greenpower inverters. He is an Associate Editor of the Journal of Power Electronicsand the Danish journal Elteknik.
Prof. Blaabjerg was appointed to the board of the Danish High Technol-ogy Foundation in 2007. He has also held a number of chairman positions inresearch policy and research funding bodies in Denmark. He is an AssociateEditor of the IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS and the IEEETRANSACTIONS ON POWER ELECTRONICS. He has been the Editor in Chief of theIEEE TRANSACTIONS ON POWER ELECTRONICS since 2006 and a DistinguishedLecturer for the IEEE Power Electronics Society since 2005. He received the1995 Angelos Award for his contribution to modulation technique and controlof electric drives and an Annual Teacher Prize at Aalborg University in 1995.In 1998, he received the Outstanding Young Power Electronics Engineer Awardfrom the IEEE Power Electronics Society. He has received nine IEEE PrizePaper Awards during the last ten years (the last in 2008) and a Prize PaperAward at Power Electronics and Intelligent Control for Energy ConservationPoland 2005. He received the C. Y. O’Connor Fellowship from Perth, Australia,in 2002, the Statoil Prize for his contributions in power electronics in 2003, andthe Grundfos Prize in acknowledgement of his international scientific researchin power electronics in 2004.
