ITRS ERD/ERM in KOREA

2

ITRS ERD/ERM Korean ChapterMemory Committee

Industry Academia

CommitteeI.-S. Yeo (Samsung)

S.W. Cheong (Hynix)

T.W. Kim (Sejong U)

H.C. Sohn (Yonsei U)

J.I. Hong (Yonsei U)

C.S. Hwang (Seoul Natl U)

H.S. Hwang (KJIST)

3

Memory Devices

Volatile Memory Non-volatile Memory

Polarizationchange

Charge Trap Resistance change

Classification of Memory Devices

DRAMSRAM

SONOSFLASH FRAM RRAM

Magneto-Resistancechanges

Phase-dependent Resistance changes

1

2’

2

V1V0

1’ “0””

I

oxide

Interface or bulk Resistancechanges

Charge-based Programming & Reading

Current-based Programming & Reading

MRAMPRAM

Ref.: Samsung

4

Nanomechanical

Memory

Fuse-

Antifuse

Memory

Ionic

Memory

Electronic

Effects

Memory

Macro-

molecular

Memory

Molecular

Memories

Storage

Mechanism

Electrostatically-

controlled

mechanical

switch

Multiple

mech.

Ion

transport

and

redox

reaction

Multiple

mechanisms

Multiple

mech.

Not

known

Cell

Elements1T1R or 1D1R

1T1R or

1D1R

1T1R or

1D1R

1T1R or

1D1R

1T1R or

1D1R

1T1R or

1D1R

Device

Types

1) Nanobridge /

cantilever

2) telescoping

CNT

3) Nanoparticle

M-I-M

(e.g.,

Pt/NiO/Pt)

1) cation

migration

2) anion

migration

1) Charge

trapping

2) Mott

transition

3) FE barrier

effects

M-I-M

(nc)-I-M

Bi-stable

switch

ITRS ERD/ERM (Emerging Memory)

Ref.: ITRS08

5

Next NVM Projects in Korea

Ref.: Ministry of Knowledge and Economy 2008. 06

Next Nonvolatile Memory Projects

1. Period: 2005~2011, 7 years2. Total Budget: 50.5B K₩ (42M US$, Exchange Rate=1200K₩ )

3. Focus on Developing New NVM for High Density Memory

3D

NFGM

J.H.Lee

(Kyungbuk U)

Nanodot,

3D- device

TBE

NFGM

W.J. Jo

(Kwangun U)

Tunel Barrier

Resistive

PoRAM

J.K. Park

(Hanyang U)

Organic,

Metal cluster

Ferro

FET

C.M. Park

(Yonsei U)

Organic/

Inorganic

FET

Chalcogenide

RAM

B.K. Jeong

(KIST)

Chalcogenide

Material

ReRAM

H.S. Hwang

(KJIST)

Cell,

Integration

Perpendicular

STT-MRAM

J.K. Park

(Hanyang U)

Planning

(will start ’09)

Supervision Hanyang Univ (J.K. Park)

NFGM STT-MRAMPoRAM ReRAM

6

Highly Reliable ReRAM !!

Binary oxideMultilayer

binary oxidePerovskitePMC

Material Develop

Materials RS Mechanism Memory cell Reliability / Uniformity Scalability (~50nm)

Cell array integration <100nm unit process 32 x 32 cell array Array characterization

Strategic Approach (ex.: ReRAM)

Epi-Oxide Charact.

Doped binary oxide

Modeling

FundamentalStudy

Unit cell & cell array develop (KJIST)

Industry:

Feedback,Tech. Support

Ref.: Hwang

7

Summary of current status (ReRAM)

ITEMMeasure Condition

1st screen Spec.

2nd Spec.Cu:MoOx

/GdOx

CuC

R.M/

LCMO(PCMO)

Switching

Isw Current @ Reset <1 mA <100 uA <300uA <300uA <100uA

VswVoltage @ Set, Reset <3.0 V <2.0 V <±2V <±1V <±3V

Roff/Ron

Roff @0.2V / Ron @0.2V >100 >1000 >1000@0.2V >100@0.1V >300@-1V

Distrib.

Vsw (Δ/σ)

Voltage @ Set, Reset (>30 point)

2.5 105.15(50samples)

8.3Hysteresis type

ΔR (@LogR) / σ (@LogR)

Ron, Roff @0.2V (>30 point)

5 209.4 (50samples)

4.9 >10

Reliab. Retention

On↔Off change after thermal stress (>30 point)

No Fail bit After125 /10 ℃h

No Fail bit after 85℃, 10 y

85 , ℃10 year(1-sample)

125 /℃>104sec(1-sample)

85 /℃>>104sec(1-sample)

Endurance 10 ms pulse >1E2 >1E4 >2E4 >1E3 >1E3AC Tsw Time Delay <10 uS <100 nS <1usec - <3usec

Cell Array - Number of Cell - -Nanoimprint 8X8 cell array

E-beam litho8X8 cell array

-

Nanoimprint 32x32 cell array

Sub 50nm Scale device

4 inch waferprocess

Unit cell process Mass production

Ref.: Hwang

8

Hybrid memory in dual layer

Cu:MoOx/GdOx stack Cu:MoOx/GdOx stack

• Schematic diagram

Filament switching

Ionic switching

• DC I-V sweep

-3 -2 -1 0 1 2 3

-300.0μ

-200.0μ

-100.0μ

0.0

100.0μ

200.0μ

-200.0

-300.0

-100.0

-4 -3 -2 -1 0 1 2 3 41E-7

1E-6

1E-5

1E-4

1E-3

0.01w/o GdOx layer

Cu

rren

t[A

]

Voltage[V]Reset

Set

Cur

rent

[uA

]

Voltage[V]

No switching for Pt/Cu:MoOx/Pt

Hysteretic bipolar switching

No Area dependence

Cycles >103 by DC

• Device performance

100 101 102 103 104 105

1E-7

1E-6

1E-5

1E-4

1E-31 0 0 1 2 0 1 4 0 1 6 0 1 8 0 2 0 0

1 E -7

1 E -6

1 E -5

1 E -4

Cu

rren

t[A]

# o f c y c le [N ]

2v, 1us, 0.2 read V

Cur

rent

[A]

# of cycle [N]100 101 102 103 104

1E-7

1E-6

1E-5

1E-4

Rlow

@85OC

Rhigh

@85OC

Rlow

@125OC

Rhigh

@125OC

Cur

rent

[A]

Retention time[S]

Cell Array

&4”

process

-3 -2 -1 0 1 2 3 40.1

1

10

40

70

95

99.5

AVR:1.352STD():0.469

VRESET VSET

Cum

ulat

ive

Posi

bilit

y[%

]

Voltage [V]

AVR:-0.794STD():0.313

∆ V=2.15

∆ V/σ=6.86

∆ V/σ=5.15

Ref.: Hwang

9

Redox / oxidation memory

Sm / LCMO stack Sm / LCMO stack

• Motivation • DC I-V sweep

• Device performance

Analysis ofSwitching mechanism

S. Muraoka et al, IEDM2007 Unity Semiconductor, US0171200

0 50 100 150 200

10-6

10-5

10-4

10-3

Set/Reset:-3/+3V

LCMO/Sm/Pt LCMO/SmN/Pt

Read V: -1.0V

Set/Reset(On/Off):100ms/1s

log

I [A

]

Number of pulse 102 103 104105

106

107

108

Read voltage:-0.5 V

Temperature: 85oC

LRS HRS

Res

ista

nce

[o

hm

]

Time [sec]

LCMO/Sm(15nm)/Mo

105 106 107 108 109 1010

10

100

R/=10Avr:8.91

STD():0.29

Cu

mu

lati

ve P

rob

abili

ty %

Log Res. [ohm]

LRS HRS

Read @ -1.0 V

R/=11.1Avr:5.99

STD():0.26

R=2.92

Ref.: Hwang

10

PMC memory

Cu-C memory Cu-C memory

• Motivation • Schematic diagram & DC I-V sweep

• Device performance

Improving

pulse switchin

g

<Problem> Low operation voltage Retention @ high temp

<Carbon> Porous Small radius

-1.0 -0.5 0.0 0.5 1.0

-200

-100

0

100

200

3

4

2

1

Cu

rren

t (

A)

Voltage (V)

1 10 100 1000 10000

10-6

10-5

10-4

read @ 100mV

Cur

rent

(A)

Retention (s)

Rhigh

@ 85oC Rhigh

@ 125oC

Rlow

@ 85oC Rlow

@ 125oC

Ref.: Hwang

11

Nanodevice using CuC (with Hynix)

1 10 100 1000

10-9

10-8

10-7

10-6

10-5

Cu

rren

t (A

)

# of pulse

LRS HRS

Set/Reset: +5V 10s/-2V 1sload resistor 10k @ Set operation

66nm

Wafer provided by Hynix-3 -2 -1 0 1 2 3 4 5 6

-250

-200

-150

-100

-50

0

50

100

150

4

3

2

Cu

rren

t (

A)

Voltage (V)

CuC/Cu60nm contact

1

40 45 50 55 60 65 7010-10

10-9

10-8

10-7

10-6

10-5

10-4

Cu

rren

t (A

)

diameter of contact (nm)

Cu/CuC read @ 100mV

• Schematic diagram • DC I-V sweep

• Pulse switching

Cu-C

Si sub

TiN W

Thermal oxide

NIT

TE

TiN

• Area dependence • Summary

materials CuC/Cu TE

type bipolar

Contact area 0.00176~0.00436μm2

On/off ratio >3 order

Set/Reset V +3/-2V

Pulse switching

+5V 10μs /-2V 1 μs

44nm58nm

Split 42~66nm

Ref.: Hwang

12

TEM Analysis on LRS/HRS spot

30 nmHRS

HRSLRSHRSHRS

PCMO

30 nm

10 nm

Element Weight% Atomic%

O K 7.91 23.52

Al K 35.57 62.70

Pt L 56.51 13.78

Totals 100.00

Element

1Weight% Atomic%

O K 42.51 57.53

Al K 50.32 40.38

Ca K 1.50 0.81

Mn K 1.71 0.67

Pr L 3.97 0.61

Totals 100.00

300k

10 nm

HRS – Robust AlOx EDX Analysis

PCMO

Pt

Pt

Pt

LRS

FIBMilling

Tilt

PtPt

PCMO

Pt

• Evidence for the switching models

Pt

• Interface sample for TEM analysis

OFF

Sm

LCMO

Mo

O 2 -

ON

AlOx

O 2 -

OFF

Al

PCMOO 2 -

ON

O 2 -

Pt

Oxidation

Reduction

Ref.: Hwang

13

Overview of ReRAM

Operation Principle (Unipolar) - Resistance Change by

Filament Formation/Rupture

- On-states When Filament Formed

- Off-states When Filament Rupture

Merits - Low-cost, Simple Processes

- Relatively Easy 3-D Stacking

Obstacles - Unclear Mechanism

- Use of Metastable Materials

Vbias

+

-

Vcell

+

-NiO

Electrode

Electrode

Oxide

Diode,ND

GND

VW

WL_0 WL_1 WL_2 WL_3

BL_3

BL_2

BL_1

BL_0

1st Layer

X-Dec

Y-D

ec

N-th Layer

Cross Point Array 3D Stacking

Strategy for Low-cost,High-density Memory

Ref.: Samsung

14

Summary

Why ReRAM?

• Scalability potential (No charge-limited) Operation at sub 20nm ??

• 4F2 Cross-point structure Requires Control Elements !!

• 3-D stacking Cost effective ??

Requirements for ReRAM• CMOS compatibility Non-noble electrode

• Control elements:

Diode for unipolar switching Enough drive current ??

Threshold switch (varistor) for bipolar switching Exist ??

• Multi-bit operation Requires large P/E window, very good distribution

Selection Rule for ReRAM ??