Magnetic Materials and Devices for MRAM Technology

7/30/2019 Magnetic Materials and Devices for MRAM Technology

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Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product

or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006. Eintell5503

TM

Magnetic Materials and Devicesfor MRAM Technology

Jon Slaughter


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TM Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product

or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006.

Slide 1

Outline

MRAM Overview 1st Generation Product Technology

Reliability

Applications

Scaling 90nm CMOS-node MRAM demonstration

Future directions Spin Transfer MRAM

Summary


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Slide 2

MRAM Advantages

Nonvolatile

Fast

Unlimited

Cycles

Flexible &

Robust

Data Retention 10 years

Symmetrical Read/Write35ns for 4Mb at 0.18m technology node

Endurance (>1015)Data stored by magnetic polarization

Integrated with Exist ing CMOS Baseline

Compatible with Embedded Designs

Highly Reliable


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Slide 3

Technology Comparison

Read Speed Fastest Fast Fast Fast Fast Fast

Write Speed Fastest Fast Slow Medium Medium Fast

Cell Density Low High High Medium High Med/HighNon-volatility No No Yes Yes Yes Yes

Endurance Unlimited Unlimited Limited Limited Limited Unlimited

Cell Leakage Low/High High Low Low Low Low

MRAMSRAM DRAM Flash FeRAM PRAM

High performance symmetrical read and write timing

Non-volatile with unlimited read-write endurance

Low leakage and low voltage operation

Easy integration for embedding in system-on-a-chip

Scalable for future generations


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Slide 4

1st Commercial MRAM

Freescale 4Mb MR2A16A

Now in volume production


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Slide 5

4Mb MRAM Memory Circuit

MR2A16A: 4 Mb Toggle MRAM 35ns Speed read/write speed

Unlimited Endurance

Date retention >>10 Years

256Kx16bit organization

3.3V single power supply

Fast SRAM pinout (center power

and ground) Commercial Temperature (0-70C)

RoHS Compliant TSOP type-II

package

Uses Freescale toggle-bittechnology


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Slide 6

MRAM Memory Cell

MagneticField

Isolation

Transistor

i

iFlux

concentratingcladding layer

Inlaid Copper

interconnects

Bit Line

DigitLin

e

MTJ


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Slide 7

MTJ Stack Key Parameter Summary

Top electrode Top Electrode (Ta)

Base electrodeMMT

AlOx

Seed

AF pinning layer

PinnedRu

Fixed

PtMn alloy

Composition tolerance 1%

Pinned SAF:Thickness uniformity


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Slide 8

4Mb Memory Cell

M5-BLVia1-4M1-3

N+

P-

Layer Name

N+ N+

M4-DL MVia BE TVia TETJ

N+ N+N+ N+

M1

M3

M2

M4-DL

V1

V2

V3

V4

MVia BE

TETJ TVia

M5-BL

Group SelectPass Xtor Pass Xtor ThkOxide

Xtor

i

i

Program pathfor Writing

information

Sense Path for

bit cell reading


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Slide 9

MRAM 4Mb bit cell

MRAM

module

Contact

Via 1

Metal 2

Via 2

Metal 4

Via 3

Metal 5

Metal 3

Bit cell

Metal 1

Cu

Cu

Al

Al

Al

MTJ

Metal 4

Metal 5

Front End

0.18 mCMOS


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Slide 10

Free Layer Field Response

H=0H=0Conventional Free Layer: switch

0

SAF Free layer: spin flop

H=0 0


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Slide 11

Toggle MRAM Switching Sequence

HardAxisHardAxisHardAxis

EasyAx isEasyAx isEasyAx is

Write

Line 2

Write

Line 1


EasyAxisEasyAxisEasyAxis

Write

Line 2

Write

Line 1



Write

Line 2



Write

Line 2



Write

Line 2

Write

Line 1

Write Line 1

Write Line 2

t0 t1 t2 t3 t4

Off

On

Off

H1

I 1

H2

I 2

H1

I 1

H2

I 2

Write

Line 1

Write

Line 1

On


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Slide 12

Toggle-Bit Selection

High bit disturb marginAll bits along -selected

current lines have

increased energy barrierduring programming

ToggleToggle


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Slide 13

Measured Switching from 4Mb Toggle-MRAM

ibit

idigit

Operating

region

0% switching region

(no disturbs)

No -select disturbs

Large operating region

4Mb, March 6N Toggle Map

Conventional MRAM

ibit

idigit

ibit

idigit

Operating

region

Conventional MRAM

ibit

idigit

ibit

idigit

Operating

region


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Slide 14

Tunnel Junction Reliability: Read

Low

StateHigh

State

Necessary

margin for

spec. read-out speed

Margin before

drift

Margin

after

driftNumberofBits@R

Bit Resistance1 10 100 1000 10000 100000

0

1000

2000

3000

4000

5000

6000

7000

0.6V

0.8V1.0VT=175 C

Resistan

ce[]

Time [s]

1) Dielectric Breakdown (catastrophic) 2) Resistance Drift (gradual)

MRAM TDDB


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Slide 15

MRAM TDDB

1.102 175

1.151 175

1.201 150

1.201 175

1.246 175

1.251 125

1.251 150

1.287 175

1.298 150

1.301 125

1.00000.10000.01000.00100.0001

99

95

90

80

7060

50

40

30

20

10

5

3

2

1

Hours

Percent

~27x/0.1VEa: 1.21 eV

Slope:1

.86

125C, 150C, 175C

1.1V 1.3V

9 TDDB Reliabili ty far exceeds 10 years at operating voltage.


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Slide 16

Resistance drift vs. bias

0.1 1 10 100 10000.80

0.85

0.90

0.95

1.00

Rnormalized

0.6V

0.7V0.8V

0.9V

1.0V T=120C

Time [min]

R generally decreases over time

more at high bias/high T

R drift wil l cause bits to fail over

time adds to R distribution

Distribution of R drift very tight all

bits drift with a very similar rate

9 Worst case drift is less


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Slide 17

Resistance drift scaling

0.1 1 10 100 10000.80

0.85

0.90

0.95

1.00

Rnormalized

0.6V

0.7V0.8V

0.9V

1.0V T=120C

Time [min]

1E-41E-3 0.01 0.1 1 10 100 10000.80

0.85

0.90

0.95

1.00

25% d.c

-1%

100% d.c

-2.2%

0.6V t/t*=25000.7V t/t*=400

0.8V t/t*=50

0.9V t/t*=6.5

1.0V t/t*=1

Rnorm

alized

Time [min]

Increasing bias shifts curve along logt axis

curves overlap when time axis is rescaled

Bias stress is a true accelerator

speeds up drift mechanism

does not introduce new mechanism

Scaling factort* can be used for extrapolations

0.00 0.25 0.50 0.75 1.00 1.250.01

0.1

1

10

100

1000

10000

100000

1000000

1E7

3*106

ScalingFactor

Bias [V]

10 years at 0.25V

1.75 min at 1V

4Mb MRAM T t d R li bilit


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Slide 18

4Mb MRAM Tested Reliability

TDDB and Drift Lifetimes, 90% LCL

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

1.E+08

1.E+09

1.E+10

1.E+11

1.E+12

50 60 70 80 90 100

Usage Temp (C)

1FITDrift,TDDBLife(hrs)

IntrinsicTDDB

4MbArrayDriftLife

10 Year Reliability

Junction Temperature (C)

TDDB and Drift Lifetimes, 90% LCL

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

1.E+08

1.E+09

1.E+10

1.E+11

1.E+12

50 60 70 80 90 100

Usage Temp (C)

1FITDrift,TDDBLife(hrs)

IntrinsicTDDB

4MbArrayDriftLife

10 Year Reliability

Junction Temperature (C)

E B i f N l til D t R t ti


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Slide 19

Energy Barrier for Nonvolatile Data Retention

= Eb/ kbT

Thermal energy can cause

bit flip if barrier too low

10-year data retention > 70 required for 1 FITquality

> 1 FIT = 1 error in 10,000

parts in 10 yrs

E

E

0

Eb

E

0 1

0

kbT

Th l ti ti i li d fi ld D t t ti


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Slide 20

Thermal activation in zero applied field Data retention

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

150 170 190 210 230 250

temp (C)

tim

eattemp(sec)

boundary for 1 failure measured data with NO failures

)1( 00

e

t

eNN

=

Theoretical curve of time to

observe 1 state change in 500

4Mb parts versus measurement

temperature with an = 70 @

85C

N = number of flipped bits

N0 = Total number of bits in samplet = time at temperature

0 = attempt time

= magnetic energy barrier divided by kbT

Measured data for time with

NO observed state changes in

500 4Mb parts

Over 3000 4Mb parts tested in total with no observed thermally induced state

changes indicating all bits in sample have >> 70


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Slide 21

Markets and Applications

Standalone and Embedded

Example: Battery backed SRAM Replacement


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Slide 22

Example: Battery-backed SRAM Replacement

MRAM: single chip solution

MCU

SRAM

Battery

Addr/Data Bus

Control

Chip

CE

MRAM

Problems Multiple parts required System design complexity Board space and weight

Battery contact failure Limited life Manufacturing complexity Environmental concerns

Benefits Single chip solution Simple system design Small profile

No battery Unlimited life Manufacturing

simplification

Environmentally friendly

Example: RAID Storage


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Slide 23

Example: RAID Storage

The Application Redundant Array of Inexpensive Disks (RAID 0-7 & Hybrids)

RAID systems are found in Imaging, Video, Audio, Web sites, emerging multimedia programs,

transaction processing systems, mission critical backup solutions for Hospitals, Police,

Banking and Insurance firms have ever increasing needs for high transfer rates and storage

capacity.

Address Vectors & System Configuration Disk Error Recovery

MRAM Improves Performance Fast read & write of 35ns No erase before write improves speed

Unlimited read & writes practically inf inite cycles Byte writeable greater granularity Non volatile memory increase security & integrity of

data Fail Safe RAID cache High Data Availability without BBSRAM difficulties

Critical Cache

Configuration

Data

RAID Journal

RAIDContr

ollerChip

Disk Arrays

RAID

Controller

Embedded MRAM


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Slide 24

Embedded MRAM

Uses standard CMOS MRAM can be readily inserted between two existinglevels of metal

Insertion does not change underlying CMOS parameters

Provides smaller die size,performance improvement anddesign flexibility

LogicLogic

Logic

DSPSRAM/NVM

ROM

SRAM

SRAM

Logic MRAM

Die Size =1 Die Size =0.8 Converged Memory

MRAM

Logic

LogicMRAM

MRAM

MRAM

Logic


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Slide 25

Scaling Toggle MRAM

90 nm CMOS Demonstration

MR for MgO/NiFe MTJ Material


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Slide 26

MR for MgO/NiFe MTJ Material

0

20

40

60

80

100

1 10 100 1000

Rcell (k )

M

R(%)

265oC

300oC

350oC

Rcell (k)

MR>90% Highest reported for NiFe

2X higher than with AlOx

Can adjust MgO thicknessto optimize resistance overbroad range

350 C post-anneal neededfor full MR ~270 C for AlOxBase electrode

MgO

Pinning

Ru

Top electrode

NiFeRu

NiFe

Base electrode

MgO

Pinning

Ru

Top electrode

NiFeRu

NiFe

Base electrode

MgO

Pinning

Ru

Top electrode

NiFeRu

NiFe

MRAM Cell Integration in 90nm BEOL


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Slide 27

MRAM Cell Integration in 90nm BEOL

90nmCM

OS

MRAM

0.29m2BitCell

Full integration of MgO-basedMRAM devices with 90nm front

end CMOS.

MRAM process with clad Cu

write lines.

8 kb arrays of memory cells

Cell Size 0.29 m2

Linear shrink from 180nm

MTJ resistance of 1kohm-m

2

Toggle write characteristics

90nm MRAM Read/Write Endurance


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Slide 28

90nm MRAM Read/Write Endurance

State 1

State 0 Read 0

Write 1

Read 0

Write 1

Read 1

Write 0

Data

Out

WriteControl

Read

Control

Passed >1e12 read/write cycles test

Breakdown of MgO/NiFe MTJ Bits


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Slide 29

Breakdown of MgO/NiFe MTJ Bits

RA (kOhm*um^2)

Break

downVoltage[V]

101

2.2

2.0

1.8

1.6

1.4

Barrier

AlOxMgO

RA (k-m2)BreakdownVolta

ge(V)

Vbd [V]

P

ercent[%]

2.22.12.01.91.81.71.61.51.4

99

95

90

80

7060504030

20

10

5

1

Barrier = MgOGaussian Probability Plot of Vbd

MgO barrier consistently

higher Vbd for given RA

0.15V improvement ~ 10-100x longer life

Vbd distributions are widerthan for AlOx material

=2.3%

Toggle MRAM Scaling


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Slide 30

Toggle MRAM Scaling

15ns / 15ns

> e^15

32 Mbit

< 0.8mm2/Mb

0.044m2

0.29m2

90nm (projected)

25ns / 25ns

> e^15

4Mbit

7.1mm2/Mb

0.28m2

1.26m2

0.18m

Read/Write Endurance

Access time read/write

Memory size / density

Magnetic bit size

Cell size

MRAM Technology

Scaling Summary


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Slide 31

g y

Demonstrated integration of MgO-based MTJ material MR>90% with NiFe SAF free layer for toggle MRAM> Highest MR ever reported with NiFe

Critical MgO material properties evaluated Bias dependence similar to AlOx

Breakdown voltage higher than AlOx (good reliability expected)

Demonstrated 0.29m cell in 90 nm CMOS with MgO Indicates capability to make and integrate high-MR material for

high-speed MRAM at 256Mb densities


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Slide 32

Future Directions

Spin Transfer Switching

Standard vs. Spin Transfer MRAM


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Slide 33

p

bit linewrite current

magnetic

tunnel junction

digit linewrite current

H-field

H-field

Isolationtransistor

Cross-point architecture

Current along bit line and digit line to

switch at intersection

free magnet

fixed magnet

tunnel barrier

IDC

Isolationtransistor

SMT MRAMStandard MRAM

Current IDC flows through MTJ and transistor Fixed magnet polarizes IDC Spin-transfer torque programs free magnet

Conservation of angular momentum

Spin Transfer MRAM Processing


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Slide 34

p g

CoFeB free layer MgO barrier

Low RA ~ 5 m2

MR ~ 100%

Conventionalphotolithographic patterning 0.1 m 0.17 m bits 200 mm wafer

~0.5 mA critical currents 5 - 15% within die 1-sigma

switching distribution width

0

5

10

15

20

25

0 5 10 15 20 25

Die num ber

Vwriterelative(

%) Low

High

(b

12

8

4

0Frequ

ency(arb.units)

1.00.50.0-0.5-1.0

Vwrite (V)

LowHigh(c

0.1

-0.9

-0.6

-0.3

0

0.3

0.6

0.9

0 2 4 6 8 10 12

Wafer num ber

Iwrit

e

(mA)

Low

High

(a

Prospects for Spin Transfer MRAM


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Slide 35

Advantages: High density Stable bits with modest switching current ( < 1mA)

High speed

No neighboring or -select disturbs

Switching current decreases with bit area

Challenges: Write current flows through MTJ itself

> Reliability

> Need to reduce critical currents to use minimum sized transistor

MRAM Summary


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Slide 36

First commercial MRAM product in industry 4Mb MRAM with 35ns read/write access time Enabled by advancement in MTJ material and Toggle Write

Only memory technology today with characteristics of non-volatility, fast read/write, and unlimited endurance

Reliability has been demonstrated to exceed all other existingnonvolatile memories

No fatigue mechanism observed Ease of integration ideal for embedded spaceAdds new functionality to SOC applications

Integration at backend provides process compatibility andflexibility

Demonstrated scalability


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Magnetic Materials and Devices for MRAM Technology

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