Remote Type 8-bit MCU HT48RA0-6 - Holtek...POR to ensu e Powe -on Reset — — 1 ms ˜˚ ˛˝ ˙...

Remote Type 8-bit MCU

HT48RA0-6

Revision: V1.20 Date: �a�� 2�� 201��a�� 2�� 201�

Rev. 1.20 2 �a�� 2�� 201� Rev. 1.20 3 �a�� 2�� 201�

HT48RA0-6Remote Type 8-bit MCU


Table of Contents

Features ............................................................................................................ 4General Description ........................................................................................ 4Block Diagram .................................................................................................. 5Pin Assignment ................................................................................................ 5Pin Description ................................................................................................ 6Absolute Maximum Ratings ............................................................................ 6D.C. Characteristics ......................................................................................... 7A.C. Characteristics ......................................................................................... 7Power-on Reset Characteristics ..................................................................... 8Characteristics Curves .................................................................................... 8

HIRC Os�illato� Voltage/Tempe�atu�e vs. F�equen�y .............................................................. 8IR Sink Cu��ent vs. VDD ......................................................................................................... 9

Functional Description .................................................................................. 10Exe�ution Flow ...................................................................................................................... 10P�og�am Counte� – PC .......................................................................................................... 10P�og�am �emo�y - RO� ........................................................................................................11Sta�k ..................................................................................................................................... 12Data �emo�y – RA� ............................................................................................................. 12Indi�e�t Add�essing Registe� ................................................................................................. 13A��umulato� .......................................................................................................................... 13A�it�meti� and Logi� Unit – ALU ........................................................................................... 1�Status Registe� – STATUS .................................................................................................... 1�Oscillator Configuration ......................................................................................................... 1�Exte�nal C�ystal/Ce�ami� Os�illato� – HXT ........................................................................... 15Inte�nal RC Os�illato� – HIRC ............................................................................................... 15Wat��dog Time� – WDT ........................................................................................................ 15Powe� Down Ope�ation – HALT ............................................................................................ 1�Reset ..................................................................................................................................... 17Input/Output Po�ts ................................................................................................................. 19Time� ..................................................................................................................................... 20Time� Ope�ation .................................................................................................................... 20Ca��ie� Output ....................................................................................................................... 22Low Voltage Reset – LVR ..................................................................................................... 25

Configuration Options ................................................................................... 26Application Circuits ....................................................................................... 27

Rev. 1.20 2 �a�� 2�� 201� Rev. 1.20 3 �a�� 2�� 201�



Instruction Set ................................................................................................ 29Int�odu�tion ........................................................................................................................... 29Inst�u�tion Timing .................................................................................................................. 29�oving and T�ansfe��ing Data ............................................................................................... 29A�it�meti� Ope�ations ............................................................................................................ 29Logi�al and Rotate Ope�ation ............................................................................................... 30B�an��es and Cont�ol T�ansfe� ............................................................................................. 30Bit Ope�ations ....................................................................................................................... 30Table Read Ope�ations ......................................................................................................... 30Ot�e� Ope�ations ................................................................................................................... 30

Instruction Set Summary .............................................................................. 31Table Conventions ................................................................................................................. 31

Instruction Definition ..................................................................................... 33Package Information ..................................................................................... 42

1�-pin NSOP (150mil) Outline Dimensions ........................................................................... �320-pin SSOP (150mil) Outline Dimensions ........................................................................... ��

Rev. 1.20 � �a�� 2�� 201� Rev. 1.20 5 �a�� 2�� 201�



Features• Operatingvoltage:–fSYS=4MHzatVDD=2.0V~3.6V(LVRenabled)–fSYS=4MHzatVDD=1.8V~3.6V(LVRdisabled)

• Oscillatortypes:–ExternalhighfrequencyCrystal–HXT–InternalhighfrequencyRC–HIRC

• 1K×14programmemory

• 32×8datamemory

• One-levelsubroutinenesting

• 16bidirectionalI/Olines

• Fullyintegratedinternal4095kHzoscillatorrequiresnoexternalcomponents

• Oneprogrammablecarrieroutput-using9-bittimer

• Carrieroutputpin(REM/REMDRV)

• Build-inIRDriver([email protected])

• WatchdogTimer

• Lowvoltageresetfunction

• Power-downandwake-upfeaturesreducepowerconsumption

• 14-bittablereadinstructions

• Upto1μsinstructioncyclewith4MHzsystemclock

• 63powerfulinstructions

• Allinstructionsexecutedin1or2machinecycles

• Bitmanipulationinstructions

• 16-pinNSOPand20-pinSSOPpackages

• HT48RA0-6BuseininternalIRdriver

General Description TheHT48RA0-6is8-bithighperformance,RISCarchitecturemicrocontrollerdevicespecificallydesignedformultipleI/Ocontrolproductapplications.

Theadvantagesoflowpowerconsumption,I/Oflexibility,timerfunctions,watchdogtimer,HALTandwake-upfunctions,aswellaslowcost,enhancetheversatilityofthisdevicetosuitawiderangeofapplicationpossibilitiessuchasindustrialcontrol,consumerproducts,andparticularlysuitableforuseinproductssuchasinfraredremotecontrollersandvarioussubsystemcontrollers.

Rev. 1.20 � �a�� 2�� 201� Rev. 1.20 5 �a�� 2�� 201�



Block Diagram

� � � � ��

� � � � � � � ��

� � � � ��

� � � � � � ��

� � � � � � ��

� � � � ��

� � � ��

� � � � � � � � � � � ��

� � � � � � � � � ��

� � � �

� � � � � � � � � ��

� � ��

Pin Assignment

� � ��

� � ��

� � � � � � � � � ��

� � ��

� ��

��

� � � � � � � � � ��

� � � � � � � � � ��

� � ��

� � � � � � ��

� � � � � � � ��

� � � � �

� � � � � � � � � ��

� ��

��

Rev. 1.20 � �a�� 2�� 201� Rev. 1.20 7 �a�� 2�� 201�



Pin Description

Pin Name I/O ConfigurationOption Description

PA0~PA7 I/O —Bidi�e�tional 8-bit input/output po�t wit� pull-�ig� �esisto�s. Softwa�e inst�u�tions dete�mine if t�e pin is an N�OS output o� S��mitt T�igge� input. Each pin can have a wake-up function if configured as an input pin.

PB0~PB3PB5/OSC2PB�/OSC1PB7

I/O OSC

Bidi�e�tional 7-bit input/output po�t wit� pull-�ig� �esisto�s. Softwa�e inst�u�tions dete�mine if t�e pin is an N�OS output o� S��mitt T�igge� input. Each pin can have a wake-up function if configured as an input pin. PB5 and PB� a�e pin-s�a�ed wit� t�e exte�nal ��ystal pins named OSC2 and OSC1 respectively determined by a configuration option.

PC0/RES ST RES

Bidi�e�tional 1-bit input/output po�t wit�out a pull-�ig� �esisto�. Softwa�e inst�u�tions dete�mine if t�e pin is an N�OS output o� S��mitt T�igge� input. This pin has the capability of wake-up when it is configured as an input pin. PC0 is pin-s�a�ed wit� t�e exte�nal �eset pin named RES determined by a configuration option.

RE�/RE�DRV O RE�/RE�DRV

Ca��ie� output dual fun�tion pin. RE� is a C�OS �a��ie� output pin wit� an initial low level afte� a �eset. RE�DRV pin is a �ig� sink �u��ent N�OS open drain carrier output pin which will be in a floating condition afte� a �eset. T�e sele�tion of RE� o� RE�DRV is dete�mined by a configuration option.

VDD — — Positive powe� supply

VSS — — Negative powe� supply� g�ound

VSS1 — — Negative powe� supply� g�ound of RE�/RE�DRV pin.

Absolute Maximum RatingsSupplyVoltage................................................................................................VSS−0.3VtoVSS+4.0VInputVoltage..................................................................................................VSS−0.3VtoVDD+0.3VStorageTemperature....................................................................................................-50˚Cto125˚COperatingTemperature..................................................................................................-20˚Cto70˚CIOHTotal..................................................................................................................................-100mAIOLTotal................................................................................................................................... 150mATotalPowerDissipation........................................................................................................ 500mW

Note:Thesearestressratingsonly.Stressesexceedingtherangespecifiedunder"AbsoluteMaximumRatings"maycausesubstantialdamagetothesedevices.Functionaloperationofthesedevicesatotherconditionsbeyondthoselistedinthespecificationisnotimpliedandprolongedexposuretoextremeconditionsmayaffectdevicesreliability.

Rev. 1.20 � �a�� 2�� 201� Rev. 1.20 7 �a�� 2�� 201�



D.C. CharacteristicsTa= 25˚C

Symbol ParameterTest Conditions

Min. Typ. Max. UnitVDD Conditions

VDD Ope�ating Voltage —LVR disable 1.8 ─ 3.� V

LVR enable 2.0 ─ 3.� V

IDD Ope�ating Cu��ent 3V No load� fSYS=��Hz ─ 0.7 1.5 mA

ISTB1 Standby Cu��ent 3V No load� system HALT� WDT disable ─ 0.1 1.0 μA

ISTB2 Standby Cu��ent 3V No load� system HALT� WDT enable ─ ─ 5.0 μA

VIL1 Input Low Voltage fo� I/O Po�ts — — 0 ─ 0.2VDD V

VIH1 Input Low Voltage fo� I/O Po�ts — — 0.8VDD ─ VDD V

VIL2 Input Low Voltage(RES) — — 0 ─ 0.�VDD V

VIH2 Input Low Voltage(RES) — — 0.9VDD ─ VDD V

IOH RE� Output Sou��e Cu��ent 3V VOH=0.9VDD -5 -7 ─ mA

IOL1 PA� PB� RE� Output Sink Cu��ent 3V VOL=0.1VDD � 12 ─ mA

IOL2 PC0 Sink Cu��ent 3V VOL=0.1VDD 0.8 1.2 ─ mA

IOL3 RE�DRV Output Sink Cu��ent 3V VOL=0.�VDD 300 330 ─ mA

RPH Pull-�ig� Resistan�e of Po�t A�Po�t B 3V — 100 150 200 kΩ

VLVR Low Voltage Reset Voltage — — 1.8 1.9 2.0 V

A.C. CharacteristicsTa= 25˚C


Min. Typ. Max. UnitVDD Condition

fSYS System Clo�k 1.8V~3.�V Ta= -20°C~70°C �00 ─ �000 kHz

fHIRC System Clo�k (HIRC) 2.2V~3.�V Ta= -10°C~50°C -1% �095 +1% kHz

tSST System Sta�t-up Time� Pe�iod ─ Powe�-up o� wake-upf�om HALT ─ 102� ─ tSYS

tWDTOSC Wat��dog Os�illato� 3V ─ �5 90 180 μs

tLVR Low Voltage Widt� to Reset ─ ─ 0.25 1.00 2.00 ms

Note:1.tSYS=1/fSYS

Rev. 1.20 8 �a�� 2�� 201� Rev. 1.20 9 �a�� 2�� 201�



Power-on Reset CharacteristicsTa= 25˚C


Min. Typ. Max. UnitVDD Conditions

VPOR VDD Sta�t Voltage to Ensu�ePowe�-on Reset — — — — 100 mV

RRVDD VDD Raising Rate to Ensu�e Powe�-on Reset — — 0.035 — — V/ms

tPOR�inimum Time fo� VDD Stays at VPOR to ensu�e Powe�-on Reset — — 1 ─ ─ ms

� � � �

� � �

� � � �

� � � � ��

Characteristics Curves

HIRC Oscillator Voltage/Temperature vs. Frequency

HIRC Curve

4000

4050

4100

4150

4200

2.0 2.5 3.0 3.6

VDD (V)

Freq

uenc

y (k

Hz)

4095kHz +1%

-25°C

25°C

75°C

4095kHz -1%

Rev. 1.20 8 �a�� 2�� 201� Rev. 1.20 9 �a�� 2�� 201�



IR Sink Current vs. VDD

IR Driver Curve Ta=25℃

0

100

200

300

�00

500

�00

700

800

1.8 2.0 2.2 2.� 2.� 2.8 3.0 3.2 3.� 3.� 3.8

VDD (V)

REM

Sin

k C

urre

nt (m

A)

Rev. 1.20 10 �a�� 2�� 201� Rev. 1.20 11 �a�� 2�� 201�



Functional Description

Execution FlowThemainsystemclock isderived fromeitheranexternalcrystaloscillatorwhichrequires theconnectionof theexternalcrystalor resonatororan internalRCoscillatorwhich requiresnoexternalcomponentforitsoperation.Itisinternallydividedintofournon-overlappingclocks.Oneinstructioncycleconsistsoffoursystemclockcycles.

Instructionfetchingandexecutionarepipelinedinsuchawaythatafetchtakesoneinstructioncyclewhiledecodingandexecutiontakesthenextinstructioncycle.However,thepipeliningschemecauseseachinstructiontoeffectivelyexecutewithinonecycle.Ifaninstructionchangestheprogramcounter,twocyclesarerequiredtocompletetheinstruction.

Program Counter – PCThe10-bitprogramcounter(PC)controlsthesequenceinwhichtheinstructionsstoredinprogrammemoryareexecutedanditscontentsspecifyamaximumof1024addresses.

Afteraccessingaprogrammemorywordtofetchaninstructioncode,thecontentsoftheprogramcounterareincrementedbyone.Theprogramcounterthenpointstothememorywordcontainingthenextinstructioncode.

Whenexecutinga jumpinstruction,conditionalskipexecution, loadingPCLregister,subroutinecall,initialresetorreturnfromsubroutine,thePCmanipulatestheprogramtransferbyloadingtheaddresscorrespondingtoeachinstruction.

Theconditionalskip isactivatedbyinstruction.Once thecondition ismet, thenext instruction,fetchedduringthecurrentinstructionexecution,isdiscardedandadummycyclereplacesittogettheproperinstruction.Otherwiseproceedwiththenextinstruction.

Thelowerbyteoftheprogramcounter(PCL)isareadableandwriteableregister(06H).MovingdataintothePCLperformsashortjump.Thedestinationwillbewithin256locations.

Whenacontroltransfertakesplace,anadditionaldummycycleisrequired.

� � � � � � � � � � � � � � � � � � � � � � � �

� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �

� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �

� � � � � � � �

� � � � � � � � � � � �

� � � � � � � � � � � � � � � � �

� �

Execution Flow

Rev. 1.20 10 �a�� 2�� 201� Rev. 1.20 11 �a�� 2�� 201�



ModeProgram Counter

*9 *8 *7 *6 *5 *4 *3 *2 *1 *0Initial �eset 0 0 0 0 0 0 0 0 0 0Skip P�og�am Counte� + 2Loading PCL *9 *8 @7 @� @5 @� @3 @2 @1 @0Jump� �all b�an�� #9 #8 #7 #� #5 #� #3 #2 #1 #0Retu�n f�om sub�outine S9 S8 S7 S� S5 S� S3 S2 S1 S0

Program Counter

Note:*9~*0:ProgramcounterbitsS9~S0:Stackregisterbits#9~#0:Instructioncodebits@7~@0:PCLbits

Program Memory - ROMTheprogrammemoryisusedtostore theprograminstructionswhichare tobeexecuted.Italsocontainsdataandtableandisorganizedinto1024×14bits,addressedbytheprogramcounterandtablepointer.

Certainlocationsintheprogrammemoryarereservedforspecialusage:

• Location000HThisarea is reservedfor the initializationprogram.Afteradevicereset, theprogramalwaysbeginsexecutionatlocation000H.

• TablelocationAnylocationin theProgramMemoryspacecanbeusedasa look-uptable.TheinstructionsTABRDC[m](thecurrentpage,onepage=256words)andTABRDL[m](thelastpage)transferthecontentsofthelower-orderbytetothespecifieddatamemoryregister,andthehigher-orderbytetoTBLH(08H).Onlythedestinationofthelower-orderbyteinthetableiswell-defined,theotherbitsofthetablewordaretransferredtothelowerportionofTBLH,theremaining2bitsarereadas“0”.TheTableHigher-orderbyteregister(TBLH)isreadonly.Thetablepointer(TBLP)isaread/writeregister(07H),wherePindicatesthetablelocation.Beforeaccessingthetable,thelocationmustbeplacedinTBLP.TheTBLHisreadonlyandcannotberestored.Alltablerelatedinstructionsneed2cyclestocompletetheoperation.Theseareasmayfunctionasnormalprogrammemorydependingupontherequirements.

� � � ��

� � � � � �

� � � � �

� � � � � � � � � � � � � � � � � � � � � � �

� � � �

� � � � � � � � � � � � � � � � � � � � � � ��

� � � � � � � � � � � � � � � � � � � � � � �

� � � �

Program Memory

Rev. 1.20 12 �a�� 2�� 201� Rev. 1.20 13 �a�� 2�� 201�



InstructionTable location

*9 *8 *7 *6 *5 *4 *3 *2 *1 *0

TABRDC [m] P9 P8 @7 @� @5 @� @3 @2 @1 @0

TABRDL [m] 1 1 @7 @� @5 @� @3 @2 @1 @0

Table Location

Note:*9~*0:TablelocationbitsPC9~PC8:CurrentProgramCounterbits@7~@0:TablePointerbits

StackThisisaspecialpartofthememorywhichisusedtosavethecontentsoftheProgramCounteronly.Thestackisorganizedintoonelevelandneitherpartof thedatanorpartof theprogramspace,andisneitherreadablenorwriteable.Theactivatedlevel is indexedbytheStackPointer,andisneitherreadablenorwriteable.Atasubroutinecallorinterruptacknowledgesignal,thecontentsoftheProgramCounterarepushedontothestack.Attheendofasubroutineoraninterruptroutine,signaledbyareturninstruction,RETorRETI,theProgramCounterisrestoredtoitspreviousvaluefromthestack.Afteradevicereset,theStackPointerwillpointtothetopofthestack.

Ifthestackisfullanda"CALL"issubsequentlyexecuted,stackoverflowoccursandthefirstentrywillbelostandonlythemostrecentreturnaddressisstored.

Data Memory – RAMThedatamemory isdivided into twofunctionalgroups:special functionregistersandgeneralpurposedatamemory(32×8).Mostareread/write,butsomearereadonly.

The remainingspacebefore the20H is reserved for futureexpandedusageand reading theselocationswill return theresult00H.Thegeneralpurposedatamemory,addressedfrom20Hto3FH,isusedfordataandcontrolinformationunderinstructioncommand.Alldatamemoryareascanhandlearithmetic,logic,increment,decrementandrotateoperationsdirectly.Exceptforsomededicatedbits,eachbit in thedatamemorycanbesetandresetbytheSET[m].iandCLR[m].i instructions, respectively.Theyarealso indirectlyaccessible throughmemorypointerregister(MP;01H).

Rev. 1.20 12 �a�� 2�� 201� Rev. 1.20 13 �a�� 2�� 201�



� � � � � � � � � � � � � � ��

� ��

� � � � ��

� � � � � �

� �

� �

�

� � � ��

� � � � � � � � � � � � � � ��

� � � � � � � �

� � � � � � � � � � � � �

� � ��

� � �

RAM Mapping

Indirect Addressing RegisterLocation00Hisanindirectaddressingregisterthatisnotphysicallyimplemented.Anyread/writeoperationto[00H]accessesthedatamemorypointedtobyMP(01H).Readinglocation00Hitselfindirectlywillreturntheresult00H.Writingindirectlyresultsinnooperation.

ThememorypointerregisterMP(01H)isa7-bitregister.Bit7ofMPisundefinedandreadingwillreturntheresult“1”.AnywritingoperationtoMPwillonlytransferthelower7-bitsofdatatoMP.

AccumulatorTheaccumulatorcloselyrelatestoALUoperations.It isalsomappedtolocation05Hofthedatamemoryandiscapableofcarryingoutimmediatedataoperations.Datamovementbetweentwodatamemorylocationshastopassthroughtheaccumulator.

Rev. 1.20 1� �a�� 2�� 201� Rev. 1.20 15 �a�� 2�� 201�



Arithmetic and Logic Unit – ALUThiscircuitperforms8-bit arithmeticand logicoperation.TheALUprovides the followingfunctions.

• Arithmeticoperations(ADD,ADC,SUB,SBC,DAA)

• Logicoperations(AND,OR,XOR,CPL)

• Rotation(RL,RR,RLC,RRC)

• IncrementandDecrement(INC,DEC)

• Branchdecision(SZ,SNZ,SIZ,SDZ....)

TheALUnotonlysavestheresultsofadataoperationbutalsochangesthecontentsofthestatusregister.

Status Register – STATUSThis8-bitstatusregister(0AH)containsthezeroflag(Z),carryflag(C),auxiliarycarryflag(AC),overflowflag(OV),powerdownflag(PDF)andwatchdogtime-outflag(TO).Italsorecordsthestatusinformationandcontrolstheoperationsequence.

With theexceptionof theTOandPDF flags, theother status registerbitscanbealteredbyinstructionslikemostotherregister.AnydatawrittenintothestatusregisterwillnotchangetheTOorPDFflags.Inadditionitshouldbenotedthatoperationsrelatedtothestatusregistermaygivedifferentresultsfromthoseintended.TheTOandPDFflagscanonlybechangedbytheWatchdogTimeroverflow,devicepower-up,clearingtheWatchdogTimerandexecutingtheHALTinstruction.

TheZ,OV,ACandCflagsgenerallyreflectthestatusofthelatestoperations.

Inaddition,onexecutingasubroutinecall,thestatusregisterwillnotbeautomaticallypushedontothestack.If thecontentsof thestatusare importantandif thesubroutinecancorrupt thestatusregister,precautionsmustbetakentosaveitproperly.

Bit No. Label Function

0 CC is set if t�e ope�ation �esults in a �a��y du�ing an addition ope�ation o� if a bo��ow does not take pla�e du�ing a subt�a�tion ope�ation; ot�e�wise C is �lea�ed. C is also affe�ted by a �otate t��oug� �a��y inst�u�tion.

1 ACAC is set if t�e ope�ation �esults in a �a��y out of t�e low nibbles in addition o� no bo��ow f�om t�e �ig� nibble into t�e low nibble in subt�a�tion; ot�e�wise AC is �lea�ed.

2 Z Z is set if t�e �esult of an a�it�meti� o� logi� ope�ation is ze�o; ot�e�wise Z is �lea�ed.

3 OV OV is set if t�e ope�ation �esults in a �a��y into t�e �ig�est-o�de� bit but not a �a��y out of t�e �ig�est-o�de� bit� o� vi�e ve�sa; ot�e�wise OV is �lea�ed.

� PDF PDF is �lea�ed w�en eit�e� a system powe�-up o� exe�uting t�e CLR WDT inst�u�tion. PDF is set by exe�uting t�e HALT inst�u�tion.

5 TO TO is �lea�ed by a system powe�-up o� exe�uting t�e CLR WDT o� HALT inst�u�tion. TO is set by a WDT time-out.

�~7 — Unused bit� �ead as “0”

Status (0AH) Register

Oscillator ConfigurationInthisdevicetherearetwomethodsofgeneratingthesystemclock,oneexternalcrystaloscillatorandoneinternalRCoscillator.

Rev. 1.20 14 March 24, 2016 Rev. 1.20 15 March 24, 2016



External Crystal/Ceramic Oscillator – HXTThe External Crystal/Ceramic System Oscillator is one of the system oscillator choices, which is selected via a configuration option. For the crystal oscillator configuration, the connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation. Two external capacitors may be required to be connected as shown. However, the feedback resistor named Rf shown in the following diagram for the crystal oscillator to oscillate properly can be selected as either an internally or externally connected type via a configuration option. When the external connection type of the feedback resistor is selected, the recommended value of the external connected feedback resistor ranges from 300kΩ to 500kΩ. Using a ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer’s specification.

For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure thatthe crystal and any associated resistors andcapacitors along with interconnectinglines are all located as close to the MCUas possible.

� � � �

� � � �

� �

� � � � � � � � � � ��

� � � � � � � ��

� �

� �

� �

� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � ��

Crystal/Resonator Oscillator – HXT

Crystal Oscillator C1 and C2 Values

Crystal Frequency C1 C24MHz 8pF 10pF

Note: C1 and C2 values are for guidance only.

Crystal Recommended Capacitor Values

Internal RC Oscillator – HIRCThe internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a fixed frequency of 4095kHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply ranging from 2.2V to 3.6V and in a temperature range from -10°C to 50°C degrees, the fixed oscillation frequency of 4095kHz will have a tolerance within 1%. Note that if this internal system clock option is selected, as it requires no external pins for its operation, I/O pins PB5 and PB6 are free for use as normal I/O pins.

Watchdog Timer – WDTThe WDT clock source is implemented by the instruction clock which is the system clock divided by 4 or the internal RC oscillator with the frequency of 12kHz. The clock source is processed by a frequency divider and a prescaler to provide various time out periods.

WDT time out period = n2SourceClock

Where n= 8~11 selected by a configuration option.

Rev. 1.20 1� �a�� 2�� 201� Rev. 1.20 17 �a�� 2�� 201�



TheWDTtimerisdesignedtopreventasoftwaremalfunctionorsequencejumpingtoanunknownlocationwithunpredictableresults.TheWatchdogTimercanbedisabledbyconfigurationoption.IftheWatchdogTimerisdisabled,alltheexecutionsrelatedtotheWDTresultinnooperationandtheWDTwillloseitsprotectionpurpose.Inthissituationthelogiccanonlyberestartedbyexternallogic.

AWDToverflowundernormaloperationwill initialisea“chipreset”andsetthestatusbit“TO”.Toclear thecontentsof theWDTprescaler, twomethodsareadopted,softwareinstructionsoraHALTinstruction.Therearetwotypesofsoftwareinstructions.Onetypeisthesingleinstruction“CLRWDT”, theother typecomprises twoinstructions,“CLRWDT1”and“CLRWDT2”.Ofthesetwotypesofinstructions,onlyonecanbeactivedependingontheconfigurationoption“CLRWDTtimesselectionoption”.If the“CLRWDT”isselected(i.e..CLRWDTtimesequalone),anyexecutionoftheCLRWDTinstructionwillcleartheWDT.Incase“CLRWDT1”and“CLRWDT2”arechosen(i.e.CLRWDTtimesequal two), thesetwoinstructionsmustbeexecutedtocleartheWDT;otherwise,theWDTmayresetthechipduetoatime-out.

� �

� � � � � ��

� � � � � � �

� � � � � � � � � � � � �

� � � � � � �

� � � � � � �

� � � � � � � � � � � � � � � � �

� � � � � � �

� � ��

� � � � � � � � � � � ��

� � � � � � � � � � � ��

� �

Power Down Operation – HALTThePower-downmodeisinitialisedbytheHALTinstructionandresultsinthefollowing:

• ThesystemoscillatorwillbeturnedoffbuttheWDToscillatorremainsrunning(iftheWDToscillatorisselected).

• Thecontentsoftheon-chipDataMemoryandregistersremainunchanged.

• WDTprescaleriscleared.

• AllI/Oportsmaintaintheiroriginalstatus.

• ThePDFflagissetandtheTOflagiscleared.

ThesystemcanquittheHALTmodebymeansofanexternalfallingedgesignalonallI/Oports.ByexaminingtheTOandPDFflags,thereasonforchipresetcanbedetermined.ThePDFflagisclearedwhenthesystempowersuporwhenaCLRWDTinstructionisexecutedandissetwhentheHALTinstructionisexecuted.TheTOflagisset if theWDTtime-outoccursduringnormaloperation.

TheI/Oportswake-upcanbeconsideredasacontinuationofnormalexecution.EachbitinI/Oportcanbeindependentlyselectedtowakeupthedevicebythecodeoption.AwakeningfromanI/Oportstimulus,theprogramwillresumeexecutionofthenextinstruction.

Onceawake-upevent(s)occurs, it takes1024 tSYS (systemclockperiods) to resumenormaloperation.Inotherwords,adummycycleperiodwillbeinsertedafterthewake-up.

Tominimizepowerconsumption,all I/Opinsshouldbecarefullymanagedbeforeentering theHALTstatus.

Rev. 1.20 1� �a�� 2�� 201� Rev. 1.20 17 �a�� 2�� 201�



ResetThereareseveralwaysinwhicharesetcanoccur:

• PowerOnreset

• RESpinreset

• LowVoltagereset

• WDTtime-outresetduringnormaloperation

Someregistersremainunchangedduringresetconditions.Mostregistersarereset to the“initialcondition”whentheresetconditionsaremet.ByexaminingthePDFandTOflags,theprogramcandistinguishbetweendifferentchipresets.

TO PDF RESET Conditions0 0 Powe�-on �esetu u RES o� LVR �eset du�ing NOR�AL ope�ation1 u WDT time-out �eset du�ing NOR�AL ope�ation1 1 WDT time-out �eset du�ing powe�-down ope�ation

Note:“u”standsforunchanged

Toguaranteethatthesystemoscillatorhasstartedandstabilized,theSST(SystemStart-upTimer)providesanextra-delayof1024systemclockpulseswhenthesystempowersuporwhenthesystemawakesfromaHALTstate.

Whenasystempowerupoccurs,anSSTdelayisaddedduringtheresetperiod.Anywake-upfromHALTwillenabletheSSTdelay.

Thefunctionalunitchipresetstatusisshownbelow.Program Counter 000H

WDT P�es�ale� Clea�Time�/Event Counte� Time� Counte� will be tu�ned offInput/Output Po�ts Input modeSta�k Pointe� Points to t�e top of t�e sta�k

Ca��ie� output Low level state or floatingstate*

“*”Determinedbyconfigurationoption

� � � � ��

� � �

� � � � � � � � � � � �

� � � � � � � � � � � � � �

Reset Timing Chart

Rev. 1.20 18 �a�� 2�� 201� Rev. 1.20 19 �a�� 2�� 201�



� � �

� � � � � � � � � �

� � � �

� � � � � � � � � � � � � � � �

��

� � � � � � � � � � � � ��

� � �

Reset Configuration

� � � � � � �

� � � � � � �

� � � � ��

� � �

� � �

� � � � � � � ��

� � � � � � �

� � � �

Note:“*”ItisrecommendedthatthiscomponentisaddedforaddedESDprotection

“**”Itisrecommendedthatthiscomponentisaddedinenvironmentswherepowerlinenoiseissignificant.

External RES Circuit

Thechipresetstatusoftheregistersissummarisedinthefollowingtable:

Register Power-on Reset RES or LVR Reset WDT Time-out(Operation)

WDT Time-out(HALT)*

PC 0 0 0 H 0 0 0 H 0 0 0 H 0 0 0 H�P - x x x x x x x -uuu uuuu -uuu uuuu -uuu uuuuACC x x x x x x x x uuuu uuuu uuuu uuuu uuuu uuuuTBLP x x x x x x x x uuuu uuuu uuuu uuuu uuuu uuuuTBLH - - x x x x x x - - u u u u u u - - u u u u u u - - u u u u u uSTATUS - - 0 0 x x x x - - u u u u u u - - 1 u u u u u - - 11 u u u uPA 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 uuuu uuuuPB 111 x 1111 111 x 1111 111 x 1111 uuuu uuuuPC - - - - - - - 1 - - - - - - - 1 - - - - - - - 1 - - - - - - - uTSR0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuuTSR1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 uuuu uuuuCARL0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuuCARL1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuuCARH0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 uuuu uuuuCARH1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 uuuu uuuu

Note:“-”standsforunimplemented“u”meansunchanged“x”meansunknown

Rev. 1.20 18 �a�� 2�� 201� Rev. 1.20 19 �a�� 2�� 201�



Input/Output PortsThereareupto17bidirectionalinput/outputlinesinthedevice,labeledPA,PBandPCwhicharemappedto[12H],[14H]and[16H]oftheDataMemory,respectively.EachlineofPAandPBcanbeselectedasNMOSoutputorSchmitttriggerinputwithpull-highresistorbyasoftwareinstruction.PC0canbeusedasaninputlinewithSchmitttriggerbutwithoutpull-highresistororastheexternalRESpindeterminedbytheconfigurationoption.

WhentheI/Oportsareusedforinputoperation,theseportsarenon-latched,thatis,theinputsshouldbereadyattheT2risingedgeoftheinstruction“MOVA,[m]”(m=12H,14Hor16H).ForI/Oportsoutputoperations,alldataislatchedandremainsunchangeduntiltheoutputlatchisrewritten.

When the I/OPortsareused for inputoperations, it shouldbenoted thatbefore readingdatafromthepads,a“1”shouldbewrittentotherelatedbitstodisabletheNMOSdevice.Thatis,theinstruction“SET[m].i”(i=0~7forPA,i=0~3,5~7forPB,i=0forPC)isexecutedfirsttodisablerelatedNMOSdevice,andthen“MOVA,[m]”togetstabledata.

Afterchipreset,theI/OPortsremainatahighlevelinputline.EachbitoftheI/Oportsoutputlatchescanbesetorclearedbythe“SET[m].i”and“CLR[m].i”(m=12H,14Hor16H)instructionsrespectively.

Someinstructionsfirstinputdataandthenfollowtheoutputoperations.Forexample,“SET[m].i”,“CLR[m]”,“CPL[m]”and“CPLA[m]”readtheentireportstatesintotheCPU,executethedefinedoperations(bit-operation),andthenwritetheresultsbacktothelatchesortotheaccumulator.

EachlineoftheI/Oportshasawake-upcapabilitywhentherelevantpinisconfiguredasaninputline.

�

�

� ��

��

� � � � �

� � � � � � � � � �

� � � � � � � � � � � � � � � � �

� � � � � � � � � � � � �

� � � � � � � � � �

� � �

� � � � � � � � � � � � � � � � � � � � �PA and PB Input/Output Ports

�

�

� ��

��

� � � � �

� � � � � � � � � �

� � � � � � � � � � � � � � � � �

� � � � �

� � � � � � � � � � � � � � � � � � �

PC0 Input/Output Port

� � � � � � � � � � � � � ��

� � � � � � � � � � � � � � � � � � �

� �

REM/REMDRV Output Pin Structure

Rev. 1.20 20 �a�� 2�� 201� Rev. 1.20 21 �a�� 2�� 201�



TimerThetimerisaninternalunitforcreatingaremotecontroltransmissionpattern.Asshown,itconsistsofa9-bitdowncounter(t8tot0),aflag(t9)permittingthe1-bittimeroutput,andazerodetector.

No. Label Function0~7 t0~t7 Down �ounte�

TSR0 (18H) Register

No. Label Function0 t8 Down �ounte�1 t9 Time� enable� initial value is “0”.

2~� — Unused bit� �ead as “0”.7 TOEF Timer operation end flag, initial value is “1”.

TSR1 (19H) Register

Timer OperationThetimerstartscountingdownwhenavalueotherthan“0”issetforthedowncounterwithatimermanipulationinstruction.Thetimermanipulationinstructionsformakingthetimerstartoperationareshownbelow: MOV A,XXH ; XX = 00H ~ FFH MOV TSR0,A MOV A,XXH ; XX 01H, t8 MOV TSR1,A SET TSR1.1 ; The timer is started by set t9=1

Additionnotesforthe9-bittimer:

• WritingtoTSR0willonlyputthewrittendatatotheTSR0register(t7~t0)andwritingtoTSR1(t8)willtransferthespecifieddataandcontentsofTSR0totheDownCounter.TOEFwillbeclearedafterthedatatransferredfromTSR1andTSR0totheDownCounteriscompletedandthenwaituntilTSR1.1issetbyuser.

• SettingTSR1.1=1,thetimerwillstartcounting.Thetimerwillstopwhenitscountisequalto“0”andthenTOEFissetequalto“1”.

• IftheTSR1.1isclearedduringthetimercounting,thetimerwillbestopped.OncetheTSR1.1isset(1→0→1),thedowncounterwillreloaddatafromt8~t0,andthenthedowncounterbeginscountingdownwiththenewloaddata.

• IfTSR1.1andTOEFareequalto1both,thetimercanre-start,afternewdataiswrittentoTSR0,TSR1(t0~t8)insequence.

Note:IfthecontentsoftheDowncounteris000H,setthet9tostartthetimercounting,thetimerwillonlycount1step.Thetimeroutputtime=64/fSYS.→[(0+1)×64/fSYS=64/fSYS]

Rev. 1.20 20 �a�� 2�� 201� Rev. 1.20 21 �a�� 2�� 201�



Thedowncounter isdecremented(-1) in thecycleof64/fSYS. If thevalueof thedowncounterbecomes“0”,thezerodetectorgeneratesthetimeroperationendsignaltostopthetimeroperation.At this time,TOEFwillbeset to“1”.Theoutputof thetimeroperationendsignal iscontinuedwhilethedowncounteris“0”andthetimerisstopped.Thefollowingrelationalexpressionappliesbetweenthetimer’soutputtimeandthedowncounter’ssetvalue.

Timeroutputtime=(Setvalue+1)×64/fSYS

AnexampleisshownbelowforfSYS=4MHz MOV A,0FFH MOV TSR0,A MOV A,01H MOV TSR1,A SET TSR1.1

Inthecaseabove,thetimeroutputtimeisasfollows.

(Setvalue+1)×64/fSYS=(511+1)×16μs=8.192ms

� � � � � � � � � � � �

� � � � � � �

Settingthet9bitchannels thetimertotheREMpin.TheREMpinwillbeacombinationofthetimerandcarriersignals.

Note:Thecarrieroutputresultsifbit9ofthehigh-levelperiodsettingmoduloregister(CARH)iscleared(“0”).

� � � � � � � � � � � � � � � � � ��

� � � � � � � � � � � �

Timer Output when Carrier is not Output

� � � � � � � � � � � � � � � � � � � �

� � � � � � � � � � � � � � � � � � � �

� � � � � � � � � �

� � � � � � � � � � � � � ��

� � � � � � �

� ��

� �

� � � � � � � �

� � � � � � � �

� � � � � � � � � � � � ��

Timer Configuration

Rev. 1.20 22 �a�� 2�� 201� Rev. 1.20 23 �a�� 2�� 201�



Carrier Output

Carrier output generatorThecarriergeneratorconsistsofa9-bitcounterandtwomoduloregistersforsettingthehigh-levelandlow-levelperiods-CARHandCARLrespectively.

Register 7 6 5 4 3 2 1 0

CARL0 CL.7 CL.� CL.5 CL.� CL.3 CL.2 CL.1 CL.0CARL1 — — — — — — Fix“0” CL.8CARH0 CH.7 CH.� CH.5 CH.� CH.3 CH.2 CH.1 CH.0

CARH1 — — — — — — CH.9(CARY)

CH.8

CARL0 (1AH) Register, CARL1 (1BH), CARH0 (1CH) Register, CARH1 (1DH), Register

Note:1.CARH1.1(CARY)initialvalueis“1”.

2.CARL1.2(CARH1.2)~CARL1.7(CARH1.7)areunusedbits,readas“0”.

Thecarrierdutyratioandcarrierfrequencycanbedeterminedbysettingthehigh-levelandlow-levelwidthsusingtherespectivemoduloregisters.Eachof thesewidthscanbeset inarangeof500nsto64μsatfSYS=4MHz.

CARH(CARH1.0,CARH0.7~CARH0.0)andCARL(CARL1.0,CARL0.7~CARL0.0)arereadandwrittenusinginstructions.

• Example:MOV A,XXH ; XXH = 00H~FFHMOV CARL0,AMOV A,XXH ; XXH 01H, CL.8 (CARL1.0)MOV CARL1,AMOV A,XXH ; XXH = 00H~FFHMOV CARH0,AMOV A,XXH ; XXH 02H, CH.8 (CARH1.0)MOV CARH1,ACLR CARH1.1 ; The carrier is started by clearing CARY(CARH1.1)= “0”

� � � � � � � �

� � � � � � � � � �

� � � ��

� � � � � � �

� � � � � � � � � � � � ��

� � � � � � � � � � �

� � � � � � � � � � � � � � � � � � � � � � � � � �

� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �

� � �

� � � � � � � � �

� � � ��

� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �

� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �

� � � �

� � �

� � � � � � ��

� � � � �

� � � � �

Configuration of Remote Controller Carrier Generator

Note:1.Bit9ofthemoduloregisterforsettingthelow-levelperiod(CARL)isfixedto“0”.

2.t9:Flagthatenablestimeroutput(timerblock,seeTimerConfiguration)

Rev. 1.20 22 �a�� 2�� 201� Rev. 1.20 23 �a�� 2�� 201�



ThevaluesofCARHandCARLcanbecalculatedfromthefollowingexpressions.

CARL(CARL1.0,CARL0.7~CARL0.0)=(fSYS×(1D)×T)–1……(1)

CARH(CARH1.0,CARH0.7~CARH0.0)=(fSYS×D×T)–1……….(2)

(1)+(2)=>CARL+CARH=(fSYS×T)–2=>ActualCarrierFrequency=fSYS/(CARL+CARH+2)

D:Carrierdutyratio(0<D<1)

fSYS:Inputclock(MHz)

T:Carriercycle(μs)

Ensuretoinputvaluesintherangeof001Hto1FFHtoCARLandCARH.

• Example:If fSYS= 4095kHz, Target fc= 38kHz, T= 1/fc= 26.3157μs= tL+tH, duty= 1/3CARL= (4.095M×(1–1/3)×26.3157μs) – 1= 70.842 select 71= 47H , actual tL= (71+1)/4.095M= 17.58μsCARH= (4.095M×1/3×26.3157μs) – 1= 34.921 select 35= 23H , actual tH= (35+1)/4.095M= 8.79μs

For actual Carrier Frequency= fSYS/(CARL+CARH+2)So, actual fc= fSYS/(CARL+CARH+2)= 4095kHz/(71+35+2)= 37.917kHzMOV A,045HMOV CARL0,AMOV A,022HMOV CARH0,ACLR CARH1.1 ; The carrier is started by clearing CARY(CARH1.1)= “0”

Carrier output controlTheremotecontrollercarriercanbeoutputfromtheREMpinbyclearingtozerobit9(CARY)ofthemoduloregisterforsettingthehigh-levelperiod(CARH).

Whenperformingacarrieroutput,be sure to set the timeroperationafter setting theCARH(CARH1.0,CARH0.7~CARH0.0)andCARL(CARL1.0,CARL0.7~CARL0.0)values.

Notethatamalfunctionmayoccurif thevaluesofCARH(CARH1.0,CARH0.7~CARH0.0)andCARL(CARL1.0,CARL0.7~CARL0.0)arechangedwhilethecarrierisbeingoutputontheREMpin.

Executingthetimermanipulationinstructionstartsthecarrieroutputfromthelowlevel.

ThereisadualfunctionremotecontrollercarrieroutputpinnamedREM.TheselectionofREMorREMDRVisdeterminedbyaconfigurationoption.Afterareset, theREMcarrieroutputpinwillhavealowlevelwhiletheREMDRVcarrieroutputpinwillbeinafloatingcondition.ThegenericstructuresoftheREMorREMDRVfunctionareillustratedintheaccompanyingdiagram.Astheexactconstructionofthecarrieroutputpinwilldifferfromthesedrawings,theyaresuppliedasaguideonlytoassistwiththefunctionalunderstandingoftheremotecarrieroutputpins.

TheoutputfromtheREMpinisinaccordancewiththevalueofbit9(CARY)ofCARHandthetimeroutputenableflag(t9),andthevalueofthetimer9-bitdowncounter(t0tot8).

Rev. 1.20 2� �a�� 2�� 201� Rev. 1.20 25 �a�� 2�� 201�



� � � � � � � � � � � �

� �

� �

� � � � � � �

� � � � � � � �

� � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � � �

Timer Output when Carrier is Output

Note:Whenthecarriersignalisactiveandduringthetimewhenthesignalishigh,ifthetimeroutputshouldgolow,thecarriersignalwillfirstcompleteitshighlevelperiodbeforegoinglow.

CARH1.1Timer Output Enable Flag(t9: TSR1.1)

9-bitDown Counter

REM Function(CMOS Output)

REMDRV Function(NMOS Output)

0 0 0Low-level output Floating output

0 0 Ot�e� t�an 0

0 1 0 ��/fSYS

(wit� �a��ie� output)��/fSYS

(wit� �a��ie� output)

0 1 Ot�e� t�an 0 Ca��ie� output (Note) Ca��ie� output

1 0 ― Low-level output Floating output

1 1 ― Hig�-level output Low-level output

REM Pin Output Control

Note: Inputvalues in the rangeof001H to1FFH toCARH(CARH1.0,CARH0.7~CARH0.0)andCARL(CARL1.0,CARL0.7~CARL0.0).Caution:CARH(CARH1.0,CARH0.7~CARH0.0)andCARL(CARL1.0,CARL0.7~CARL0.0)mustbesetwhiletheREMpinisatalowlevel(t9=0ort0tot8=0).

Target Setting Actual

fC(kHz) Duty CARH(CARH1.0,CARH0.7~CARH0.0)

CARL(CARL1.0,CARL0.7~CARL0.0) tH(μs) tL(μs) T(μs) fC(kHz)

3� 1/3 25H �BH 9.28 18.5� 27.8� 35.92 38 1/3 23H �7H 8.79 17.58 2�.37 37.92 5� 1/3 18H 2FH �.11 11.72 17.83 5�.10 5� 1/2 23H 2�H 8.79 9.0� 17.83 5�.10

Carrier Frequency Setting (fSYS= 4095kHz)

Target Setting Actual

fC(kHz) Duty CARH(CARH1.0,CARH0.7~CARH0.0)

CARL(CARL1.0,CARL0.7~CARL0.0) tH(μs) tL(μs) T(μs) fC(kHz)

3� 1/3 2�H �9H 9.25 18.50 27.75 3�.0� 38 1/3 22H �5H 8.75 17.50 2�.25 38.10 5� 1/3 17H 2EH �.00 11.75 17.75 5�.3� 5� 1/2 23H 22H 9.00 8.75 17.75 5�.3�

Carrier Frequency Setting (fSYS= 4MHz)

Rev. 1.20 2� �a�� 2�� 201� Rev. 1.20 25 �a�� 2�� 201�



� �

�

� � � � � � � � � � � � � �

� �

Low Voltage Reset – LVRThemicrocontrollerprovidesalowvoltageresetcircuitinordertomonitorthesupplyvoltageofthedevice.Ifthesupplyvoltageofthedeviceiswithintherange0.9V~VLVR,suchaswhenchangingabattery,theLVRwillautomaticallyresetthedeviceinternally.

TheLVRincludesthefollowingspecifications:

• Thelowvoltage(0.9V~VLVR)hastoremaininthisstateforatimeinexcessof1ms.Ifthelowvoltagestatedoesnotexceed1ms,theLVRwillignoreitandwillnotperformaresetfunction.TherelationshipbetweenVDDandVLVRisshownbelow.

� � � �

� � � �

� � � �

� � �

� � � �

� � �

� � � �

� � � �

� � � �

� �

� � � � � � � � � � �

� � � � �

� � �

� � � � � � � � � � � � � � � � � � �

� � � � � � � � � � � � � � � � �

Low Voltage Reset

Note:“*1”Tomakesurethatthesystemoscillatorhasstabilised,theSSTprovidesanextradelayof1024systemclockpulsesbeforeenteringnormaloperation.

“*2”Sincelowvoltagehastobemaintainedinitsoriginalstateandexceed1ms,a1msdelayenterstheresetmode.

Rev. 1.20 2� �a�� 2�� 201� Rev. 1.20 27 �a�� 2�� 201�



Configuration OptionsThefollowingtableshowstherangeofconfigurationoptionsforthedevice.Alltheconfigurationoptionsmustbedefinedtoensurepropersystemfunctioning.

No. Code Options

Oscillator Options

1

System os�illato� sele�tion - fSYS:XTAL os�illato� wit�out inte�nal feedba�k �esisto�XTAL os�illato� wit� inte�nal feedba�k �esisto�Inte�nal �095kHz RC os�illato�

REM/REMDRV Pin Options

2 RE� o� RE�DRV output fun�tion sele�tion

Watchdog Options

3 WDT �lo�k sele�tion - fS:Inte�nal RC os�illato� o� fSYS/�

� WDT fun�tion: enable o� disable

5 CLRWDT inst�u�tion sele�tions: 1 o� 2 inst�u�tions

� WDT time-out pe�iod sele�tions: 28/fS� 29/fS� 210/fS� 211/fS

LVR Options

7 LVR fun�tion: enable o� disable

Reset Pin Options

8 I/O o� RES pin sele�tion

Rev. 1.20 2� �a�� 2�� 201� Rev. 1.20 27 �a�� 2�� 201�



Application Circuits• ThefollowingapplicationcircuitshowsthesituationwhenatransistorisaddedtoIRdrivercircuit.HeretheMCUREMfunctionmustbeenabled.

VDD

VSS

REM

C 1

R1

R 2

R3

IR LED

Q18050

C 20.1μF

10Ω

2Ω

250Ω

Battery

HT48RA0-6

VSS1

VDDVDD1

VBAT

HT48RA0-6

Note:1.ThevaluesofR1andC2shouldbeselectedinconsultationwiththeactualapplication,R1=10Ω,C1=0.1μF,C2=200~330μFarerecommendedvalues.

2.Toobtain abetter frequency stability and longer transmissiondistances,C2=330μF is arecommendedvalue.Thefrequencystabilitymaybedifferentandthetransmissiondistancemaybeshorterifavalueotherthan330μFisused.

3.TomaintaintheaccuracyoftheinternalHIRCoscillatorfrequency,a0.1μFdecouplingcapacitorshouldbeconnectedbetweenVDDandVSSonthePCB.

4.TheC1(0.1μF)decouplingcapacitorshouldbelocatedasclosetotheVDDandVSSpinsaspossible.

5.R1andC1shouldbelocatedasclosetotheVDDpinaspossible.

6.VSS,VSS1,C2andQ1mustbeconnectedtothepowerGNDterminal.

7.VDDandVDD1mustbeconnectedtothepowerVBATterminal.

8.ThevaluesofR1andC2shouldbeselectedinconsultationwiththeactualapplication.

9. Itshould tobenoted thatwhenprogrammingthedevice, theHT48RA0-6writer type is thee-WriterPRO,whichwhenusedtogetherwiththee-Socket,canensurethattheHIRCoscillatorfrequencywillhaveatolerancewithin1%intheactualapplicationcircuit.

Rev. 1.20 28 �a�� 2�� 201� Rev. 1.20 29 �a�� 2�� 201�



• ThefollowingapplicationcircuitshowsthesituationwhentheinternalIRdrivercircuitisused.HeretheMCUREMDRVfunctionmustbeenabled.

VDD

VSS

REMDRV

C1

R1

R3

IR LED

C 20.1μF

10Ω

2ΩBattery

VSS1

VDD

VDD1VBAT

HT48RA0-6HT48RA0-6

Note:1.ThevaluesofR1andC2shouldbeselectedinconsultationwiththeactualapplication,R1=10Ω,C1=0.1μF,C2=47~100μFarerecommendedvalues.

2.Toobtain abetter frequency stability and longer transmissiondistances,C2=100μF is arecommendedvalue.Thefrequencystabilitymaybedifferentandthetransmissiondistancemaybeshorterifavalueotherthan100μFisused.

3.TomaintaintheaccuracyoftheinternalHIRCoscillatorfrequency,a0.1μFdecouplingcapacitorshouldbeconnectedbetweenVDDandVSSonthePCB.

4.TheC1(0.1μF)decouplingcapacitorshouldbelocatedasclosetotheVDDandVSSpinsaspossible.

5.R1andC1shouldbelocatedasclosetotheVDDpinaspossible.

6.VSS,VSS1,C2andQ1mustbeconnectedtothepowerGNDterminal.

7.VDDandVDD1mustbeconnectedtothepowerVBATterminal.

8.ThevaluesofR1andC2shouldbeselectedinconsultationwiththeactualapplication.

9. Itshould tobenoted thatwhenprogrammingthedevice, theHT48RA0-6writer type is thee-WriterPRO,whichwhenusedtogetherwiththee-Socket,canensurethattheHIRCoscillatorfrequencywillhaveatolerancewithin1%intheactualapplicationcircuit.

Rev. 1.20 28 �a�� 2�� 201� Rev. 1.20 29 �a�� 2�� 201�



Instruction Set

IntroductionCentral to thesuccessfuloperationofanymicrocontroller is its instructionset,whichisasetofprograminstructioncodesthatdirectsthemicrocontrollertoperformcertainoperations.InthecaseofHoltekmicrocontroller,acomprehensiveandflexiblesetofover60instructionsisprovidedtoenableprogrammerstoimplementtheirapplicationwiththeminimumofprogrammingoverheads.

Foreasierunderstandingofthevariousinstructioncodes, theyhavebeensubdividedintoseveralfunctionalgroupings.

Instruction TimingMostinstructionsareimplementedwithinoneinstructioncycle.Theexceptionstothisarebranch,call,ortablereadinstructionswheretwoinstructioncyclesarerequired.Oneinstructioncycleisequalto4systemclockcycles,thereforeinthecaseofan8MHzsystemoscillator,mostinstructionswouldbeimplementedwithin0.5μsandbranchorcall instructionswouldbeimplementedwithin1μs.Althoughinstructionswhichrequireonemorecycle to implementaregenerally limited totheJMP,CALL,RET,RETIandtablereadinstructions, it is important torealize thatanyotherinstructionswhichinvolvemanipulationoftheProgramCounterLowregisterorPCLwillalsotakeonemorecycletoimplement.AsinstructionswhichchangethecontentsofthePCLwillimplyadirect jumptothatnewaddress,onemorecyclewillberequired.Examplesofsuchinstructionswouldbe“CLRPCL”or“MOVPCL,A”.Forthecaseofskipinstructions,itmustbenotedthatiftheresultofthecomparisoninvolvesaskipoperationthenthiswillalsotakeonemorecycle,ifnoskipisinvolvedthenonlyonecycleisrequired.

Moving and Transferring DataThe transferofdatawithin themicrocontrollerprogram isoneof themost frequentlyusedoperations.MakinguseofthreekindsofMOVinstructions,datacanbetransferredfromregisterstotheAccumulatorandvice-versaaswellasbeingabletomovespecificimmediatedatadirectlyintotheAccumulator.Oneofthemostimportantdatatransferapplicationsis toreceivedatafromtheinputportsandtransferdatatotheoutputports.

Arithmetic OperationsTheabilitytoperformcertainarithmeticoperationsanddatamanipulationisanecessaryfeatureofmostmicrocontrollerapplications.WithintheHoltekmicrocontrollerinstructionsetarearangeofaddandsubtractinstructionmnemonicstoenablethenecessaryarithmetictobecarriedout.Caremustbe takentoensurecorrecthandlingofcarryandborrowdatawhenresultsexceed255foradditionandlessthan0forsubtraction.TheincrementanddecrementinstructionsINC,INCA,DECandDECAprovideasimplemeansofincreasingordecreasingbyavalueofoneofthevaluesinthedestinationspecified.

Rev. 1.20 30 �a�� 2�� 201� Rev. 1.20 31 �a�� 2�� 201�



Logical and Rotate OperationThestandardlogicaloperationssuchasAND,OR,XORandCPLallhavetheirowninstructionwithintheHoltekmicrocontroller instructionset.Aswiththecaseofmost instructionsinvolvingdatamanipulation, datamust pass through theAccumulatorwhichmay involve additionalprogrammingsteps. Inall logicaldataoperations, thezero flagmaybeset if the resultof theoperationiszero.AnotherformoflogicaldatamanipulationcomesfromtherotateinstructionssuchasRR,RL,RRCandRLCwhichprovideasimplemeansofrotatingonebitrightorleft.Differentrotateinstructionsexistdependingonprogramrequirements.Rotateinstructionsareusefulforserialportprogrammingapplicationswheredatacanberotatedfromaninternalregister intotheCarrybitfromwhereitcanbeexaminedandthenecessaryserialbitsethighorlow.Anotherapplicationwhichrotatedataoperationsareusedistoimplementmultiplicationanddivisioncalculations.

Branches and Control TransferProgrambranchingtakestheformofeitherjumpstospecifiedlocationsusingtheJMPinstructionor toa subroutineusing theCALL instruction.Theydiffer in the sense that in thecaseofasubroutinecall, theprogrammustreturn to the instruction immediatelywhenthesubroutinehasbeencarriedout.Thisisdonebyplacingareturninstruction“RET”inthesubroutinewhichwillcausetheprogramtojumpbacktotheaddressrightaftertheCALLinstruction.InthecaseofaJMPinstruction,theprogramsimplyjumpstothedesiredlocation.ThereisnorequirementtojumpbacktotheoriginaljumpingoffpointasinthecaseoftheCALLinstruction.Onespecialandextremelyusefulsetofbranchinstructionsaretheconditionalbranches.Hereadecisionisfirstmaderegardingtheconditionofacertaindatamemoryor individualbits.Dependingupon theconditions, theprogramwillcontinuewiththenextinstructionorskipoveritandjumptothefollowinginstruction.These instructionsare thekey todecisionmakingandbranchingwithin theprogramperhapsdeterminedbytheconditionofcertaininputswitchesorbytheconditionofinternaldatabits.

Bit OperationsTheabilitytoprovidesinglebitoperationsonDataMemoryisanextremelyflexiblefeatureofallHoltekmicrocontrollers.Thisfeature isespeciallyusefulforoutputportbitprogrammingwhereindividualbitsorportpinscanbedirectlysethighorlowusingeitherthe“SET[m].i”or“CLR[m].i”instructionsrespectively.Thefeatureremovestheneedforprogrammerstofirstreadthe8-bitoutputport,manipulatetheinputdatatoensurethatotherbitsarenotchangedandthenoutputtheportwiththecorrectnewdata.Thisread-modify-writeprocessistakencareofautomaticallywhenthesebitoperationinstructionsareused.

Table Read OperationsDatastorage isnormally implementedbyusing registers.However,whenworkingwith largeamountsoffixeddata, thevolumeinvolvedoftenmakesit inconvenienttostorethefixeddataintheDataMemory.Toovercomethisproblem,HoltekmicrocontrollersallowanareaofProgramMemorytobesetupasatablewheredatacanbedirectlystored.Asetofeasytouseinstructionsprovides themeansbywhich this fixeddatacanbereferencedandretrievedfromtheProgramMemory.

Other OperationsInaddition to theabovefunctional instructions,a rangeofother instructionsalsoexistsuchasthe“HALT”instructionforPower-downoperationsand instructions tocontrol theoperationoftheWatchdogTimerfor reliableprogramoperationsunderextremeelectricorelectromagneticenvironments.Fortheirrelevantoperations,refertothefunctionalrelatedsections.

Rev. 1.20 30 �a�� 2�� 201� Rev. 1.20 31 �a�� 2�� 201�



Instruction Set SummaryThefollowingtabledepictsasummaryoftheinstructionsetcategorisedaccordingtofunctionandcanbeconsultedasabasicinstructionreferenceusingthefollowinglistedconventions.

Table Conventionsx:Bitsimmediatedatam:DataMemoryaddressA:Accumulatori:0~7numberofbitsaddr:Programmemoryaddress

Mnemonic Description Cycles Flag AffectedArithmeticADD A�[m] Add Data �emo�y to ACC 1 Z� C� AC� OVADD� A�[m] Add ACC to Data �emo�y 1Note Z� C� AC� OVADD A�x Add immediate data to ACC 1 Z� C� AC� OVADC A�[m] Add Data �emo�y to ACC wit� Ca��y 1 Z� C� AC� OVADC� A�[m] Add ACC to Data memo�y wit� Ca��y 1Note Z� C� AC� OVSUB A�x Subt�a�t immediate data f�om t�e ACC 1 Z� C� AC� OVSUB A�[m] Subt�a�t Data �emo�y f�om ACC 1 Z� C� AC� OVSUB� A�[m] Subt�a�t Data �emo�y f�om ACC wit� �esult in Data �emo�y 1Note Z� C� AC� OVSBC A�[m] Subt�a�t Data �emo�y f�om ACC wit� Ca��y 1 Z� C� AC� OVSBC� A�[m] Subt�a�t Data �emo�y f�om ACC wit� Ca��y� �esult in Data �emo�y 1Note Z� C� AC� OVDAA [m] De�imal adjust ACC fo� Addition wit� �esult in Data �emo�y 1Note CLogic OperationAND A�[m] Logi�al AND Data �emo�y to ACC 1 ZOR A�[m] Logi�al OR Data �emo�y to ACC 1 ZXOR A�[m] Logi�al XOR Data �emo�y to ACC 1 ZAND� A�[m] Logi�al AND ACC to Data �emo�y 1Note ZOR� A�[m] Logi�al OR ACC to Data �emo�y 1Note ZXOR� A�[m] Logi�al XOR ACC to Data �emo�y 1Note ZAND A�x Logi�al AND immediate Data to ACC 1 ZOR A�x Logi�al OR immediate Data to ACC 1 ZXOR A�x Logi�al XOR immediate Data to ACC 1 ZCPL [m] Complement Data �emo�y 1Note ZCPLA [m] Complement Data �emo�y wit� �esult in ACC 1 ZIncrement & DecrementINCA [m] In��ement Data �emo�y wit� �esult in ACC 1 ZINC [m] In��ement Data �emo�y 1Note ZDECA [m] De��ement Data �emo�y wit� �esult in ACC 1 ZDEC [m] De��ement Data �emo�y 1Note ZRotateRRA [m] Rotate Data �emo�y �ig�t wit� �esult in ACC 1 NoneRR [m] Rotate Data �emo�y �ig�t 1Note NoneRRCA [m] Rotate Data �emo�y �ig�t t��oug� Ca��y wit� �esult in ACC 1 CRRC [m] Rotate Data �emo�y �ig�t t��oug� Ca��y 1Note CRLA [m] Rotate Data �emo�y left wit� �esult in ACC 1 NoneRL [m] Rotate Data �emo�y left 1Note NoneRLCA [m] Rotate Data �emo�y left t��oug� Ca��y wit� �esult in ACC 1 CRLC [m] Rotate Data �emo�y left t��oug� Ca��y 1Note C

Rev. 1.20 32 �a�� 2�� 201� Rev. 1.20 33 �a�� 2�� 201�



Mnemonic Description Cycles Flag AffectedData Move�OV A�[m] �ove Data �emo�y to ACC 1 None�OV [m]�A �ove ACC to Data �emo�y 1Note None�OV A�x �ove immediate data to ACC 1 NoneBit OperationCLR [m].i Clea� bit of Data �emo�y 1Note NoneSET [m].i Set bit of Data �emo�y 1Note NoneBranchJ�P add� Jump un�onditionally 2 NoneSZ [m] Skip if Data �emo�y is ze�o 1Note NoneSZA [m] Skip if Data �emo�y is ze�o wit� data movement to ACC 1Note NoneSZ [m].i Skip if bit i of Data �emo�y is ze�o 1Note NoneSNZ [m].i Skip if bit i of Data �emo�y is not ze�o 1Note NoneSIZ [m] Skip if in��ement Data �emo�y is ze�o 1Note NoneSDZ [m] Skip if de��ement Data �emo�y is ze�o 1Note NoneSIZA [m] Skip if in��ement Data �emo�y is ze�o wit� �esult in ACC 1Note NoneSDZA [m] Skip if de��ement Data �emo�y is ze�o wit� �esult in ACC 1Note NoneCALL add� Sub�outine �all 2 NoneRET Retu�n f�om sub�outine 2 NoneRET A�x Retu�n f�om sub�outine and load immediate data to ACC 2 NoneRETI Retu�n f�om inte��upt 2 NoneTable ReadTABRDC [m] Read table to TBLH and Data �emo�y 2Note NoneTABRDL [m] Read table (last page) to TBLH and Data �emo�y 2Note NoneMiscellaneousNOP No ope�ation 1 NoneCLR [m] Clea� Data �emo�y 1Note NoneSET [m] Set Data �emo�y 1Note NoneCLR WDT Clea� Wat��dog Time� 1 TO� PDFCLR WDT1 P�e-�lea� Wat��dog Time� 1 TO� PDFCLR WDT2 P�e-�lea� Wat��dog Time� 1 TO� PDFSWAP [m] Swap nibbles of Data �emo�y 1Note NoneSWAPA [m] Swap nibbles of Data �emo�y wit� �esult in ACC 1 NoneHALT Ente� powe� down mode 1 TO� PDF

Note:1.Forskipinstructions,iftheresultofthecomparisoninvolvesaskipthentwocyclesarerequired,ifnoskiptakesplaceonlyonecycleisrequired.

2.AnyinstructionwhichchangesthecontentsofthePCLwillalsorequire2cyclesforexecution.

3.For the“CLRWDT1”and“CLRWDT2”instructionstheTOandPDFflagsmaybeaffectedbytheexecutionstatus.TheTOandPDFflagsareclearedafterboth“CLRWDT1”and“CLRWDT2”instructionsareconsecutivelyexecuted.OtherwisetheTOandPDFflagsremainunchanged.

Rev. 1.20 32 �a�� 2�� 201� Rev. 1.20 33 �a�� 2�� 201�



Instruction Definition

ADC A,[m] AddDataMemorytoACCwithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADCM A,[m] AddACCtoDataMemorywithCarryDescription ThecontentsofthespecifiedDataMemory,Accumulatorandthecarryflagareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]+CAffectedflag(s) OV,Z,AC,C

ADD A,[m] AddDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+[m]Affectedflag(s) OV,Z,AC,C

ADD A,x AddimmediatedatatoACCDescription ThecontentsoftheAccumulatorandthespecifiedimmediatedataareadded. TheresultisstoredintheAccumulator.Operation ACC←ACC+xAffectedflag(s) OV,Z,AC,C

ADDM A,[m] AddACCtoDataMemoryDescription ThecontentsofthespecifiedDataMemoryandtheAccumulatorareadded. TheresultisstoredinthespecifiedDataMemory.Operation [m]←ACC+[m]Affectedflag(s) OV,Z,AC,C

AND A,[m] LogicalANDDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″[m]Affectedflag(s) Z

AND A,x LogicalANDimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalAND operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″AND″xAffectedflag(s) Z

ANDM A,[m] LogicalANDACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalAND operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″AND″[m]Affectedflag(s) Z

Rev. 1.20 3� �a�� 2�� 201� Rev. 1.20 35 �a�� 2�� 201�



CALL addr SubroutinecallDescription Unconditionallycallsasubroutineatthespecifiedaddress.TheProgramCounterthen incrementsby1toobtaintheaddressofthenextinstructionwhichisthenpushedontothe stack.Thespecifiedaddressisthenloadedandtheprogramcontinuesexecutionfromthis newaddress.Asthisinstructionrequiresanadditionaloperation,itisatwocycleinstruction.Operation Stack←ProgramCounter+1 ProgramCounter←addrAffectedflag(s) None

CLR [m] ClearDataMemoryDescription EachbitofthespecifiedDataMemoryisclearedto0.Operation [m]←00HAffectedflag(s) None

CLR [m].i ClearbitofDataMemoryDescription BitiofthespecifiedDataMemoryisclearedto0.Operation [m].i←0Affectedflag(s) None

CLR WDT ClearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT1 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksin conjunctionwithCLRWDT2andmustbeexecutedalternatelywithCLRWDT2tohave effect.RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT2will havenoeffect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CLR WDT2 Pre-clearWatchdogTimerDescription TheTO,PDFflagsandtheWDTareallcleared.Notethatthisinstructionworksinconjunction withCLRWDT1andmustbeexecutedalternatelywithCLRWDT1tohaveeffect. RepetitivelyexecutingthisinstructionwithoutalternatelyexecutingCLRWDT1willhaveno effect.Operation WDTcleared TO←0 PDF←0Affectedflag(s) TO,PDF

CPL [m] ComplementDataMemoryDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Operation [m]←[m]Affectedflag(s) Z

Rev. 1.20 3� �a�� 2�� 201� Rev. 1.20 35 �a�� 2�� 201�



CPLA [m] ComplementDataMemorywithresultinACCDescription EachbitofthespecifiedDataMemoryislogicallycomplemented(1′scomplement).Bitswhich previouslycontaineda1arechangedto0andviceversa.Thecomplementedresultisstoredin theAccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]Affectedflag(s) Z

DAA [m] Decimal-AdjustACCforadditionwithresultinDataMemoryDescription ConvertthecontentsoftheAccumulatorvaluetoaBCD(BinaryCodedDecimal)value resultingfromthepreviousadditionoftwoBCDvariables.Ifthelownibbleisgreaterthan9 orifACflagisset,thenavalueof6willbeaddedtothelownibble.Otherwisethelownibble remainsunchanged.Ifthehighnibbleisgreaterthan9oriftheCflagisset,thenavalueof6 willbeaddedtothehighnibble.Essentially,thedecimalconversionisperformedbyadding 00H,06H,60Hor66HdependingontheAccumulatorandflagconditions.OnlytheCflag maybeaffectedbythisinstructionwhichindicatesthatiftheoriginalBCDsumisgreaterthan 100,itallowsmultipleprecisiondecimaladdition.Operation [m]←ACC+00Hor [m]←ACC+06Hor [m]←ACC+60Hor [m]←ACC+66HAffectedflag(s) C

DEC [m] DecrementDataMemoryDescription DatainthespecifiedDataMemoryisdecrementedby1.Operation [m]←[m]−1Affectedflag(s) Z

DECA[m] DecrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisdecrementedby1.Theresultisstoredinthe Accumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]−1Affectedflag(s) Z

HALT EnterpowerdownmodeDescription Thisinstructionstopstheprogramexecutionandturnsoffthesystemclock.Thecontentsof theDataMemoryandregistersareretained.TheWDTandprescalerarecleared.Thepower downflagPDFissetandtheWDTtime-outflagTOiscleared.Operation TO←0 PDF←1Affectedflag(s) TO,PDF

INC [m] IncrementDataMemoryDescription DatainthespecifiedDataMemoryisincrementedby1.Operation [m]←[m]+1Affectedflag(s) Z

INCA [m] IncrementDataMemorywithresultinACCDescription DatainthespecifiedDataMemoryisincrementedby1.TheresultisstoredintheAccumulator. ThecontentsoftheDataMemoryremainunchanged.Operation ACC←[m]+1Affectedflag(s) Z

Rev. 1.20 3� �a�� 2�� 201� Rev. 1.20 37 �a�� 2�� 201�



JMP addr JumpunconditionallyDescription ThecontentsoftheProgramCounterarereplacedwiththespecifiedaddress.Program executionthencontinuesfromthisnewaddress.Asthisrequirestheinsertionofadummy instructionwhilethenewaddressisloaded,itisatwocycleinstruction.Operation ProgramCounter←addrAffectedflag(s) None

MOV A,[m] MoveDataMemorytoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Operation ACC←[m]Affectedflag(s) None

MOV A,x MoveimmediatedatatoACCDescription TheimmediatedataspecifiedisloadedintotheAccumulator.Operation ACC←xAffectedflag(s) None

MOV [m],A MoveACCtoDataMemoryDescription ThecontentsoftheAccumulatorarecopiedtothespecifiedDataMemory.Operation [m]←ACCAffectedflag(s) None

NOP NooperationDescription Nooperationisperformed.Executioncontinueswiththenextinstruction.Operation NooperationAffectedflag(s) None

OR A,[m] LogicalORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwise logicalORoperation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″[m]Affectedflag(s) Z

OR A,x LogicalORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″OR″xAffectedflag(s) Z

ORM A,[m] LogicalORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″OR″[m]Affectedflag(s) Z

RET ReturnfromsubroutineDescription TheProgramCounterisrestoredfromthestack.Programexecutioncontinuesattherestored address.Operation ProgramCounter←StackAffectedflag(s) None

Rev. 1.20 3� �a�� 2�� 201� Rev. 1.20 37 �a�� 2�� 201�



RET A,x ReturnfromsubroutineandloadimmediatedatatoACCDescription TheProgramCounterisrestoredfromthestackandtheAccumulatorloadedwiththespecified immediatedata.Programexecutioncontinuesattherestoredaddress.Operation ProgramCounter←Stack ACC←xAffectedflag(s) None

RETI ReturnfrominterruptDescription TheProgramCounterisrestoredfromthestackandtheinterruptsarere-enabledbysettingthe EMIbit.EMIisthemasterinterruptglobalenablebit.Ifaninterruptwaspendingwhenthe RETIinstructionisexecuted,thependingInterruptroutinewillbeprocessedbeforereturning tothemainprogram.Operation ProgramCounter←Stack EMI←1Affectedflag(s) None

RL [m] RotateDataMemoryleftDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←[m].7Affectedflag(s) None

RLA [m] RotateDataMemoryleftwithresultinACCDescription ThecontentsofthespecifiedDataMemoryarerotatedleftby1bitwithbit7rotatedintobit0. TherotatedresultisstoredintheAccumulatorandthecontentsoftheDataMemoryremain unchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←[m].7Affectedflag(s) None

RLC [m] RotateDataMemoryleftthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit0.Operation [m].(i+1)←[m].i;(i=0~6) [m].0←C C←[m].7Affectedflag(s) C

RLCA [m] RotateDataMemoryleftthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedleftby1bit.Bit7replacesthe Carrybitandtheoriginalcarryflagisrotatedintothebit0.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.(i+1)←[m].i;(i=0~6) ACC.0←C C←[m].7Affectedflag(s) C

RR [m] RotateDataMemoryrightDescription ThecontentsofthespecifiedDataMemoryarerotatedrightby1bitwithbit0rotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←[m].0Affectedflag(s) None

Rev. 1.20 38 �a�� 2�� 201� Rev. 1.20 39 �a�� 2�� 201�



RRA [m] RotateDataMemoryrightwithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bitwithbit0 rotatedintobit7.TherotatedresultisstoredintheAccumulatorandthecontentsofthe DataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←[m].0Affectedflag(s) None

RRC [m] RotateDataMemoryrightthroughCarryDescription ThecontentsofthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0 replacestheCarrybitandtheoriginalcarryflagisrotatedintobit7.Operation [m].i←[m].(i+1);(i=0~6) [m].7←C C←[m].0Affectedflag(s) C

RRCA [m] RotateDataMemoryrightthroughCarrywithresultinACCDescription DatainthespecifiedDataMemoryandthecarryflagarerotatedrightby1bit.Bit0replaces theCarrybitandtheoriginalcarryflagisrotatedintobit7.Therotatedresultisstoredinthe AccumulatorandthecontentsoftheDataMemoryremainunchanged.Operation ACC.i←[m].(i+1);(i=0~6) ACC.7←C C←[m].0Affectedflag(s) C

SBC A,[m] SubtractDataMemoryfromACCwithCarryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheAccumulator.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SBCM A,[m] SubtractDataMemoryfromACCwithCarryandresultinDataMemoryDescription ThecontentsofthespecifiedDataMemoryandthecomplementofthecarryflagare subtractedfromtheAccumulator.TheresultisstoredintheDataMemory.Notethatifthe resultofsubtractionisnegative,theCflagwillbeclearedto0,otherwiseiftheresultis positiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]−CAffectedflag(s) OV,Z,AC,C

SDZ [m] SkipifdecrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]−1 Skipif[m]=0Affectedflag(s) None

Rev. 1.20 38 �a�� 2�� 201� Rev. 1.20 39 �a�� 2�� 201�



SDZA [m] SkipifdecrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstdecrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0, theprogramproceedswiththefollowinginstruction.Operation ACC←[m]−1 SkipifACC=0Affectedflag(s) None

SET [m] SetDataMemoryDescription EachbitofthespecifiedDataMemoryissetto1.Operation [m]←FFHAffectedflag(s) None

SET [m].i SetbitofDataMemoryDescription BitiofthespecifiedDataMemoryissetto1.Operation [m].i←1Affectedflag(s) None

SIZ [m] SkipifincrementDataMemoryis0Description ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.Asthisrequirestheinsertionofadummyinstructionwhile thenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0theprogram proceedswiththefollowinginstruction.Operation [m]←[m]+1 Skipif[m]=0Affectedflag(s) None

SIZA [m] SkipifincrementDataMemoryiszerowithresultinACCDescription ThecontentsofthespecifiedDataMemoryarefirstincrementedby1.Iftheresultis0,the followinginstructionisskipped.TheresultisstoredintheAccumulatorbutthespecified DataMemorycontentsremainunchanged.Asthisrequirestheinsertionofadummy instructionwhilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot 0theprogramproceedswiththefollowinginstruction.Operation ACC←[m]+1 SkipifACC=0Affectedflag(s) None

SNZ [m].i SkipifbitiofDataMemoryisnot0Description IfbitiofthespecifiedDataMemoryisnot0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultis0theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i≠0Affectedflag(s) None

SUB A,[m] SubtractDataMemoryfromACCDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheAccumulator.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−[m]Affectedflag(s) OV,Z,AC,C

Rev. 1.20 �0 �a�� 2�� 201� Rev. 1.20 �1 �a�� 2�� 201�



SUBM A,[m] SubtractDataMemoryfromACCwithresultinDataMemoryDescription ThespecifiedDataMemoryissubtractedfromthecontentsoftheAccumulator.Theresultis storedintheDataMemory.Notethatiftheresultofsubtractionisnegative,theCflagwillbe clearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation [m]←ACC−[m]Affectedflag(s) OV,Z,AC,C

SUB A,x SubtractimmediatedatafromACCDescription TheimmediatedataspecifiedbythecodeissubtractedfromthecontentsoftheAccumulator. TheresultisstoredintheAccumulator.Notethatiftheresultofsubtractionisnegative,theC flagwillbeclearedto0,otherwiseiftheresultispositiveorzero,theCflagwillbesetto1.Operation ACC←ACC−xAffectedflag(s) OV,Z,AC,C

SWAP [m] SwapnibblesofDataMemoryDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.Operation [m].3~[m].0↔[m].7~[m].4Affectedflag(s) None

SWAPA [m] SwapnibblesofDataMemorywithresultinACCDescription Thelow-orderandhigh-ordernibblesofthespecifiedDataMemoryareinterchanged.The resultisstoredintheAccumulator.ThecontentsoftheDataMemoryremainunchanged.Operation ACC.3~ACC.0←[m].7~[m].4 ACC.7~ACC.4←[m].3~[m].0Affectedflag(s) None

SZ [m] SkipifDataMemoryis0Description IfthecontentsofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthis requirestheinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwo cycleinstruction.Iftheresultisnot0theprogramproceedswiththefollowinginstruction.Operation Skipif[m]=0Affectedflag(s) None

SZA [m] SkipifDataMemoryis0withdatamovementtoACCDescription ThecontentsofthespecifiedDataMemoryarecopiedtotheAccumulator.Ifthevalueiszero, thefollowinginstructionisskipped.Asthisrequirestheinsertionofadummyinstruction whilethenextinstructionisfetched,itisatwocycleinstruction.Iftheresultisnot0the programproceedswiththefollowinginstruction.Operation ACC←[m] Skipif[m]=0Affectedflag(s) None

SZ [m].i SkipifbitiofDataMemoryis0Description IfbitiofthespecifiedDataMemoryis0,thefollowinginstructionisskipped.Asthisrequires theinsertionofadummyinstructionwhilethenextinstructionisfetched,itisatwocycle instruction.Iftheresultisnot0,theprogramproceedswiththefollowinginstruction.Operation Skipif[m].i=0Affectedflag(s) None

Rev. 1.20 �0 �a�� 2�� 201� Rev. 1.20 �1 �a�� 2�� 201�



TABRDC [m] Readtable(currentpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(currentpage)addressedbythetablepointer(TBLP)is movedtothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

TABRDL [m] Readtable(lastpage)toTBLHandDataMemoryDescription Thelowbyteoftheprogramcode(lastpage)addressedbythetablepointer(TBLP)ismoved tothespecifiedDataMemoryandthehighbytemovedtoTBLH.Operation [m]←programcode(lowbyte) TBLH←programcode(highbyte)Affectedflag(s) None

XOR A,[m] LogicalXORDataMemorytoACCDescription DataintheAccumulatorandthespecifiedDataMemoryperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″[m]Affectedflag(s) Z

XORM A,[m] LogicalXORACCtoDataMemoryDescription DatainthespecifiedDataMemoryandtheAccumulatorperformabitwiselogicalXOR operation.TheresultisstoredintheDataMemory.Operation [m]←ACC″XOR″[m]Affectedflag(s) Z

XOR A,x LogicalXORimmediatedatatoACCDescription DataintheAccumulatorandthespecifiedimmediatedataperformabitwiselogicalXOR operation.TheresultisstoredintheAccumulator.Operation ACC←ACC″XOR″xAffectedflag(s) Z

Rev. 1.20 �2 �a�� 2�� 201� Rev. 1.20 �3 �a�� 2�� 201�



Package Information

Note that thepackage informationprovidedhere is for consultationpurposesonly.As thisinformationmaybeupdatedatregularintervalsusersareremindedtoconsulttheHoltekwebsiteforthelatestversionofthePackage/CartonInformation.

Additionalsupplementaryinformationwithregardtopackagingislistedbelow.Clickontherelevantsectiontobetransferredtotherelevantwebsitepage.

• PackageInformation(includeOutlineDimensions,ProductTapeandReelSpecifications)

• TheOperationInstructionofPackingMaterials

• Cartoninformation

http://www.holtek.com/en

http://www.holtek.com/en/package_carton_information

Rev. 1.20 �2 �a�� 2�� 201� Rev. 1.20 �3 �a�� 2�� 201�



16-pin NSOP (150mil) Outline Dimensions

� �

�

�

�

�

� �

�

�

� �

��

� �

SymbolDimensions in inch

Min. Nom. Max.A — 0.23� BSC —B — 0.15� BSC —C 0.012 — 0.020 C' — 0.390 BSC —D — — 0.0�9 E — 0.050 BSC —F 0.00� — 0.010 G 0.01� — 0.050 H 0.00� — 0.010 α 0° ― 8°

SymbolDimensions in mm

Min. Nom. Max.A — �.000 BSC —B — 3.900 BSC —C 0.31 — 0.51 C' — 9.900 BSC —D — — 1.75 E — 1.270 BSC —F 0.10 — 0.25 G 0.�0 — 1.27 H 0.10 — 0.25 α 0° ― 8°

Rev. 1.20 �� a�� 2�� 201� Rev. 1.20 �5 �a�� 2�� 201�



20-pin SSOP (150mil) Outline Dimensions

� �

�

� �

� �

� �

�

�

� �

� � ��

�

SymbolDimensions in inch

Min. Nom. Max.A — 0.23� BSC —B — 0.15� BSC —C 0.008 — 0.012 C’ — 0.3�1 BSC —D — — 0.0�9 E — 0.025 BSC —F 0.00� — 0.0098 G 0.01� — 0.05 H 0.00� — 0.01 α 0° — 8°

SymbolDimensions in mm

Min. Nom. Max.A — �.000 BSC —B — 3.900 BSC —C 0.20 — 0.30 C’ — 8.��0 BSC —D — — 1.75 E — 0.�35 BSC —F 0.10 — 0.25 G 0.�1 — 1.27 H 0.10 — 0.25 α 0° — 8°

Rev. 1.20 �� a�� 2�� 201� Rev. 1.20 �5 �a�� 2�� 201�



Copy�ig�t© 201� by HOLTEK SE�ICONDUCTOR INC.

T�e info�mation appea�ing in t�is Data S�eet is believed to be a��u�ate at t�e time of publi�ation. Howeve�� Holtek assumes no �esponsibility a�ising f�om t�e use of the specifications described. The applications mentioned herein are used solely fo� t�e pu�pose of illust�ation and Holtek makes no wa��anty o� �ep�esentation t�at su�� appli�ations will be suitable wit�out fu�t�e� modifi�ation� no� �e�ommends t�e use of its p�odu�ts fo� appli�ation t�at may p�esent a �isk to �uman life due to malfun�tion o� ot�e�wise. Holtek's p�odu�ts a�e not aut�o�ized fo� use as ��iti�al �omponents in life suppo�t devi�es o� systems. Holtek �ese�ves t�e �ig�t to alte� its products without prior notification. For the most up-to-date information, please visit ou� web site at �ttp://www.�oltek.�om.tw.

Date post:	28-Feb-2021
Category:	Documents
Upload:	others
View:	0 times
Download:	0 times

Remote Type 8-bit MCU HT48RA0-6 - Holtek...POR to ensu e Powe -on Reset — — 1 ms ˜˚ ˛˝ ˙...

Documents