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Semiconductor Packaging Number of Lectures : 2 Learning Objectives : To appreciate the need for a variety of semiconductor packages, and the

characteristics that influence the selection of package for an application.

At the end of the Module the student should be able to:

• To understand the need for and the availability of a large variety of packages at the chip

level.

• To understand the characteristics of single chip packages and their influence on the system

construction and performance

• To appreciate the criteria according to which a chip level package is selected.

• To have an appreciation of different interconnection technologies used in single chip

packages.

• To have an overall appreciation of materials issues in chip level packaging

• To become familiar with many of the popular single chip packages available in the market.

1 Introduction

2 Characteristics of SC packages : Lead-count and pitch, chip power, electrical performance,

size and weight, and reliability

3 Material issues

4 Interconnections : Issues involved in interconnections. Interconnection technologies

5 Single Chip P ackage Fam ilies : In-line (IP, PDIP, CERDIP), Small Outline (SOJ, SOP, TSOP),

Quad Surface Mount (PLCC, PQFP, LDCC, CERQUAD) , and Array (PGA, BGA, CSP)

6 Multichip Modules :

7 Summary

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SEMICONDUCTOR PACKAGING 1. INTRODUCTION Integrated Circuits are created using one of the many manufacturing technologies available, MOS

(metal-oxide semiconductor) technology being the most popular. The other technologies are

bipolar, bipolar-complementary MOS, and gallium arsenide technologies. The goal of all these

technologies is to integrate more and more devices in a given area of silicon. The smallest circuit

feature that can be created, specified in terms of microns, characterizes the integration level. The

state-of-the-art silicon technology is at the level of 0.13 microns. It is hoped that 0.1-micron levels

would be reached by the year 2002. When more devices are accommodated in a given chip, the

number of functions a chip can perform is enhanced. This increase in functional complexity leads

to an increase in the number of its inputs and outputs as well as the amount of power that is

dissipated by the device as heat.

The integrated circuit, whatever be its level of complexity, will have to be packaged for it to be

used in an electronic system. The silicon chip has to be protected from the environment,

electrical connections have to be created to the external world (next level of packaging), and it

has to be ensured that the heat generated is effectively dissipated. All these requirements have

to be met without significantly reducing the performance of the integrated circuit. The additional

materials and structures used in packaging an integrated circuit will increase the thermal

resistance from the chip to the ambient, increase the electrical delay, reduce the reliability of the

device because of the incompatibility between materials used. However, the requirements at the

product level are continuously increasing in terms of performance, size, weight, and operating

conditions. It is not possible to meet the present day range of product requirements through any

one type of packaging. Consequently, a large variety of chip-level package configurations and

technologies have been created, and new ones are constantly introduced. The major package

families are in-line, small outline, quad flat pack, and array packages. Packaging has always

been a substantial fraction of the price of an IC (10 – 50%). Therefore, reducing packaging costs

while maintaining reliability and performance is the focus of a package designer.

Semiconductor packaging can be broadly divided into two categories: Single Chip Packaging

(SCM) and Multi Chip Packaging (MCM). As the name suggests, there is only one silicon die in a

single chip package. In a multi chip module a number of bare dies are interconnected on a

substrate to achieve higher performance at system level. This Module presents a very brief

overview of the semiconductor packaging technologies and packages, from the point of view of

an electronic system designer.

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2.CHARACTERISTICS OF SEMICONDUCTOR PACKAGES

The lead, pin or pad in a semiconductor package connects a conductor on a printed circuit board

through the body of the package and another interconnect to a bond site on the chip, as shown in

the figure 2.1.

FIG.2.1: Elements of a semiconductor package

Semiconductor packages range in complexity from simple and all too familiar dual-in-line

packages with a small number of leads to 3D Multi Chip Modules. While there are a large variety

of packages, with some large vendors having their own proprietary versions, the single chip

semiconductor packages can be broadly fitted into four families:

• In-line (SIP, PDIP, CERDIP)

• Small outline (SOJ, SOP, TSOP)

• Quad surface mount (PLCC, LDCC, PQFP, CERQUAD)

• Grid array (PGA, BGA)

The multi chip modules are classified into:

• MCM-L

• MCM-C

• MCM-D

Some of these packages are shown in the figure 2.2. Each packaging style provides a certain

combination of characteristics, which is an optimum for some range of applications. The

important characteristics of a package are

• Packaging efficiency

• Leadcount

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• Thermal performance

• Electrical performance

• Size and weight

• Reliability

FIG.2.2: Some of the commonly used semiconductor packages

Packaging Efficiency: The ratio of functional area to nonfunctional area in an electronic system

is an index of the effectiveness of the packaging. The packaging efficiency is defined as

where Fp is packaging efficiency, ASC is the silicon chip area and Ap is package area. If the size

and weight of a product is to be reduced, the packaging efficiency has to be high at all packaging

levels. It will be a strong function of width of the interconnections on the substrate and the

number of interconnection layers used. If dual-inline packages are used on a printed wiring board

(PWB) the packaging efficiency is as low as 1 to 3%. If the semiconductor packages are surface

mount in nature the packaging efficiency can increase up to 6 to 14%. An MCM-D package can

give up to 60% packaging efficiency.

Leadcount : A semiconductor package will have a number of leads to interface with other

components in a circuit in which it is embedded. The function and performance specifications

determine the number of leads, leadcount, of a package. Different package families offer

different leadcount ranges. For example, in-line packages can handle up to 56 leads, and are

more commonly used in the 8 – 20 leadcount ranges, and they require through-hole mounting. If

a smaller form factor is required for the same number of leads, and the ICs need to be assembled

through surface mount technology, the small outline (SO) package is more suitable. Memory

p

SCp A

AF =

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chips that typically use 24 – 36 leads are generally housed in small outline type packages. Bus

interface chips, whose leadcounts are in the range of 64 – 200, use small to medium-sized quad

packages. At very large leadcounts, like with VLSIs, it will be necessary to use some version of

array packaging. The lead count and the distance between the leads, called pitch, are closely

related. The pitch varies from 0.1 inches in DIPs to 0.025 inches in high-end packages.

Thermal Performance : All electronic components generate heat during their operation. This

generated heat needs to be transferred to the ambient. It should not be allowed to accumulate

inside the component, nor transferred to the ambient at a rate that is likely to increase the device

temperature beyond the safe operating temperature. Once the safe operating temperatures are

exceeded, the electronic components may get permanently damaged. The devices in digital

integrated circuits carry more current during transients. Therefore, higher the frequency at which

these devices operate higher is the heat generated by them. As the number of switching

elements in an integrated circuit increase the amount of heat generated per unit area also

increases significantly. The ability of the package to transfer heat generated at the silicon level to

the ambient is characterized by the thermal resistance, specified in terms of OC/Watt. Thermal

performance of a package correlates more significantly with the package materials and

construction than the package type. Each package family has subfamilies that offer lower

thermal resistance. This is done through the use of ceramic bodies and integral heat spreaders.

High-power ICs typically use packages with attached aluminum heat sinks. Once the heat is

conducted to the heat sink, which will offer adequate area for heat transfer, mechanisms like

natural or forced air convection, or more sophisticated liquid cooling mechanisms are used.

ICs with power dissipation in excess of 10 watts may be found in workstation applications, and

ICs with power dissipation ranging between 20 W and 40 W may be found in the mainframe

computers. For example a 7 x 7 mm chip dissipating 30 W results in a heat flux of more than 6 x

105 W/m2, which is about hundred times lower than the heat flux at the surface of the sun. While

the surface temperature of sun is at 6000 OC, the semiconductor devices need to be maintained

in the vicinity of 100 OC. With the ever-increasing integration level at the silicon level, power

dissipation levels are continuously increasing. Developing heat transfer technologies for ICs

dissipating more than 40 watts without the use of bulky fans constitutes one of the present day

challenges to the package designer.

Electrical Performance : The three parameters that characterize electrical performance of an IC

are delay, crosstalk and supply voltage. When the ICs are operated at very high frequencies

(200 MHz and above), the rise rimes of signals become low (in the range of a nanosecond or

less). The interconnections over which such signals are transmitted need to be treated as

transmission lines. There is always a delay associated with such transmission lines, the delay

depending on the length and impedance of the interconnection and the dielectric surrounding it.

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When there are discontinuities in the interconnection, in terms of materials used and its geometry,

the signal gets distorted as well through the phenomenon of reflection. Cross talk is caused by

the electromagnetic induction of voltage in one line from the signals switching in neighboring

lines. With the switching rates of signals being very high and separation between neighboring

leads being very low in IC packages, the cross talk problem can be significant. The supply

voltage to each switching circuit in an IC can change because of the fast switching currents and

the inability of the power supply to respond to such fast transient current requirements. An IC

communicates with other ICs through its driver circuit. These current requirements can be large,

and can cause a dip in the supply voltage. Supply voltage reductions, during transients, can

significantly reduce the noise margins of the circuits.

Packaging will always contribute to the reduction of the electrical performance an IC, as it

increases the interconnection lengths. Increase interconnection lengths will lead to increased

lead resistance, capacitance and inductance. With switching circuits at silicon level operating at

hundreds of MHz, the electrical performance of the packages becomes important. Most of the

attempts of the modern day packaging are directed towards reducing the distance between the

signal or power supply pad on the chip to the printed circuit board on which the IC is to be

mounted. The lead resistance may vary from 30 mΩ in a DIP unit to 4 mΩ in a BGA package.

The lead inductance ranges over 1 nH in a BGA package to 20 nH in a DIP unit.

Size and weight : As products become smaller and portable the size and weight of the ICs also

become important. Decreasing size would mean increasing the silicon efficiency (ratio of silicon

area to the area of the package) of the package. Ball grid array and chip scale packaging help in

significantly reducing the size of the package. Besides these many new packaging technologies,

at the development stage, are attempting to further increase the silicon efficiency. The weight of

the packages can be reduced only through the choice of materials. Ceramic is replaced by

plastic as the package body materials. For example a 40-pin plastic DIP weighs about 6 gms

while the same 40 pin IC with ceramic body can weigh about 12 gms. However, a 196-lead

plastic quad flatpack weighs only about 9 gms.

Reliability : Reliability is a measure to assess the satisfactory performance of the device over

time. It may be specified in terms of number of failures per million device hours. Poor reliability

has consequences to both the customer and the vendor. A failed device can result in loss of

system life, loss of mission capability, system down time, and/or additional work hours and paper

work to the user of the devices. Unreliable devices would lead to warranty claims, additional work

hours and paper work, and/or loss of image and goodwill to the vendor.

An integrated circuit is the result of many processing steps with a variety of materials. Different

materials come in close contact as multilayered structures. These structures undergo many

thermal and other forms of stress cycles both during manufacturing and operating stages. These

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will lead to both structural and material modifications. The packages when exposed to different

operating and storage environments can have some of their parts corroded over a period of time.

The choice of materials, manufacturing processes, and operating conditions and environment all

have significant influence on the reliability of the package, and consequently on the reliability of

the product. Hermetic packages that minimize the leakage between the environment and the die

cavity have higher reliability than the “nonhermetic” packages. Organic coatings are used to

protect the die and the interconnects from corrosion. The devices may be operated at current

levels less than the rated values to reduce the thermal stress and thereby enhance the reliability.

When there is a possibility, the environment ambient to the device can be controlled to reduce the

undesirable effects. All companies make continuous efforts in studying why the devices and

packages fail, and improve their materials and processes to enhance the reliability of the

integrated circuits.

3. MATERIAL ISSUES

Several materials are used in creating semiconductor packages. The packaging materials may

serve as electrical conductors or insulators, provide structure and form, provide thermal paths,

and protect the circuits from environmental factors such as moisture, contamination, hostile

chemicals, and radiation. The properties of materials that are of concern to the performance and

reliability of semiconductor packages can be classified into electrical, thermal and

thermomechnical, mechanical, chemical and miscellaneous properties. Let us briefly explore

some of the important properties of materials and their role and influence on the package

performance.

Electrical Properties : Processing electrical signals is central to electronic systems. The

materials and their structures used in packaging influence the propagation of signals, which

becomes very critical when the circuits operate at very high frequencies. Some of the electrical

properties that are of importance to packaging are dielectric constant, loss factor, dielectric

strength, volumetric resistivity, and surface resistivity. The dielectric constant of the substrate

material influences both the signal propagation and the power supply glitches. The propagation

delay of a signal directly varies with the square root of the dielectric constant. However, a high

dielectric constant is desired for the material between the ground and power plane to smooth

small inductive spikes in power supply. Most materials possess a dielectric constant that

depends on the frequency of the applied electromagnetic field. Electrical power loss occurs

whenever an insulating material is subjected to a sinusoidally time-varying applied potential. A

low loss is desired for a dielectric material so that electric power dissipated in the insulator is

minimized. This is particularly important for high-power circuits operating at high speeds. For

example, epoxy resin has a dielectric constant of about 4 and a loss factor of 1200, while

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polyimide has a dielectric strength of 3.5 and a loss factor in the range of 0.008 – 0.035. This

makes the polyimide a better substrate material in packaging high frequency circuits.

The dielectric strength, expressed in megavolts per cm (MV/cm) is defined as the voltage

gradient that an insulating material can withstand before the arc forms through the material. It is

also a function of temperature and humidity. The higher the value of dielectric strength, the better

the insulator against applied voltage gradients. Volumetric resistivity, expressed in megaohms-

centimeters (MΩ-cm), is the bulk material property and varies with temperature, moisture content,

applied voltage and the time duration of the applied voltage. In general, a material with a high

resistivity is a better insulator. Surface resistivity is the resistance offered by 1 cm2 surface film.

The mechanism of surface conduction is through an absorbed film on the surface of the material.

Surface contaminants, ambient temperature, and humidity affect surface resistance. A material

with a higher surface resistance provides better insulation against electrical conduction occurring

on a material’s surface. Many other measures, which could be better indicators in specific

operating conditions, may be defined in terms of these basic electrical properties.

Thermal and Thermomechanical Properties : Materials in packaging experience a range of

steady-state temperatures, temperature gradients, rate of change of temperature, temperature

cycles, and thermal shock through manufacturing, storage, and operation. Thermal properties

that are of significance to the performance of the packages are thermal conductivity, the

deflection temperature, glass transition temperature, and the coefficient of thermal expansion.

Thermal conductivity, expressed in watts per meter per degree centigrade (W/m-oC), is an index

of how easily the material conducts heat. Polymers are generally poor conductors and exhibit

very low thermal conductivity (epoxy glass – 0.3 W/m-oC and polyimide – 0.2 W/m-oC), often

several orders of magnitude lower than metals (copper – 380 W/m-oC, and aluminum – 210 W/m-oC). Ceramics exhibit better heat conductivity than polymers (alumina – 36 W/m-oC). The

effective thermal conductivity of some materials can be improved by adding fibers or fillers of

higher thermal conductivity.

The glass transition temperature is the temperature at which a material changes from a hard,

brittle “glass-like” form to a softer, rubber-like consistency. This is a property specific to polymers,

and is not generally exhibited by metals or ceramics. The change in state occurs over a range of

temperatures for amorphous polymers (epoxy type FR-4 – 125-135oC, polymide – 240-260oC).

Electrical, thermomechanical, and mechanical properties of a material dramatically change often

beyond the glass transition temperature. The deflection temperature is the temperature at which

a specified deflection occurs in a specimen under a selected load and loading method. This

temperature is indicative of the mechanical load-carrying capability of a material. The deflection

temperature of polymeric materials and composites may approximate their glass transition

temperature. As polymeric laminates are used as substrates at both semiconductor level and

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board level packaging, it is of great interest to have polymers with glass transition temperatures

beyond temperatures used in manufacturing processes such as soldering.

The coefficient of linear thermal expansion (CTE) is the change in linear dimension per unit length

per degree change of the bulk material temperature, and is generally expressed in

micrometer/meter-degree centigrade (µm/m-oC) and specified at 55OC. The CTE is often

positive, but can be negative or zero. It can change appreciably with temperature. Polymers

exhibit almost an order of magnitude higher CTE than most metals, ceramics and glasses.

Above the glass transition temperature, the CTE of polymers further increases by a factor of 3-5.

When packaging structures are created in which different materials are joined together,

endurance to thermal cycles is dependent on the matching of CTEs.

Mechanical Properties : The mechanical properties affect the material’s ability to sustain loads

due to vibration, shock, and thermomechanical stresses during manufacture, assembly, storage,

and operation. Key properties that are of importance to electronic packaging applications include

the modulus of elasticity, tensile strength, Poisson’s ratio, flexural modulus, fracture toughness,

creep resistance, and fatigue strength.

Chemical Properties : The chemical properties of importance to packaging are water absorption,

flammability, and corrosion resistance. Water absorption is defined as the increase in weight of a

material after immersion in water for a specified duration of time at a specified temperature.

Water absorption is dependent on the chemical nature of the material as well as on the presence

of voids. The electrical properties of materials often change as a result of water absorption.

Dimensional instabilities can also occur due to water absorption. In molding materials, water

absorption lead to corrosion of embedded metals. Flammability is the property of a material

whereby flaming combustion is prevented, terminated, or inhibited following application of a

flaming or non-flaming source of ignition. The numerical value of flammability is given by the

oxygen index, which is the percent oxygen in an oxygen-nitrogen mixture that will just sustain

combustion of a material. Often, the composition of polymers used in electronic packaging has to

be adjusted to meet the certification by Underwriters Laboratories.

Corrosion resistance is the ability of a material to resist deterioration due to chemical or

electrochemical attack. Corrosion occurs in metals largely due to the formation of an

electrochemical cell, and in nonmetals through chemical attack. The standard oxidation potential

(relative to hydrogen electrode) is a useful index to determine the corrosion resistance. A lower

galvanic potential of one metal with respect to the other is an index of corrosion resistance of a

metal. Corrosion of nonmetals leads to formation of more stable compounds and can involve loss

in weight, swelling, decomposition, depolymerization, and degradation in physical properties.

Let us consider some material issues in semiconductor packaging situations. Details of a typical

plastic package are shown in the figure 3.1.

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FIG.3.1: Details of a typical plastic package

It consists of a silicon chip and metal leadframe to which the die is attached. The pads on the die

are wire bonded to the leadframe. The top surface of the die is passivated. The entire assembly

is encapsulated in a thermoset molding compound via the transfer-molding process. The

encapsulant must possess adequate mechanical strength, adhesion to package components,

manufacturing and environmental chemical resistance, electrical resistance, matched coefficient

of thermal expansion to the materials it interfaces with, and high thermal and moisture resistance

in the application temperature range. The molding compound is a multicomponent mixture of an

encapsulanting resin with various types of additives. The principal active and passive

components in a molding compound include curing agents or hardeners, accelerators, inert fillers,

coupling agents, flame retardants, stress-relief additives, coloring agents, and mold-release

agents

The leadframe is the backbone of a molded plastic package. Fabricated from a strip of sheet

metal by stamping or chemical milling, it serves first as a holding fixture during the assembly

process, then, after molding, becomes an integral part of the package. Copper would be an ideal

leadframe material from an electrical and thermal conductivity standpoint, but it has properties

that must be modified before it can be successfully used in plastic packages. The addition of

iron, zirconium, zinc, tin, and phosphorous serves to improve the tensile strength and ductility of

the material. However, copper alloys have high thermal-expansion rates with respect to silicon,

but nearly match the expansion rate of low-stress molding compounds. For example silver-filled

epoxies and polyimide chip-attach adhesives have been developed and are flexible enough to

absorb the strain developed between chip and copper.

4. INTERCONNECTIONS

The interconnections encountered in semiconductor packages can be broadly classified into two

categories: die-to-substrate interconnection, and interconnection on substrates. There are three

popular technologies for creating die-to-substrate interconnections in semiconductor packages.

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They are wire bonding, tape automated bonding (TAB), and controlled collapse chip connection

(C4). The structures of these interconnections are illustrated in the figure 4.1.

Fig.4.1: Different types of die-to-substrate interconnections

In addition to these, there are several specialty interconnect technologies such as pressure

contact, transfer metal bumps and conductive adhesives, which are used either for a few limited

applications or under development. The most basic function of the die-to-substrate

interconnections is to provide electrical path to and from the substrate for power and signal

distribution. Electrical parameters such as resistance, inductance, and capacitance of the

interconnection are important, as each of these will affect the performance the system. In

addition to the electrical function, TAB and C4 interconnections also provide mechanical support

for the chip. The technologies used for creating interconnections on substrates in MCMs are thin-

film, thick film, and copper deposition using either additive or subtractive processes.

As the interconnection materials are also good conductors of heat, they can be designed for

removal of heat from the chip as well. Thus interconnections provide electrical, mechanical, and

thermal functions. A brief description of the major interconnection technologies is given in the

following.

Wire Bonding : Wire bonding is the oldest and most widely used interconnect approach and is

compatible with a wide range of packages, particularly for ICs with moderate leadcounts (< 200).

The process uses a fine (0.8 – 1.5 mil) gold or aluminum wire, which is connected between each

I/O pads located around the periphery of the silicon die, and its associated package pin (figure

4.1(a)). These interconnections are created one at a time. While this looks disadvantageous, it

turns out to be its greatest strength, namely flexibility. Wiring changes can be accomplished very

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easily and in short times, without any need for special tooling and material changes. Bell Labs

introduced wire bonding process in 1957, and the first commercial wire bonding equipment was

introduced in 1963. Since then, the reliability of the processes and the speed of the bonding

equipment significantly improved. The infrastructure and the knowledge base on wire bonding is

extensive, making it the most preferred chip level interconnection technology.

Wire bonding is done after the die is attached to the package or leadframe. The wire, in wire

bonding process, is fed off a spool to a bonding tool, which is positioned over the bond pad on the

chip. Once in position, the tool places the wire in contact with the pad, and attaches it to the pad

through a thermocompression (high temperature and pressure), ultra sonic (vibration and

pressure), or thermosonic (vibration, high temperature and pressure) process. The tool then

retracts, bringing the wire with it and moves to the package bond finger. Once over the bond

finger, the tool comes back down and repeats the process to complete the interconnection. After

completing the attachment to the bond finger, the wire is clamped by the bond head, so that when

the tool pulls away, the wire breaks, leaving the completed bond in place. The machine then

positions the bond over the next pad and repeats the process, until all bond pads on the die are

properly bonded to the bond fingers.

In the gold wire bonding process, the bonding tool is a hollow capillary through which the wire

feeds. Once a short segment is through, the tip of the wire is melted to form a ball. It is this ball

that is compressed and attached to the chip bond pad. The second bond compresses the wire to

the bond finger, and when the tool clamps the wire and retracts, a short wire segment is left

extended form the capillary, ready for the next ball formation. Figure 4.2 illustrates gold ball

bonding process.

FIG.4.2: Gold ball bonding process

The process used with aluminum wire is known as “wedge bonding”. In this process, the bond

head is actually shaped like a wedge. The wire is fed through a wire guide and extends beneath

this wedge. The wedge maintains some lateral motion while it compresses the wire to the pad to

form the bond. After this process is used for the second bond, the tool rocks on the wire to thin or

cut it before retracting. This leaves a wire segment, ready for the next bond beneath the wedge

tool. Figure 4.3 illustrates wedge bonding.

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FIG.4.3: Wedge bonding process

Wire bonding is the most prevalent means of doing interconnects with more than 90 percent of

total first level interconnects. Of this figure, gold wire bonding represents approximately 90

percent of interconnects while the remainder is aluminum and other noble or near-noble metals.

When you would use each of these types of processes depends on the specific type of

application. For example, gold wire bonding is used in most high volume applications because it

is a faster process. Aluminum wire bonding is used in situations when packages or a printed

circuit board cannot be heated. In addition, the wedge bonding process can attain a finer pitch

than gold wire bonding. Presently, the pitch limits of gold wire bonding are as fine as perhaps 60

microns. Aluminum wedge bonding with fine wire can be performed at pitches finer than 60

microns.

Tape Automated Bonding (TAB) : The TAB concept originated in the 1960s at General Electric

Research Laboratories. This process was developed as a high productivity alternative when the

wire bonding process was at its infancy, and high reliabilities and speeds were not achieved. In

the TAB process all the pads on the wafer can be bonded to the leads in one operation. Many

other companies like IBM, Lucent Technologies, Sharp and Shindo developed several variations

of the TAB process. The TAB process became more popular in eighties and nineties for

application in liquid crystal displays, printheads, and smart cards. The term “tape” refers to the

actual interconnect medium used in the process. Tape is constructed as a layer of either rolled or

electro-deposited and plated copper, which can be attached to and supported by a dielectric

polymer film. Polyimide is often used as the film in the process due to its availability and cost, its

mechanical, chemical, and electrical properties, and the ease with which it can be handled and

processed. A conductor pattern for the copper, specific to the integrated circuit under

consideration, is created on the tape using a photo-etching process. The copper is first covered

with a photoresist and then exposed to light through an artwork that contains the conductor

pattern. The conductors are patterned as leads, with a width and spacing to match the pad pitch

on the die and a length and position to extend from the die pad to the package bond location.

Following photoresist exposure, chemical etching is used to remove copper and leave the lead

pattern. The conductors are plated with nickel, which acts as a seed and protective barrier layer

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prior to the final plating. The final plating is either gold or tin, depending on the TAB assembly

process that will be used.

The tape must be raised off the surface of the die to prevent damage to any underlying device

structures and to prevent electrical shorting between the tape and the edge of the die. This is

done through creating metallized bumps over the die pads. They will accommodate the flat TAB

tape lead and provide the proper material for a reliable connection to the tape. The bump

fabrication process uses a metal deposition and plating process. First a series of barrier and

seed layers of metal are deposited over the surface of the wafer. A layer of photoresist is

deposited over these barrier and seed layers. A photomask is used to pattern the locations over

each of the pads that will be bumped. An etching process exposes the pads, and the open resist

hole defines the shape and height of the bump. The bump, which is typically gold, is then

electroplated over the pad and the deposited barrier metals. Once the plating is complete, a

series of etching steps are used to remove the photoresist and the barrier metal layers that are

covering the rest of the die. The gold bump protects the underlying materials from being etched.

While gold bumping is the most common, copper, tin-lead, as well as layered combinations of

these materials are used for bumping. An alternative to die bumping is to create bumps on the

tape. For high lead counts, wafer bumping is more common. Figure 4.4 illustrates a completed

bump and a TAB tape lead.

FIG.4.4: TAB with wafer bumping

The leads are attached to the bumps on the wafer through a process called “inner lead bonding”

(ILB). If the tape is gold plated, the ILB process is one of thermocompression, where in a

bonding tool applies pressure and high temperature to each lead/bump. If the tape is tin plated, a

slightly modified thermocompression bonding process is used. Instead of constant temperature

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application, a pulsed heat flow is used to form a tin-gold intermetallic bond. The ILB process is

illustrated in the figure 4.5.

FIG.4.5: Inner lead bonding process

Once the chip is connected to the tape it can be tested electrically. Following testing, the tape

with die is “excised” from the tape carrier, leaving the test pads and other portions of the tape

behind. The remaining structure is the extension of the leads off the dies, which will be

connected to the bond fingers of the package or the printed wiring board. The second bonding,

called outer lead bonding (OLB), is the process of connecting the outer leads of the tape to the

package, leadframe, substrate, or card, and is similar to the ILB process.

TAB’s inherent advantage of being light, thin, short, and small, and its flexibility will enable it to

maintain its edge in a wide variety of applications such as watches, calculators, cameras,

sensors, and hearing aids.

Controlled Collapse Chip Connection (C4): IBM introduced in 1964 the facedown soldering of

silicon devices to alumina substrates, known as flip-chip technology. It was an attempt to create

an alternative to the expensive, unreliable and low productivity wire bonding technology of that

era. This method of interconnection later evolved into a technology wherein a pure solder bump

was restrained (controlled) from collapsing or flowing over the electrode land by using thick-film

glass dams, or stop offs, which limited device solder-bump flow to the tip of the substrate

metallization. The chip is flip mounted on the package, so that pads and bumps on the chip

directly align with the bond pads on the package. A reflow-soldering technique forms all the joints

between the chip and package simultaneously, once the chip is in position. Using this technique,

both the shortest electrical path between the chip and package, as well as the highest I/O pad

density off the chip can be realized.

The pad is metallized with layers of chrome, copper, and gold to hold the solder in place. Solder

is then deposited over the pads to create the bump that will be connected to the package.

Different sized bumps and different solder alloys are used depending on factors such as pad

pitch, die size, and package substrate material. The reflow process is self-aligning in nature in

that the bumps hold the die and package in the correct orientation, because of the shape and

surface tension of the solder bump.

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Thin-Film Int erconnections : Thin film refers to coating a layer of thickness typically in the range

of 2-3 atomic layers to a few (1-5) microns. The interconnections have line widths in the range of

12-50 microns. The thin film conductors are created, in MCM-D technology, over unreinforced

dielectric material. The most commonly used metals as primary current carrying conductors are

aluminum, copper, and gold. Chromium and titanium are often used as interface materials to

improve adhesion. Typical metals used as top layer metallization are gold, nickel and chromium.

Primary metallization is done by either thin film vacuum processes such as evaporation or

sputtering or by wet processes such as electrolytic or electroless plating. Film thickness

uniformity is key to repeatable manufacturing of thin film structures. In general, vacuum

deposition processes result in more uniform films than do electroplating processes. In general,

electroplating is used for copper and gold, and sputtering or evaporation is used for aluminum.

Thick Film Int erconnections : Interconnections in thick film technology, used in MCM-C modules

and hybrids, are formed upon the substrate by the sequential screen printing, drying, and firing of

the conductive pastes. Multilayer interconnections are formed by the alternate deposition of

conductive and dielectric materials. The printing pastes or inks are comprised of both organic

and inorganic components, which are present in the form of a suspension of conductive particles

in an organic fluid. Thick film conductors are typically silver or gold and their alloys with platinum

or palladium when the substrate is ceramic. Low cost conductor pastes such as those based on

copper or nickel are also used sometimes.

Copper Deposition : MCM-L technology uses copper deposition for creating conductors either

through subtractive processes or additive process. These processes are the same as those used

in creating printed wiring boards. The subtractive process, shown in the figure 4.6, consists of

preparing copper clad laminate, applying photoresist, exposing the conductor pattern using a

photo mask, developing, etching copper and removing the resist.

FIG.4.6: Subtractive process

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5. SINGLE CHIP PACKAGE FAMILIES

5.1 PACKAGE FABRICATION PROCESSES

There are three major package construction processes: plastic, cofired ceramic, and pressed

ceramic processes. A typical plastic package (figure 5.1) consists of

• a silicon chip,

• a metal support or a leadframe,

• wires that electrically attach the chip circuits to a leadframe, which incorporates

external electrical connections, and

• a plastic epoxy-encapsulating material to protect the chip, and the wire interconnects

FIG.5.1: Details of a plastic package

The leadframe is made of copper alloy, and is plated with gold and silver or palladium, either

completely or in selected areas over nickel or nickel/cobalt. The silicon chip is usually attached to

the leadframe with an organic conductive formulation of epoxy. Gold or aluminum wires are

bonded to the aluminum bonding pads on the chips and to the fingers of the leadframe. The

assembly is then typically molded in epoxy. The external leads are then plated with a lead-tin

alloy, cut away from the strip, and formed into desired shapes. Plastic packages are made in

either surface-mount or through-hole configurations.

Cofired ceramic technology refers to the process of taking multiple layers of cast ceramic "tape"

which have been imprinted with metallized patterns and vias, stacking them together so the

metallized layers connect through the vias, and firing (sintering) them together in a furnace such

that a monolithic body is formed. The commonly used material is alumina, which has been

specially blended with ceramic, glass, organic binders, solvents, and plasticizers. The additives,

which are considered as trade secrets, ensure a controlled and specified shrinkage rate and

adhesion of all layers. The metallization is commonly tungsten, which can handle the high

refractory temperature of approximately 1500oC. , As this technology can support many

metallized layers within the package, it is common to find several layers used for power and

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ground references, and at least two layers for signal interconnections. The metallization creates

a connection from the pad on the chip to a lead, pad or pin through vias. Several variants exist

for this process. The process steps are shown in the figure 5.2.

FIG.5.2: Multilayer ceramic fabrication process

Pressed ceramic process, first developed at IBM and called as SLT (Solid Logic Technology) in

1963, uses a sandwich of a pressed ceramic body and a leadframe connected with borosilicate

glass as shown in the figure 5.3. Following the chip assembly, a ceramic lid with glass preform is

used to seal the cavity. This process was initially used for creating ceramic DIPs with up to 64

pins, and subsequently extended to chip carriers, which are either leaded or leadless.

FIG.5.3: Pressed ceramic package body

Plastic Versus Ceramic : Ceramics possess a combination of electrical, thermal mechanical and

dimensional stability properties unmatched by any other group of materials. Ceramic substrates

provide the highest wiring density of all substrate technologies. Plastic encapsulated

microelectronics (PEMs) offer many advantages over hermetic packages in the areas of size,

19

weight, performance, cost, reliability, and availability. Therefore, it is not surprising that plastics

account for more than 97% of the worldwide commercial chip-encapsulation market. Commercial

PEMs generally weigh about half as much as ceramic packages (for example 14 pin plastic DIP

weighs 1 gm against 2 gms for 14-pin ceramic DIP). Smaller outline packages (SOPs), and

thinner configurations, such as thin small-outline packages (TSOPs) are available only in plastic.

Plastics have better dielectric properties than ceramics. Plastic quad flat pack (PQFP), pin-grid

arrays, and ball grid arrays (PBGA) are favored for minimizing propagation delays. However, at

very high frequencies (up to 20 GHz) better and more predictable performance is obtained with

ceramic packages. Ceramic packages usually have a higher material and testing cost, and are

fabricated with more labor-intensive manual processes. The reliability of PEMs has vastly

improved over the years, and their failure rates are comparable to those of ceramic packages.

5.2 INLINE PACKAGES

There are two categories of inline packages: Dual-Inline (DIP) and Single-Inline (SIP) packages.

Dual-inline package, shown in the figure 5.4, is one of the earliest packaging styles introduced. It

is available in low cost plastic and hermetic ceramic types, with through hole mounting I/O

terminals on a 0.1 inch inline pitch. Their inline-to-inline terminal spacing varies from 0.30 to 0.60

inches depending on the terminal count.

FIG.5.4: Dual inline package

DIP was extremely popular in the early era of integrated circuits because

• it cost-effectively and reliably satisfied the electrical, and mechanical requirements for

many years.

• with its 8 through 40 I/O terminals satisfied the needs of a wide range of IC devices, and

• it satisfied the assembly requirements on PCBs either through manual soldering or using

automatic termination techniques.

20

As the demand for lead count requirements, electrical performance, and small footprints increase,

most of the advantages of DIPs disappear, and there is need for considering other types of

packages.

Single-inline packages (SIP) are rectangular in shape with leads on one of the long sides, as

shown in the figure 5.5. This type of packaging is mainly used to provide a means for packaging

of memory chips in a high-density format. When it is inserted into a PCB many of these can be

placed side by side and stacked closely together, separated by just the thickness of the package,

because the leads or contacts are located along just one side of the package. There are two

more variants of this package. One is zig-zag inline package (ZIP) and the single in-line memory

module (SIMM). The leads of a ZIP are typically 0.05 inch centers at the plastic body interface,

formed into two staggered rows spaced 0.1 or 0.05 inch apart. These packages offer a high

profile but small footprint on the board, maintaining 0.1 inch hole mounting standard.

FIG.5.5: Single in-line package

5.3 SMALL OUTLINE PACKAGES

A small package body characterizes the small outline peripheral leaded package family. These

packages have surface mount leads on two sides. The primary advantages of a small outline

package is its small size and its suitability for surface mounting. There are three sub families:

Small Outline J-Bend Package (SOJ), Small Outline Gull-Wing Package (SOP) and Thin Small

Outline Package (TSOP). The characteristics of SOJ and SOP may be summarized in

comparison with corresponding DIPs as:

16-pin 28-pin

SO DIP SO DIP

Body size L x W (mm2) 40 140 140 500

Board area (mm2) 62 175 192 590

Body thickness (mm) 1.45 3.6 2.45 3.9

Height above board (mm) 1.75 5.1 2.65 5.1

Weight (gms) 0.13 1.2 0.7 4.3

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These packages are about one-third the size and use about one-quarter of the substrate

mounting area of the equivalent DIP. Consequently, small outline components are quite often

used in applications where space and weight are at premium.

The SOJ, shown in the figure 5.6, is leadframe based package with a molded plastic body. The

“J” in the package name refers to the lead configuration. The leads extend out from the side of

the package and are wrapped underneath the body, forming the shape of the letter J. The typical

application for this package is the DRAM. The standard lead pitch for this package is 0.05

inches, and the leadframe is prepared for surface mounting. The lead count varies from 15 to 28.

FIG.5.6: Small outline package with J leads

The gull wing package, shown in the figure 5.7, is more commonly known as SOP. The SOP is

plastic molded leadframe based package like SOJ. The lead is formed away from the body in the

shape of a “gull wing”, for surface mounting. It is available with 0.05 inch lead pitch, and in many

body sizes from 0.15 inches to 0.44 inches and lead counts 8 to 32. The SOP is commonly used

for SRAM chip, and consequently is a very high volume package in the industry. As SRAMs

generate more heat than DRAMs, the lead frame materials of SOP are adjusted for transferring

larger amounts of heat, which is in the range of 0.25 to 0.5 watts

FIG.5.7: Gull wing SOP

The thin small outline packages (TSOP) shown in the figure 5.8, are created in response to needs

of new applications in lightweight and portable electronics. The TSOPs have their heights in the

range of 1 – 1.2 mm. There are two types of TSOPs, shown in the figure 5.8, designated as Type

1 and Type 2. In Type 1 TSOP the leads are on the shorter side. These packages maintain 0.05

22

inch lead pitches like other small outline packages, and have lead counts in the range 20 – 48.

This package is low-cost and used for memory applications.

FIG.5.8: TSOP

5.4 QUAD PACKAGES

The quad surface mount package family is characterized by a larger body and higher lead counts

with leads on all four sides. The prominent members of this family are PQFP (Plastic Quad Flat

Pack), CQFP (Ceramic Quad Flat Pack), and CC (Chip Carrier). Figure 5.9 shows a PQFP with

gull-wing leads.

FIG.5.9: PQFP with gull wing leads

It can have up to 244 leads with the lead pitch in the range of 0.65 to 0.2 mm. It also features

molded bumpers in its corners to help protect the leads from damage during handling and

assembly. PQFP is a large sub-family ranging from 5 x 5 mm to 40 x 40 mm square. The most

commonly used are the 28 x 28 mm body size with lead counts of either 160, 208, or 256. This

QFP sub family is low-cost and usually used for ASIC applications.

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Figure 5.10 shows a CQFP with clip lead frames and gull-wing leads. The chip is solder bumped

on a metallized ceramic substrate, which serves as the distribution layer between the chip and

the PCB. Encpasulant is used to “cement” the chip to the substrate in order to enhance the

solder joint reliability. Final package encapsulation may be done using urethane coating to

protect the ceramic circuitry. This package is available with lead pitch of 0.4 and 0.5 mm. One

prominent IC offered in this package is IBM Power PC 601 microprocessor.

FIG.5.10: Ceramic QFP

Chip carriers may be described as being low profile quad packages. The I/O terminals consist of

either metallized features on lead-less versions or discrete leads formed around or attached to

the side of the package on the leaded versions. There are five lead less versions (Type A, B, C, D

and E) with 0.05 or 0.04 inch lead pitch. These packages are ceramic, with hermetically sealed

metal or ceramic leads, as shown in figure 5.11. There are two leaded versions (Type A and B)

as shown the figure 5.12. This sub family is of low cost and used for packaging ASICs.

FIG.5.11: Leadless chip carrier

FIG.5.12: Plastic leaded chip carrier

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5.5 ARRAY PACKAGES

The array package family is characterized by an array of pins or pads placed in a regular array on

the package body. There are three main subfamilies under this category: pin grid array (PGA),

ball grid array (BGA) and chip scale (CS) packages. These packages enable the designer to

significantly increase the leadcounts, reduce the footprint of the package, and greatly reduce the

length of interconnection between the die and the board.

Pins and their electrical routing to the die in a pin grid array package is shown in figure 5.13.

FIG.5.13: Pin grid array package

PGA packages are available with ceramic and organic substrates. The pins are arranged across

the bottom of the package. The through-hole mounted PGAs typically use 100 x 100 mil or

staggered 50 x 100 mil centers. The ceramic PGA package body is typically constructed as a

cofired multilayered ceramic. One, two, or occasionally more wire bond tiers are used within the

package cavity for chip to package interconnect with wire bond, although TAB and C4

interconnects also can be used. PGA packages played a dominant role in high-density packaging

for many years, and were used for ASICs and microprocessors. They provided high pin count

and could dissipate high power (in the range of 4 – 10 W), and consequently were used in high-

performance computers. While PGA packages offered high performance, had many drawbacks

like high cost, through holes on the PCB for mounting (not SMT compatible), 100 mil pin pitch,

handling, and pin bending and insertion.

The expensive pins of PGA packages are replaced by cheaper solder balls in BGA packages.

The solder balls also provide SMT compatibility. Many companies like Motorola, IBM, Hitachi and

NEC went in a big way initially for the ceramic BGAs and subsequently to plastic BGAs. The

cross section of a BGA chip is shown in the figure 5.14.

25

FIG.5.14: BGA

A typical PBGA (Plastic Ball Grid Array) package consists of a BT (bismaleimide triazine)

laminate substrate with two metal layers and through-hole vias. The IC die is mounted on top of

the substrate, usually on a metal die attach pad or "flag", and is enclosed in a plastic mold (figure

5.15). The package may be enhanced electrically by adding additional metal layers for power and

ground, and thermally by adding thermal vias under the die. Wire bonding or solder bump

technology is used to attach the silicon chip to the substrate. Pin counts for BGA packages are

now nearing 1000, with 300 to 600 being standard. Ball pitches are decreasing from 1.27 mm to

1.0 mm. Standard metal trace widths are 0.003" on a 0.006" pitch, and routing vias typically

consist of a 0.010" hole and a 0.020" land.

FIG.5.15: Plastic ball grid array

BGA packages are gaining acceptance in the electronic industry as low-cost alternatives to fine-

pitch QFPs. The most evident advantage that BGA has over QFP is the package area. BGAs

typically are 20 to 25% smaller than QFPs. When total board area to place and route the package

is taken into account, the size reduction can be as much as 50%. A more serious consideration

when dealing with high pin count QFPs is the lead pitch. To accommodate the required number of

I/O, lead pitches of 0.65mm are not uncommon and can be as small as 0.50mm. This presents

several problems when working with a QFP. First, because the small leads are very fragile,

special handling is required for manufacturing, testing, shipping, and final placement of the

26

package on a PWB. Soldering is also a consideration. QFPs are held to very stringent coplanarity

specifications to insure solderability. In addition, visual inspections of solder joints are required to

insure quality. Another requirement due to its small lead pitch is placement accuracy. A typical

QFP must be placed with an accuracy of + 0.003," whereas the same specification for a typical

BGA is + 0.012". In addition to the mechanical considerations, BGA packages offer better

thermal and electrical characteristics than QFPs. The long fingers of the QFP leadframe are more

inductive than the shorter traces of a BGA substrate. This difference can be even greater when

power and ground planes are added to the BGA substrate. The ability to add thermal vias directly

under the IC die improves the thermal performance of a BGA package. The most obvious

drawback to using a BGA package is its marginally higher cost. The need for visual inspection of

the solder joints is also eliminated with improved soldering process.

Chip scale packages (CSPs) are not very different from other forms of array packaging. Industry

defines CSPs as those packages that have an area less than 1.2 times the die size. Sometimes

CSPs are defined as array packages with ball pitches less than 1.0 mm. CSPs offer high-speed

electrical access to memory and RF components without the need for major captive investments.

There are many variations of CSP technologies at present. One sample of chip scale package

(Sharp) is shown in the figure 5.16.

FIG.5.16: Chip scale package

6. MULTICHIP MODULES

Multi chip modules interconnect and package more than one bare integrated circuit chip (die).

This enables the designer to drastically reduce the interchip distance (delay), and lead to

significant reduction in the size of the product. Besides conventional ceramics and glass epoxies,

even silicon can be used as substrate material. In some specific instances, the interconnect line

widths as low as 12 microns were used. However, microminiature multichip modules are more

27

expensive per unit substrate area than are conventional packaging technologies. The multichip

modules are divided broadly into three types depending on the substrate dielectric construction.

MCM-L technology uses laminated dielectric like printed wiring board substrates. MCM-C

technology uses ceramic dielectric material. MCM-D technology uses deposited dielectric.

MCM-L Packa ging : These packages are constructed with printed circuit board laminates. The

interconnections on the laminate are almost always copper, and are created by photo imaging

either through subtractive or additive deposition process. Vias are created through drilling,

electroless plating followed by electroplating. When the dimension of vias is very small (less

than 100 microns) laser ablasion is used. The dice are attached either through wire bonding or

flip chip process. Metal constraining cores or supporting planes are used for thermal

management when required. The process sequence is shown in the figure 6.1

FIG.6.1 MCM-L packaging

MCM-C Packaging : The technology used in this packaging is normally referred to as hybrid

microcircuit technology. Unlike hybrid microcircuits, the number of active devices in a MCM-C

package is far greater than passive devices. The substrates in this type of packaging are

ceramics or glass ceramic alternatives. Conductors are of fireable metal materials, such as

tungsten or molybdenum, and the screen-printable frit metal thick-film conductors, such as gold

silver, palladium and copper. Conductor widths are generally greater than 125 microns. Vias are

formed during the conductor screen printing operation and are of the same material as the

conductors.

FIG.6.2: MCM-C Package

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MCM-D Packaging : This technology is based on depositing a dielectric over a substrate, which is

usually ceramic, silicon, copper, or other metals or metal composites. The dielectrics used can

be broadly classified into two categories: polymeric and inorganic. While SiO2 has been

traditionally used in ICs as a dielectric, polymers have the capability to form thicker layers, lower

cost and higher speed of deposition, better planarization, and lower dielectric constant. A variety

of polymers with different properties are available from different vendors. Aluminum, copper and

gold are used for conductor metallization. Copper and nickel are the most common via fill

materials.

Applications of MCM-D packaging have traditionally been performance driven and are dominated

by high-clock rate and I/O intensive requirements. Mainframe computers, and military and space

applications have used this technology. For example NEC’s SX-3/SX-X and IBM’s ES 9000 are

based on the MCM-D technology. It is expected that interconnect rich architectures like tightly

coupled microprocessors, crossbar switches, multiple bus architectures, and cache memory

systems will use this technology.

FIG.6.3: MCM-D package

7. SUMMARY

The integrated circuits have to be packaged for them to be used in an electronic system. The

silicon die has to be protected from the environment, electrical connections have to be created to

the external world, and the heat generated is effectively transferred to environment to maintain

the silicon at safe temperatures. All these requirements have to be met without significantly

reducing the performance of the integrated circuit. Semiconductor packaging can be broadly

divided into two categories: Single Chip Packaging (SCM) and Multi Chip Packaging (MCM).

Commercially available SCMs can be broadly fitted into four families: in-line (SIP, PDIP,

CERDIP), small outline (SOJ, SOP, TSOP), quad surface mount (PLCC, LDCC, PQFP,

CERQUAD), grid array (PGA, BGA). The MCMs are classified into MCM-L, MCM-C and MCM-D

packages. Each packaging style provides a certain combination of characteristics, which is an

optimum for some range of applications. The important characteristics of a package are

29

packaging efficiency, leadcount, thermal performance, electrical performance, size and weight,

and reliability.

A variety of materials are used in creating semiconductor packages to serve as electrical

conductors or insulators, provide structure and form, provide thermal paths, and protect the

circuits from environmental factors. They greatly influence the package performance. The

materials have to be carefully chosen, some times new materials have to be created to ensure

that the materials used are compatible with each other while meeting the requirements of the

package.

There are two types of interconnections encountered in semiconductor packages: die-to-

substrate interconnection, and interconnection on substrates. The three popular technologies for

creating die-to-substrate interconnections in semiconductor packages are wire bonding, tape

automated bonding (TAB), and controlled collapse chip connection (C4). While wire bonding is a

mature technology and most extensively used for die-to-substrate interconnections, the use of C4

technology in packaging large leadcount ICs is steadily increasing. TAB technology has

advantages of being light, thin, short, small, and flexibile. These advantages will enable it to

maintain its edge in a wide variety of applications such as watches, calculators, cameras,

sensors, and hearing aids. However, the TAB process by its very nature is economical mainly in

large volume production. MCMs use both thick film and thin film technologies for creating

interconnections, especially on the substrates.

There are three major package construction processes: plastic, cofired ceramic, and pressed

ceramic processes. Ceramic substrates offer the highest wiring density and good thermal

performance. However plastic encapsulation offer many advantages over ceramic packages in

the areas of size, weight, performance, cost, reliability, and availability.

While small outline and quad flat packages are the most extensively used in present day

electronic products, the use of array packages in the form of plastic ball grid arrays and chip scale

packages is increasing. New variants of array packages are being introduced all the time.