Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU

Implementing LDPC Implementing LDPC Decoding on Network-On-Decoding on Network-On-

ChipChipT. Theocharides, G. Link, N. Vijaykrishnan, M.

J. Irwin Penn State UniversityInternational Conference on VLSI Design 200

5

Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU

OutlineOutline• Intro• Message Passing• Iterative Decoding• Word length• Processing Elements• Virtual & Physical nodes• Network on Chip• Packets• Message Decoding Behavior• Bit node PE & Check node PE• Power Optimization• Conclusion & Comparison

Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU

IntroIntro• Addressing problem are either limited in

the types of LDPC codes, or constrained by hardware.

• Reconfigurable for different block sizes and code rates.

Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU

Message PassingMessage Passing• Start from bit function unit• Message passing iterations are performed

by the two computation units.

Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU

Iterative DecodingIterative Decoding• Check node operation

where– This function is implemented by using a ROM

based look-up table (LUT).

oldioldnoldold

newi

llrBllrBllrBllrBB

llr

___1_0

_

oldi

oldi

llr

llr

newieellrB

_

_

11ln_

Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU

Iterative DecodingIterative Decoding• Bit node operation

• stored_llr describes the previously stored logarithmic likelihood ration for the bit.

newininewi llrllrllrllrllrstoredllr _10_ _

Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU

Word lengthWord length• Word length is critical parameter.

– Performance– Power consumption

• A large data word results in a lower BER even in noisy channels.– Sign-magnitude representation– 16 bit word length

Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU

Processing element (PE)Processing element (PE)• Bit and check nodes act as PEs.• PEs communicate via on-chip routers.• Each PE has a dedicated memory to store

configuration information.

Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU

Virtual & Physical nodesVirtual & Physical nodes• Virtual nodes cannot

be mapped all at once on a single chip.

A B C D E F G H I

a b c d e f

VN

PN

Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU

Network on Chip (NoC)Network on Chip (NoC)• Inter-PE communication is handled by an

on-chip network consisting of a number of small on-chip routers.

• A full packet of data moves one hop per clock cycle.

• Losing a single packet is catastrophic to LDPC computation.

Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU

PacketsPackets• Physical destination address

• Virtual identification information

• Packet Mark (1 bit)

pnofnumber __log2

pnpervnofnumber ____log2

Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU

Packet SizePacket Size• 48bit for PN * 25, VN * 64, MAX=16

– Header 16 bit• Physical address 5 bit• Virtual address 6 bit• Max 4 bit• Reserved 1bit

– Data 16 bit * 2• Word length 16 bit

Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU

Message Decoding BehaviorMessage Decoding Behavior• Analog signal arrives and is converted to llr valu

es after ADC conversion, the llr values are grouped into message blocks.

• Two blocks are decoded in parallel. (66% network traffic)

Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU

Bit Node PEBit Node PE• Node has 48 bit input, output ports.• Data concentrator directs values to accumulator base on

VID.• Once all input values for a given virtual bit node are

received, the computation proceeds to the execution unit.

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Check Node PECheck Node PE• Node supports the simultaneous decoding of two

independent message blocks.

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ResultsResults• 16 physical bit nodes• 9 physical check

nodes• 64 virtual nodes• 2D Mesh topology

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Power ConsumptionPower Consumption• 750Mbps@500MHz 34.8W (N=1024)

– interconnect 43%– check nodes 23%– bit nodes 22%– leakage 12%

Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU

Power Consumption (detail)Power Consumption (detail)• A range between 25% and 40% of the total data

passed between each node are either zero or infinity. (High switch activity)

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Encoding ValuesEncoding Values• If the result is either zero or infinity, we set S1

and S2 to corresponding value.

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ResultResult• 750Mbps@500MHz (N=1024)

– 34.8W 30.36W (-12.75%)

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Early TerminationEarly Termination

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Result (+Early Termination)Result (+Early Termination)• 750Mbps@500MHz (N=1024)

– 34.8W 30.36W (-12.75%) 24.32W (-30%)

Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU

ConclusionConclusion• Network-on-chip interconnect is scalable.• Multiple LDPC codes of varying types are

supported.• Design can be extended into reconfigurabl

e low-power decoders.

Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU

My conclusionMy conclusion• Distance between nodes must be

considered.• Parameters (number of physical nodes,

node placement) are the keys.• Two messages must have the same

latency.• Syndrome test can offer early termination

Team LDPC, SoC Lab. Graduate InstTeam LDPC, SoC Lab. Graduate Institute of CSIE, NTUitute of CSIE, NTU

ComparisonComparisonThis design Our design

Number Representation

Sign-magnitude 2’s complement & sign-magnitude

Code type Arbitrary QC-LDPC

Word Length 16 bit 6 bit

Data Overhead Packet header (48bit) None

Rate ¾ ½

ROM/LUT Required Not required

HUE N/A >97.56% (40iter)

Memory Req. Double size Single size

Strategy Dual code simultaneous Single

Algorithm SPA SMSA/SPA

Addressing Router & HFT Counter

Reconfigurable Feasible Feasible