TI MSP430 Learning Materials

8/11/2019 TI MSP430 Learning Materials

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Lecture 2MSP430 Architecture

MSP430 Teaching Materials

Texas Instruments IncorporatedUniversity of Beira Interior (PT)

Pedro Dinis Gaspar, Antnio Esprito Santo, Bruno Ribeiro, Humberto SantosUniversity of Beira Interior, Electromechanical Engineering Department

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Copyright 2009 Texas InstrumentsAll Rights Reserved

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Contents (1/3)

MSP430 architecture:

Main characteristics

Architecture topology Address space

Interrupt vector table

Central Processing Unit (MSP430 CPU)

Central Processing Unit (MSP430X CPU)

Addressing modes

Instructions set


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Contents (2/3)

Exploring the addressing modes of the MSP430architecture:

Instruction format:

Instruction format I: Double operand

Instruction format II: Single operand

Jump instructions format

Emulated instructions

Addressing modes:

Register mode

Indexed mode

Symbolic mode

Absolute mode

Indirect register mode

Indirect auto-increment mode

Immediate mode


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Contents (3/3)

Exploring the addressing modes of the MSP430Xarchitecture:

Instruction format in the MSP430X CPU

Exceptions to the representation of the extended Format IIinstructions

Extended emulated instructions

MSP430X address instructions

MSP430X CPU addressing modes


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Introduction

A comprehensive description of the MSP430 architecture,covering its:

Main characteristics; Device architecture;

Address space;

Interrupt vector table;

Central Processing Unit (MSP430 CPU and MSP430X CPU);

7 seven addressing modes and instruction set composed of:

27 base opcodes;

24 emulated instructions.


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Microcontroller characteristics

Integration: Able to implement a whole design onto a singlechip.

Cost: Are usually low-cost devices (a few $ each);

Clock frequency: Compared with other devices(microprocessors and DSPs), MCUs use a low clock frequency:

MCUs today run up to 100 MHz/100 MIPS (Million

Instructions Per Second).

Power consumption: Low power (battery operation);

Bits: 4 bits (older devices) to 32 bits devices;

Memory: Limited available memory, usually less than 1 MByte;

Input/Output (I/O): Low to high (8 to 150) pin-out count.


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MSP430 main characteristics (1/3)

Low power consumption:

0.1 A for RAM data retention;

0.8 A for real-time clock mode operation;

250 A/MIPS during active operation.

Low operation voltage (from 1.8 V to 3.6 V);

< 1 s clock start-up;

< 50 nA port leakage;

Zero-power Brown-Out Reset (BOR).


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On-chip analogue features:

10/12/16-bit Analogue-to-Digital Converter (ADC);

12-bit dual Digital-to-Analogue Converter (DAC);

Comparator-gated timers;

Operational Amplifiers (Op Amps);

Supply Voltage Supervisor (SVS).

16 bit RISC CPU:

Compact core design reduces power consumption and cost;

16-bit data bus;

27 core instructions;

7 addressing modes;

Extensive vectored-interrupt capability.


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Flexibility:

Up to 256 kByte Flash;

Up to 100 pins;

USART, I2C, Timers; LCD driver;

Embedded emulation;

And many more peripherals modules

Microcontroller performance:

Instruction processing on either bits, bytes or words

Reduced instructions set;

Compiler efficient; Wide range of peripherals;

Flexible clock system.


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Address Space

Mapped into a single, contiguous address space:

Flash/ROM: All code, tables, and hard-coded constantsreside in this memory space.

Information memory: Variables needed for the nextpower up can be stored here during power down. It can alsobe used as code memory.

Boot memory: The bootstrap loader performs some of the

same functions as the JTAG interface.

RAM: RAM is used for both code and data.

Peripheral Modules: Peripheral modules consist of all on-chip peripheral registers that are mapped into the address

space.

Special Function Registers (SFRs): Some peripheralfunctions are mapped into memory with special dedicatedfunctions.


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Memory Map

Memory Address Description Access

End: 0FFFFh

Start: 0FFE0h

Interrupt Vector TableWord/Byte

End: 0FFDFh

Flash/ROM

0F800hStart *:01100h

Word/Byte

010FFhEnd *:

0107Fh Information Memory

Start: 01000h (Flash devices only)

Word/Byte

End: 0FFFh

Start: 0C00h

Boot Memory(Flash devices only) Word/Byte

09FFhEnd *:

027Fh RAM

Start: 0200h

Word/Byte

End: 01FFh

Start: 0100h

16-bit Peripheral modules Word

End: 00FFh

Start: 0010h8-bit Peripheral modules Byte

End: 000Fh

Start: 0000hSpecial Function Registers Byte


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Interrupt vector table

Mapped at the very end of memory space (upper 16words of Flash/ROM): 0FFE0h - 0FFFEh (4xx devices);

Priority of the interrupt vector increases with the word

address.


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Central Processing Unit (MSP430 CPU) (1/7)

RISC (Reduced Instructions Set Computing) architecture: Instructions are reduced to the basic ones (short set):

27 physical instructions;

24 emulated instructions.

This provides simpler and faster instruction decoding;

Interconnect by a using a common memory address bus(MAB) and memory data bus (MDB) - Von Neumannarchitecture: Makes use of only one storage structure for data and

instructions sets.

The separation of the storage processing unit is implicit;

Instructions are treated as data (programmable).


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RISC (Reduced Instructions Set Computing) typearchitecture:

Uses a 3-stage instruction pipeline containing:

Instruction decoding; 16 bit ALU;

4 dedicated-use registers;

12 working registers.

Address bus has 16 bit so it can address 64 kB (includingRAM + Flash + Registers);

Arithmetic Logic Unit (ALU): Addition, subtraction, comparison and logical (AND, OR,

XOR) operations;

Operations can affect the overflow, zero, negative, and carryflags of the SR (Status Register).


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Incorporates sixteen 16-bit registers:

4 registers (R0, R1, R2 and R3) have dedicated functions;

12 register are working registers (R4 to R15) for general

use.

R0: Program Counter (PC):

Points to the next instruction to be read from memory andexecuted by the CPU.

R1: Stack Pointer (SP):

1st: stack can be used by user to store data for later use(instructions: store by PUSH, retrieve by POP);

2nd: stack can be used by user or by compiler for subroutineparameters (PUSH, POP in calling routine; addressed via offsetcalculation on stack pointer (SP) in called subroutine);


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R1: Stack Pointer (SP) (continued):

3rd: used by subroutine calls to store the program countervalue for return at subroutine's end (RET);

4th: used by interrupt - system stores the actual PC valuefirst, then the actual status register content (on top of stack)on return from interrupt (RETI) the system get the same

status as just before the interrupt happened (as long as nonehas changed the value on TOS) and the same programcounter value from stack.


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R2: Status Register (SR):

Stores status and control bits;

System flags are changed automatically by the CPU;

Reserved bits are used to support the constant generator.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved for CG1 V SCG1 SCG0 OSCOFF CPUOFF GIE N Z C

Bit Description

8 V Overflow bit. V = 1 Result of an arithmetic operation overflows the signed-variable range.

7 SCG1 System clock generator 0. SCG1 = 1 DCO generator is turned off if not used for MCLK or SMCLK

6 SCG0 System clock generator 1. SCG0 = 1 FLL+ loop control is turned off

5 OSCOFF Oscillator Off. OSCOFF = 1 turns off LFXT1 when it is not used for MCLK or SMCLK

4 CPUOFF CPU off. CPUOFF = 1 disable CPU core.3 GIE General interrupt enable. GIE = 1 enables maskable interrupts.

2 N Negative flag. N = 1 result of a byte or word operation is negative.

1 Z Zero flag. Z = 1 result of a byte or word operation is 0.

0 C Carry flag. C = 1 result of a byte or word operation produced a carry.


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R2/R3: Constant Generator Registers (CG1/CG2):

Depending of the source-register addressing modes (As)value, six constants can be generated without code word or

code memory access to retrieve them.

This is a very powerful feature which allows theimplementation of emulated instructions, for example,instead of implement a core instruction for an increment the

constant generator is used.Register As Constant Remarks

R2 00 - Register mode

R2 01 (0) Absolute mode

R2 10 00004h +4, bit processing


R3 00 00000h 0, word processing

R3 01 00001h +1R3 10 00002h +2, bit processing

R3 11 0FFFFh -1, word processing


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R4 - R15: GeneralPurpose Registers:

These general-purpose registers are adequate to store dataregisters, address pointers, or index values and can be

accessed with byte or word instructions.


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Central Processing Unit (MSP430X CPU)(1/10)

Main features of the MSP430X CPU architecture:

The MSP430X CPU extends the addressing capabilities of theMSP430 family beyond 64 kB to 1 MB;

To achieve this, some changes have been made to theaddressing modes and two new types of instructions havebeen added;

One instruction type allows access to the entire addressspace, and the other is designed for address calculations;

The MSP430X CPU address bus has 20 bits, although thedata bus still has 16 bits. Memory accesses to 8-bit, 16-bit

and 20-bit data are supported;

Despite these changes, the MSP430X CPU remainscompatible with the MSP430 CPU, having a similar numberof registers.


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Organization of the MSP430X CPU: Although the MSP430X CPU structure is

similar to that of the MSP430 CPU, thereare some differences that will now be

highlighted;

With the exception of the status registerSR, all MSP430X registers are 20 bits;

The CPU can now process 20-bit or 16-bit data.



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The MSP430X CPU has 16 registers, some of which havespecial use:

R0 (PC) Program Counter: Has the same function as the MSP430 CPU, although now it

has 20 bits.

R1 (SP) Stack Pointer:

Has the same function as the MSP430 CPU, although now ithas 20 bits.

R2 (SR) Status Register:

Has the same function as the MSP430 CPU, but it still has 16bits.


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R2 (SR) Status Register:

Description of the SR bits:


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R2 (SR/CG1) and R3 (CG2) Constant Generators:

Registers R2 and R3 can be used to generate six differentconstants commonly used in programming, without adding

an additional 16-bit word to the instruction;

The constants are fixed and are selected by the (As) bits ofthe instruction. (As) selects the addressing mode.

Values of constants

generated:


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R2 (SR/CG1) and R3 (CG2) Constant Generators:

Whenever the operand is one of the six constants, theregisters are selected automatically;

Therefore, when used in constant mode, registers R2 and R3cannot be used as source registers.

R4-R15 General-purpose registers:

Have the same function as in the MSP430 CPU, althoughthey now have 20 bits;

These registers can process 8-bit, 16-bit or 20-bit data;

If a byte is written to one of these registers it takes bits 7:0,the bits 19:8 are filled with zeroes. If a word is written toone of these registers it takes bits 15:0, the bits 19:16 arefilled with zeroes.


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Handling byte data (8 bits) using the suffix . B:


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Handling word data (16 bits) using the suffix . W:


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Manipulation of a 20-bit address using the suffix . A:


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Addressing modes

7 addressing modes for the source operand:

4 addressing modes for the destination operand: Register mode; Indexed mode; Symbolic mode; Absolute

mode.

For the destination operand, two additional addressingmodes can be emulated.


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Instruction set

27 core instructions;

24 emulated instructions;

The instruction set is orthogonal;

The core instructions have unique opcodes decoded bythe CPU, while the emulated ones need assemblers andcompilers for their mnemonics;

There are three core-instruction formats: Double operand;

Single operand;

Program flow control - Jump.


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E l i th dd i d f th


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Organization of the MSP430 CPU: 16-bit address bus (MAB) and 16-bit

data bus (MDB).

Both registers and memory can beaccessed either in word format or in byteformat.

Allows the direct transfer of data

between memory, without passingthrough the registers.

The 16-bit registers can be accesseddirectly through the instructions, someof which run in a single clock cycle.

Some of the constants most used inprogramming can be obtained from theconstant generator.

Exploring the addressing modes of theMSP430 architecture (2/11)

E l i th dd i d f th


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Organization of the MSP430 CPU(continued):

The architecture has a 16 bit Arithmetic

Logic Unit (ALU).

Carrying out operations affects the stateof the following flags:

Zero (Z); Carry (C); Overflow (V); Negative (N).

The MCLK (Master) clock signal drivesthe CPU.



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Exploring the addressing modes of the


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R1 (SP) Stack Pointer:

This register is used by the MSP430 CPU to store the returnaddress of routines or interrupts;

Each time the data stack is accessed, the SP is incrementedor decremented automatically;

The user should be careful to initialise the SP register withthe valid address of the data stack in RAM;

The stack pointer SP always points to an even address, soits LSB is always zero.



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R2 SR/CG1 & R3 CG2 (Status Register):

The status of the MSP430 CPU is defined by a set of bits

contained in register R2 (SR) (status register);

This register can only be accessed through registeraddressing mode;

All other addressing modes are reserved to support theconstants generator;

The organization of the individual bits of register R2 isshown in the following figure:



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R2 SR/CG1 & R3 CG2 (Status Register):15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved for CG1 V SCG1 SCG0 OSCOFF CPUOFF GIE N Z C

Bit Description

8 V Overflow bit.

V = 1 Result of an arithmetic operation overflows the signed-variable range.7 SCG1 System clock generator 1.

SCG1 = 1 DCO generator is turned off if not used for MCLK or SMCLK6 SCG0 System clock generator 0.

SCG0 = 1 FLL+ loop control is turned off

5 OSCOFF Oscillator Off.

OSCOFF = 1 turns off LFXT1 when it is not used for MCLK or SMCLK4 CPUOFF CPU off.

CPUOFF = 1 disable CPU core.3 GIE General Interrupt Enable.

GIE = 1 enables maskable interrupts.

2 N Negative flag.

N = 1 result of a byte or word operation is negative.1 Z Zero flag.

Z = 1 result of a byte or word operation is 0.0 C Carry flag.

C = 1 result of a byte or word operation produced a carry.



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R2 SR/CG1 & R3 CG2 (Constant Generators):

Six different constants commonly used in programming canbe generated using the registers R2 and R3, without the

need to add a 16-bit word of code to the instruction; The constants are fixed and are selected by the instruction

bits (As). These control the addressing mode.

Register As Constant RemarksR2 00 - Register mode

R2 01 (0) Absolute mode



R3 00 00000h 0, word processing

R3 01 00001h +1


R3 11 0FFFFh -1, word processing



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R4-R15: General-purpose registers:

The general purpose registers R4 toR15 can be used as data registers,data pointers and indices. They canbe accessed either as a byte or as aword;

These registers support operations

on words or bytes;

In the example to the right, thecontents of the least significant byte

of register R5 (0x8F) is added to thecontents of the memory addresspointed to by the register R6 (0x12h);



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The contents of the memory addressis updated with the result of the

operation (0xA1);

The status flags of the CPU in the SRare updated after the execution of

the instruction.



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The contents of the memory addresspointed to by R6 (0x5F) is added to

the contents of the least significantbyte of register R5 (0x02);

The result of the operation (0x61) is

stored in the least significant byte ofregister R5;

Meanwhile, the most significant byte

of register R5 is set to zero;

The system flags in SR are updatedin accordance with the result.

I t ti f t (1/4)


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Instructions format (1/4)

In addition to the 27 instructions of the CPU there are 24emulated instructions;

The CPU coding is unique;

The emulated instructions make reading and writingcode more easy, but do not have their own op-codes;

Emulated instructions are replaced automatically byinstructions from the CPU;

There are no penalties for using emulated instructions. There are three formats used to encode instructions for

processing by the CPU core:

Double operand;

Single operand;

Jumps.

I t ti f t (2/4)


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The instructions for double and single operands, dependon the suffix used, (. W) word or (. B) byte.

These suffixes allow word or byte data access;

If the suffix is ignored, the instruction processes worddata by default.



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The source and destination of the data operated by aninstruction are defined by the following fields:

src: source operand address, as defined in As and S-reg;

dst: destination operand address, as defined in Ad and D-reg; As: addressing bits used to define the addressing mode used

by the source operand;

S-reg: register used by the source operand;

Ad: Addressing bits used to define the addressing mode usedby the destination operand;

D-reg: register used by the destination operand;

B/W: word or byte access definition bit.



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While all addresses within the address space are valid, itis the responsibility of the user to check that the type ofaccess is valid.

Example: the contents of the flash memory can be usedas a source operand, but can only be written to in certainconditions.



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Organization of instructions with two operands:

Double operand instructions:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Op-code S-Reg Ad B/W As D-Reg

Mnemonic Operation Description

Arithmetic instructions

ADD( . B or . W) sr c, dst src+dstdst Add source to destination

ADDC( . B or . W) sr c, dst src+dst+Cdst Add source and carry to destination

DADD( . B or . W) sr c, dst src+dst+Cdst (dec) Decimal add source and carry to destination

SUB( . B or . W) sr c, dst dst+.not.src+1dst Subtract source from destination

SUBC( . B or . W) sr c, dst dst+.not.src+Cdst Subtract source and not carry from destination

Logical and register control instructions

AND( . B or . W) sr c, dst src.and.dstdst AND source with destination

BI C( . B or . W) sr c, dst .not.src.and.dstdst Clear bits in destination

BI S( . B or . W) sr c, dst src.or.dstdst Set bits in destinationBI T( . B or . W) sr c, dst src.and.dst Test bits in destination

XOR( . B or . W) sr c, dst src.xor.dstdst XOR source with destination

Data instructions

CMP(. B or . W) sr c, dst dst-src Compare source to destination

MOV( . B or . W) sr c, dst srcdst Move source to destination

Examples: double operand (1/3)


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Move the contents of register R5 to register R4:

MOV R5, R4

Instruction code: 0x4504

This instruction uses 1 word;

The instruction coding specifies that the CPU must perform a16-bit data MOV instruction, with the contents of register R5

as the source and with register R4 as the destination.

Op-code S-reg Ad B/W As D-reg

0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0

MOV R5 Register 16-Bits Register R4



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Move the contents of register R5 to the address inmemory TONI:

MOV R5, TONI


This instruction uses 2 words;

The instruction coding specifies that the CPU must perform a16-bit data MOV instruction using the contents of register R5to the memory address pointed to by X1 + PC;

The word X1 is stored in the word following the instruction.


0 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0

MOV R5 Symbolic 16 Bits Register PC



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Move the contents between the memory addresses EDENand TONI:MOV EDEN, TONI



The instruction coding specifies that the CPU must perform a16-bit data MOV instruction using the contents of the EDENmemory address pointed to by X1 + PC to the TONI memoryaddress pointed to by X2 + PC;

The word X1 followed by the word X2 are stored after theinstruction.

Op-code S-reg Ad B/W As D-reg0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0MOV PC Symbolic 16-Bits Symbolic PC



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The instructions with one operand are coded using thefollowing structure:

Single operand instructions:

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Op-code B/W Ad D/S-Reg

Mnemonic Operation Description


RRA( . B or . W) dst MSBMSBLSBC Roll destination right

RRC( . B or . W) dst CMSBLSBC Roll destination right through (from) carry

SWPB( or . W) dst Swap bytes Swap bytes in destination

SXT dst bit 7bit 8bit 15 Sign extend destination

PUSH( . B or . W) sr c SP-2SP, src@SP Push source on stack

Program flow control instructions

CALL( . B or . W) dst SP-2SP, PC+2@SPdstPC

Subroutine call to destination

RETI TOSSR, SP+2SPTOSPC, SP+2SP

Return from interrupt

Examples: single operand (1/2)


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Move the contents of register R5 to the right with carryflag:

RRC R5



The instruction coding specifies that the CPU must perform a16-bit data RRC instruction using the contents of register R5.

Op-code B/W Ad D-reg

0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1

RRC 16 bits Register R5



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Rotate the contents of memory TONI to the right withcarry flag:

RRC TONI



The instruction coding specifies that the CPU must perform a16-bit data RRC instruction pointed to by X1 + PC;

Word X1 is stored in the word following the instruction.

Op-code B/W Ad D-reg

0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0

RRC 16 bits Symbolic PC


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Jump instructions format (2/3)


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p ( / )

The op-code always takes the value 001b, indicating thatit is a jump instruction;

The condition on which a jump occurs depends on the Cfield consisting of 3 bits, and may take the followingvalues:

000b: jump if not equal;

001b: jump if equal; 010b: jump if carry flag equal to zero;

011b: jump if carry flag equal to one;

100b: jump if negative (N = 1);

101b: jump if greater than or equal (N=V or (N OR V=0));

110b: jump if lower (N! = V or (V XOR N = 1));

111b: unconditional jump.


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Examples: jump format (1/2)


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Continue execution at the label mai n if the carry flag isactive:

J C mai n

Instruction code: 0x2FE4


The instruction coding specifies that the PC must be loadedwith the value resulting from the offset - 0x1C being appliedto the previous expression.

Op-code C 10-Bit PC offset

0 0 1 0 1 1 1 1 1 1 1 0 0 1 0 0JC Carry = 1 0x1C

Examples: jump format (2/2)


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Continue to unconditionally execute code at the labelmai n:

J MP mai n

Instruction code: 0x3FE3


The instruction coding specifies that the PC must be loadedwith the value resulting from the offset - 0x1D being appliedto the previous expression.

Op-code C 10-Bit PC offset

0 0 1 1 1 1 1 1 1 1 1 0 0 0 1 1

JMP unconditional 0x1D

Emulated instructions (1/3)


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In addition to the 27 CPU instructions, the following 24emulated instructions can also be used:

Mnemonic Operation Emulation Description

Arithmetic instructions

ADC(.B or .W) dst dst+Cdst ADDC(.B or .W) #0,dst Add carry to destination

DADC(.B or .W) dst dst+Cdst (decimally) DADD(.B or .W) #0,dst Decimal add carry todestination

DEC(.B or .W) dst dst-1dst SUB(.B or .W) #1,dst Decrement destination

DECD(.B or .W) dst dst-2dst SUB(.B or .W) #2,dst Decrement destination twice

INC(.B or .W) dst dst+1dst ADD(.B or .W) #1,dst Increment destination

INCD(.B or .W) dst dst+2dst ADD(.B or .W) #2,dst Increment destination twice

SBC(.B or .W) dst dst+0FFFFh+Cdstdst+0FFhdst

SUBC(.B or .W) #0,dst Subtract source and borrow/.NOT. carry from dest.



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In addition to the 27 CPU instructions, the following 24emulated instructions can also be used (continued):



INV(.B or .W) dst .NOT.dstdst XOR(.B or .W) #0(FF)FFh,dst Invert bits in destination

RLA(.B or .W) dst CMSBMSB-1LSB+1LSB0

ADD(.B or .W) dst,dst Rotate left arithmetically

RLC(.B or .W) dst CMSBMSB-1LSB+1LSBC

ADDC(.B or .W) dst,dst Rotate left through carry

Program flow control

BR dst dstPC MOV dst,PC Branch to destination

DINT 0GIE BIC #8,SR Disable (general)

interruptsEINT 1GIE BIS #8,SR Enable (general) interrupts

NOP None MOV #0,R3 No operation

RET @SPPCSP+2SP

MOV @SP+,PC Return from subroutine



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In addition to the 27 CPU instructions, the following 24emulated instructions can also be used (continued):


Data instructions

CLR(.B or .W) dst 0dst MOV(.B or .W) #0,dst Clear destination

CLRC 0C BIC #1,SR Clear carry flag

CLRN 0N BIC #4,SR Clear negative flag

CLRZ 0Z BIC #2,SR Clear zero flag

POP(.B or .W) dst @SPtempSP+2SPtempdst

MOV(.B or .W) @SP+,dst Pop byte/word from stackto destination

SETC 1C BIS #1,SR Set carry flag

SETN 1N BIS #4,SR Set negative flagSETZ 1Z BIS #2,SR Set zero flag

TST(.B or .W) dst dst + 0FFFFh + 1dst + 0FFh + 1

CMP(.B or .W) #0,dst Test destination

Examples: Emulated instructions (1/6)


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Clear the contents of register R5:

CLR R5


This instruction is equivalent to using MOV R3, R5 where R3takes the value #0.


0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 1MOV R3 Register 16 Bits Register R5



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Increment the content of register R5:

I NC R5


This instruction is equivalent to having ADD 0( R3) , R5 whereR3 takes the value #1.


0 1 0 1 0 0 1 1 0 0 0 1 0 1 0 1ADD R3 Register 16 Bits Indexed R5



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Decrement the contents of register R5:

DEC R5


This instruction is equivalent to using SUB 0( R3) , R5 whereR3 takes the value #1.


1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 1

SUB R3 Register 16 Bits Indexed R5



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Decrement by two the contents of register R5:

DECD R5


This instruction is equivalent to using SUB @R3, R5 where R3points to the value #2.


1 0 0 0 0 0 1 1 0 0 1 0 0 1 0 1

SUB R3 Register 16 Bits Indirect R5



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Do not carry out any operation:

NOP


This instruction is equivalent to using MOV R3, R3 and

therefore the contents of R3 are moved to itself.


0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 1

MOV R3 Register 16 Bits Register R3

UBI



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Add the carry flag to the register R5:

ADC R5


This instruction is equivalent to using ADDC R3, R5 where R3takes the value #0.


0 1 1 0 0 0 1 1 0 0 0 0 0 1 0 1

ADDC R3 Register 16 Bits Register R5

UBI

Addressing modes (1/2)


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There are seven addressing modes that take a sourceoperand and four of these addressing modes also take adestination operand;

The operands can be located in any memory spaceaddress, but the user needs to be aware of the effectsthat their accesses may have;

The addressing modes are selected by the As and Adfields that make up the instruction;

The following table summarizes the seven addressingmodes:


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Register mode (1/3)


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In Register addressing mode, the contents of a registeris used as the operand;

This type of addressing mode can be used both withsource and destination operands.


MOV R5,R4


Op-code S-reg Ad B/W As D-reg0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0MOV R5 Register 16-bit Register R4

UBI

Register mode (2/3)


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Move the contents of register R5 to register R4

MOV R5,R4


The 16-bit contents (B/ W = 0) of register R5 (S-reg) aretransferred to the register R4 (D-reg);

After the instruction fetch, the PC is incremented by 2 andpoints to the next instruction to be executed;

The addressing mode used for the source and destinationoperands is determined by As = 00 (Register mode) andAd = 0 (Register mode), respectively.


UBI

Register mode (3/3)


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Move the contents of register R5 to register R4 (cont.):MOV R5,R4



UBI

Indexed mode (1/4)


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In indexed mode, whether used to indicate the sourceaddress or the destination address, the sum of theregister contents and the signed offset point to thelocation in memory;

The offset value is stored in the word following theinstruction;

After the execution of the instruction, the contents ofregisters are not affected and the PC is incremented topoint to the next instruction to be executed;

This addressing mode is useful to access data stored intables. Apart from the registers PC and SR, all otherregisters can be used as an index in indexed mode.

UBI

Indexed mode (2/4)


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Move the byte pointed to by (R5 + 4) to the byte pointedto by (R4 + 1):

MOV.B 4(R5),1(R4)

Instruction code: 0x45D4

The instruction coding specifies that the byte (B/ W = 1)

pointed to by the sum of the contents of register R5(S- r eg = 0101) and the word X1 should be moved to the

memory address pointed to by the sum of register R4(D- r eg = 0100) and the contents of the word X2;

Op-code S-reg Ad B/W As D-reg0 1 0 0 0 1 0 1 1 1 0 1 0 1 0 0MOV R5 Indexed 8-bit Indexed R4


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Indexed mode (4/4)


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Move the byte pointed to by (R5 + 4) to the byte pointedto by (R4 + 1) (continued):

MOV.B 4(R5),1(R4)

UBI

Symbolic mode (1/5)


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In symbolic addressing mode, for either the source ordestination operands, the memory address is determinedby adding an offset to the program counter (PC) register;

The offset value is obtained by determining the codeposition in the memory, then calculating the differencebetween the offset address and the memory position thatshould be achieved;

The assembler determines the offset value and puts it inthe word following to the instruction;

After the execution of the instruction, the programcounter (PC) register is incremented in order to point tothe next instruction.

UBI

Symbolic mode (2/5)


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Although this mode of address is similar to register modeit request more cycles, but in this case, the programcounter (PC) is used to point to the data;

This addressing mode can be used to determine eitherthe source or the destination of the data.

UBI

Symbolic mode (3/5)


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Move the word pointed to by EDEN to the word pointed toby TONI:

MOV EDEN,TONI


The instruction coding specifies that the value pointed to bythe sum of the PC register contents (S- r eg = 0) and theword X1 should be moved to the memory address pointed to

by the sum of register PC contents (D- r eg = 0) and theword X2;

The words X1 and X2 are stored in the memory addresses

following the instruction.

Op-code S-reg Ad B/W As D-reg0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0MOV PC Symbolic 16-bit Symbolic PC

UBI

Symbolic mode (4/5)


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Move the word pointed to by EDEN to the word pointed toby TONI (continued):

MOV EDEN,TONI


The addressing mode used for the source and destinationoperands is controlled by the bits Ad = 1 (Symbolic mode)and As = 01 (Symbolic mode) because (D- r eg = 0000) and

(S- r eg = 0000), respectively.

Op-code S-reg Ad B/W As D-reg0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0MOV PC Symbolic 16-bit Symbolic PC

UBI

Symbolic mode (5/5)


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MOV EDEN,TONI

UBI

Absolute mode (1/4)


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In Absolute mode, the data memory address is placedafter the instruction;

The difference between this addressing mode andIndexed mode is that the register R2 is now used as anindex, using the constants generator to generate thevalue zero;

This addressing mode can be used to define either thesource address or the destination address.

UBI

Absolute mode (2/4)


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MOV &EDEN,&TONI


From the instruction coding it can be seen that the register

R2 has (S- r eg = 0010) and (D- r eg = 0010). Register R2 isused as an addresses index, in which the constant generatorloads the value zero;

When the contents of this register is added to the offset

value X1 or X2, the source and destination addresses areobtained;

The words X1 and X2 are stored in the memory addresses

following the instruction.

Op-code S-reg Ad B/W As D-reg0 1 0 0 0 0 1 0 1 0 0 1 0 0 1 0MOV R2/CG1 Absolute 16-bit Absolute R2/CG1

UBI

Absolute mode (3/4)


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Move the word pointed to by EDEN to the word pointed toby TONI (continued):

MOV &EDEN,&TONI


The addressing mode used for the source and destinationoperands is specified by the bits Ad = 1 (Absolute mode)and As = 01 (Absolute mode) because (D- r eg = 0010) and

(S- r eg = 0010), respectively.

Op-code S-reg Ad B/W As D-reg0 1 0 0 0 0 1 0 1 0 0 1 0 0 1 0MOV R2/CG1 Absolute 16-bit Absolute R2/CG1


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Indirect register mode (1/3)


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In Indirect register mode, any of the 16 CPU registerscan be used. If R2 or R3 are used then a constant valueis used as an operand, #0x04 for R2 and #0x02 for R3;

A restriction arises from the fact that this addressingmode can only be used to specify the source operandaddress in dual-operand instructions;

An alternative way to avoid this restriction is to useindexed mode to specify the destination operand address,with a zero offset.

UBI


h d i d b h d i d b


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Move the word pointed to by R5 to the word pointed to byR4:

MOV @R5,0(R4)

Instruction code: 0x45A4

The instruction coding specifies that register R5(S- r eg = 0101) uses the source address (As = 10);

The destination address is pointed to in Indexed mode(Ad = 1) by R4 (D- r eg = 0100), using a zero value offset.

Op-code S-reg Ad B/W As D-reg0 1 0 0 0 1 0 1 1 0 1 0 0 1 0 0MOV R5 Indexed 16-bit Indirect R4

UBI



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Move the word pointed to by R5 to the word pointed toby R4 (continued):

MOV @R5,0(R4)

UBI

Indirect auto-increment mode (1/3)

Thi dd i d i i il t th i


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This addressing mode is similar to the previous one;

The contents of source register is incremented accordingto the data type processed;

If the data value is byte, the source register isincremented by 1;

If the data value is a word, the source register isincremented by 2;

Note that this addressing mode can only be used tospecify the s o u r c e operand in dual-operand instructions.

UBI


M th d i t d t b R5 t th d i t d t


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Move the word pointed to by R5 to the word pointed toby R4, and increment the source pointer:

MOV @R5+,0(R4)

Instruction code: 0x45B4

The instruction coding specifies that the register R5(S- r eg = 0101) contains the source address (As = 11);

The destination address is pointed to in indexed mode by R4

(D- r eg = 0100), using a zero value offset; The execution of the instruction increments the contents of

register R5 by 2.

Op-code S-reg Ad B/W As D-reg0 1 0 0 0 1 0 1 1 0 1 1 0 1 0 0MOV R5 Indexed 16-bit Ind. aut. inc. R4

UBI


Mo e the o d pointed to b R5 to the o d pointed to


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Move the word pointed to by R5 to the word pointed toby R4, and increment the source pointer (continued):

MOV @R5+,0(R4)

UBI

Immediate mode (1/2)

The Immediate addressing mode allows values to be


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The Immediate addressing mode allows values to beloaded directly into registers or memory addresses. Itcan only be used with source operands.

Move the value 0x0200 to R5:

MOV #0x0200,R5


The instruction coding specifies that the register PC(S- r eg = 0000) is used to define the address of the word inmemory that loads the register R5 (D- r eg = 0101)with (As = 11).

Op-code S-reg Ad B/W As D-reg0 1 0 0 0 0 0 0 0 0 1 1 0 1 0 1MOV PC Register 16-bit Immediate R5

UBI

Immediate mode (2/2)

Move the value 0x0200 to R5 (continued):


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Move the value 0x0200 to R5 (continued):

MOV 0x0200,R5

UBI

Instruction format in the MSP430X CPU(1/2)

There are three possibilities to choose between the


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There are three possibilities to choose between theinstructions of the MSP430 CPU and MSP430X CPU:

Use only the MSP430 CPU instructions. The followingrules must be followed, with the exception of the

instructions CALLA/RETA, BRA:

Put all the data in memory below 64 kB and accessthe data using 16-bit pointers;

Place the routines at an address within the range

PC 32 kB;

No 20-bits data.

Use only the MSP430X CPU instructions. This causes a

reduction in the application execution speed and anincrease in the memory space occupied by the program;

Use an appropriate selection of the instruction types.

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Instruction format in the MSP430X CPU (2/2)

The MSP430X CPU supports all functions of the MSP430


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The MSP430X CPU supports all functions of the MSP430CPU;

It also offers a set of instructions that provide full accessto the 20-bit addressing space;

An additional op-code word is added to some of theinstructions. Therefore all addresses, indexes andimmediate numbers have 20 bits.

UBI

Extension word for register addressingmode (1/2)

In register mode the


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In register mode, theextension word of aninstruction of format type I(two operands) or format

type II (single operand) iscoded as:

The description of each field:

UBI

Extension word for register addressingmode (1/2)

Unlike the MSP430, the MSP430X CPU supports the


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Unlike the MSP430, the MSP430X CPU supports therepeated execution of the same instruction, providedthat the operands are of the register type;

The repetition is set by placing the repeat RPT instructionbefore the instruction to be executed;

The assembler incorporates information in the extensionword in the fields # (bit 7) and in the repetition counter(bits 3:0);

An example of this feature will be provided later.

UBI

Extension word for the other addressingmodes

In a non-register


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In a non registeraddressing mode, theextension word of aninstruction, whether

format I (doubleoperands) or format II(single operand), iscoded as:

The description of each

field:

UBI

Extended format I -Double operand-instructions

There are twelve extended instructions that use two


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There are twelve extended instructions that use twooperands:

UBI

Examples: Extended double operandinstructions (1/7)



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g g

MOVX R5,R4

Instruction code: 0x1840 0x4504


The instruction coding specifies that the CPU must performthe 16-bit data function MOVX, using the contents of the

source register R5 and the destination register R4.

0 0 0 1 1 0 0 ZC # A/L 0 0 n-1/Rn

0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0


0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0

MOVX R5 Register 16-bit Register R4

UBI


Move the contents of the register R5 to the memory


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g yaddress TONI:

MOVX R5,TONI

Instruction code: 0x184F 0x4580


0 0 0 1 1 src 19:16 A/L 0 0 dst 19:16

0 0 0 1 1 0 0 0 0 1 0 0 1 1 1 1

Op-code S-reg Ad B/W As D-reg0 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0

MOVX R5 Symbolic 16-bits Register PC

UBI


Move the contents of the register R5 to the memorydd TONI ( ti d)


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g yaddress TONI (continued):

MOVX R5,TONI

The instruction coding specifies that the CPU must performthe 16-bit data function MOVX, the source being the contentsof register R5 and the destination being the memory addresspointed to by (dst 19: 16: X1 + PC);

The bits dst 19: 16 is stored in the extension word and thevalue X1 is stored in the word following.

0 0 0 1 1 src 19:16 A/L 0 0 dst 19:16

0 0 0 1 1 0 0 0 0 1 0 0 1 1 1 1


0 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0

MOVX R5 Symbolic 16-bits Register PC

UBI


Move the contents of the memory address TONI to


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register R5:

MOVX TONI,R5

Instruction code: 0x1FC0 0x4015


0 0 0 1 1 src 19:16 A/L 0 0 dst 19:16

0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0


0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1

MOVX PC Register 16-bit Symbolic R5

UBI


Move the contents of the memory address TONI toregister R5 (contin ed)


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register R5 (continued):

MOVX TONI,R5

The coding specifies that the CPU must perform the 16-bitdata function MOVX, the source being the contents of memoryaddress pointed to by (sr c 19: 16: X1 + PC) and thedestination being register R5;

The bits dst 19: 16 are stored in the extension word and thevalue X1 is stored in the word following.

0 0 0 1 1 src 19:16 A/L 0 0 dst 19:16

0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0


0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1

MOVX PC Register 16-bit Symbolic R5

UBI


Move the contents of the memory address TONI to thedd EDEN


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memory address EDEN:

MOVX TONI,EDEN

Instruction code: 0x1FCF 0x4090


0 0 0 1 1 src 19:16 A/L 0 0 dst 19:16

0 0 0 1 1 1 1 1 1 1 0 0 1 1 1 1


MOVX PC Symbolic 16-Bit Symbolic PC

UBI


Move the contents of the memory address TONI to theaddress memory EDEN:


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address memory EDEN:

MOVX TONI,EDEN

The coding specifies that the CPU must perform the 16-bitdata function MOVX, the source being the contents of thememory address pointed to by (sr c 19: 16: X1 + PC) andthe destination being the contents of the memory address

pointed to by (dst 19: 16: X2 + PC); The bits sr c 19: 16 and dst 19: 16 are stored in the

extension word and the words X1 and X2 are stored in thewords following.

0 0 0 1 1 src 19:16 A/L 0 0 dst 19:16

0 0 0 1 1 1 1 1 1 1 0 0 1 1 1 1Op-code S-reg Ad B/W As D-reg

0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0

MOVX PC Symbolic 16-Bit Symbolic PC

UBI

Extended format II - single operand-instructions (1/2)

Extended instructions using format II are:


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UBI

Extended format II - single operand-instructions (2/2)

The MSP430X CPU has some additional capabilities inaddition to those of the MSP430 CPU:


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addition to those of the MSP430 CPU:

The ability to push/pop several registers on/off the data

stack using only a single instruction;

The ability to rotate the contents of a register several timesduring the execution of a single instruction.

UBI

Examples: Extended single operandinstructions (1/4)

Rotate right the 20-bit contents of register R5 with thecarry flag:


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carry flag:

RRCX.A R5

Instruction code: 0x1800 0x1045

This instruction uses 2 words; The coding specifies that the CPU must perform the function

RRCX using the 20-bit data contents of register R5.

0 0 0 1 1 0 0 ZC # A/L 0 0 n-1/Rn

0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0

Op-code B/W Ad D/S-reg0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 1

RRCX 20-bit Register R5

UBI


Rotate right the 20-bit contents of the memory addressTONI with carry flag:


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TONI with carry flag:

RRCX.A TONI



The coding specifies that the CPU must perform the functionRRCX using the 20-bit data contents of the memory addresspointed to by (dst 19: 16: X1 + PC);

0 0 0 1 1 src 19:16 A/L 0 0 dst 19:16

0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1


RRCX 20-bit Symbolic PC

UBI


Rotate right the 20-bit contents of the memory addressTONI with carry flag (continued):


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TONI with carry flag (continued):

RRCX.A TONI


The bits dst 19: 16 are stored in the extension word and thevalue X1 is stored in the word following;

0 0 0 1 1 src 19:16 A/L 0 0 dst 19:16

0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 1


RRCX 20-bit Symbolic PC

UBI


Rotate right the 20-bit contents of the memory addressTONI with carry flag (continued):


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TONI with carry flag (continued):

RRCX.A TONI

Because the instruction operand is located in memory ratherthan in a CPU register, two words are used to store theoperand. The format is shown in the figure below:

UBI

Exceptions to the representation of theextended Format II instructions (1/7)

Store the 20-bit registers R10, R9, R8:PUSHM.A #3,R10


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PUSHM.A #3,R10

The instructions PUSHMand POPMare coded according to the

structure given in the figure below:

Instruction code: 0x142A


The coding specifies that the CPU must perform the functionPUSHMof the 20-bit registers R10 to R8.

Op-code n - 1 D-reg

0 0 0 1 0 1 0 0 0 0 1 0 1 0 1 0

PUSHM.A #3 R10

UBI


Rotate right three times the contents of the 20-bit registerR5 with the carry flag:


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R5 with the carry flag:

RRCM.A #3,R5

The instructions RRCM, RRAM, RRUMand RLAMare coded

according to the structure given in the figure below:

UBI


Rotate right three times the content of the 20-bit registerR5 with the carry flag (continued):


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y g ( )

RRCM.A #3,R5



The coding specifies that the CPU must perform the functionRRCMusing the contents of the 20-bit register R5 a total of 3

times.

C n-1 Op-code R-reg

0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1

#3 RRCM R5

UBI


Perform a branch in the program flow:BRA R5


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BRA R5

This type of instruction can be coded in three differentformats, as shown in the figure below:

UBI


Perform a branch in the program flow (continued):BRA R5


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BRA R5

Instruction code: 0x05C0


The coding specifies that the PC must be loaded with thevalue in register R5.

C R-reg Op-code 0(PC)

0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0

R5 BRA PC

UBI


Call a routine:CALLA R5


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This type of instruction can be coded in three differentformats, as shown in the figure below:

UBI


Call a routine (continued):CALLA R5


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The coding specifies that the PC must be loaded with thevalue in register R5;

The execution of this instruction saves the PC on the datastack, so the function can return at the end of execution ofthe routine.

Op-code D-reg

0 0 0 1 0 0 1 1 0 1 0 0 0 1 0 1

CALLA R5

UBI

Extended emulated instructions

The constant generator provide a set of extendedemulated instructions, as shown in the following table:


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UBI

MSP430X address instructions

Address instructions support 20-bit operands, but theyhave restrictions on the addressing modes they can use;


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List of extended address instructions:

UBI

MSP430X CPU addressing modes

As with the MSP430 CPU, the MSP430X CPU supportsseven addressing modes for the source operand and fourdd i d f th d ti ti d


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addressing modes for the destination operand;

Both the MSP430 CPU and MSP430X CPU instructions canbe used throughout the 1 MB address space;

In the following sections we will explore the different

addressing modes available to the MSP430X CPU.

UBI

Register mode (1/3)

This addressing mode is identical to that of the MSP430CPU;


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There are three different types of access to the registers:

8-bit access (Byte operation);

16-bit access (Word operation);

20-bit access (Address-word).

The instruction SXT is the only exception, as the sign ofthe value is extended to the other bits of the register.


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UBI

Register mode (3/3)

Move the 20-bit contents of register R5 to register R4(continued):

MOVX A R5 R4


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MOVX. A R5, R4

After the execution of the instruction, the PC is incrementedby 4 and pointed to the next instruction;

The addressing mode used for the source and destinationoperands is specified by Ad = 0 (Register mode) and

As = 00 (Register mode).

UBI

Indexed mode

Indexed mode can be used in three different situations:


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Indexed mode in the memory address space below 64 kB;

Indexed mode in the memory address space above 64 kB;

Indexed mode using a MSP430X CPU instruction.

UBI

Indexed mode: below 64 kB (1/4)

Indexed mode in the memory address space below 64 kB:

If h CPU i R i dd l d


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If the CPU register Rn points to a memory address locatedbelow 64 kB, the address resulting from the sum of the index

and the register Rn has the value zero in bits 19:16.

This ensures that the address is always located in memorybelow 64 kB.

UBI


Move the word pointed to by (R5 0x30) to the wordpointed to by (R4 + 2):

MOV 0XFFD0( R5) , 2( R4)


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( ) , ( )



The instruction coding specifies that the word (B/ W = 0)pointed to by the sum of register R5 contents (S- r eg = 0101)and the word X1 should be moved to the memory addresspointed to by the sum of the register R4 contents(D- r eg = 0100) and the word X2;


0 1 0 0 0 1 0 1 1 0 0 1 0 1 0 0

MOV R5 Indexed 16-bit Indexed R4

UBI


Move the word pointed to by (R5 0x30) to the wordpointed to by (R4 + 2) (continued):

MOV 0XFFD0( R5) 2( R4)


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MOV 0XFFD0( R5) , 2( R4)

The words X1 and X2 are located in the memory addressesfollowing the instruction;

The addressing mode used for the source and destination

operands is specified by the bits Ad = 1 (Indexed mode) andAs = 01 (Indexed mode), because D- r eg = 0100 andS- r eg = 0101 respectively;

In this example, bits 19:16 are set to zero when the operandaddresses are calculated.

UBI


Move the word pointed to by (R5 0x30) to the wordpointed to by (R4 + 2) (continued):

MOV 0XFFD0( R5) 2( R4)


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MOV 0XFFD0( R5) , 2( R4)

UBI

Indexed mode: above 64 kB (1/2)

Indexed mode in the memory address space above 64 kB:

If the CPU register Rn points to a memory address above 64


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If the CPU register Rn points to a memory address above 64kB, bits 19:16 are used to calculate the operand of the

address;

A prerequisite is that the operand must be located in therange Rn 32KB, because the index is a signed 16-bit value;

Outside this range, the operand address can overflow orunderflow the memory address space below or above the64 kB.

If the registers now point to a memory address space above64 kB, bits 19:16 are used to determine the address in theoperands.

UBI

Indexed mode: above 64 kB (2/2)

Indexed mode in the memory address space above 64 kB(continued):


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UBI

Indexed mode: MSP430X CPU (1/4)

Indexed mode using a MSP430X CPU instruction:

When a MSP430X CPU instruction is used in indexed mode


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When a MSP430X CPU instruction is used in indexed mode,the operand can reside anywhere in the range of addresses

Rn 19 bits;

The operand address is calculated from the sum of the 20-bitcontents of the register Rn and the signed 20-bit index.

UBI

Indexed mode: MSP430X (2/4)

Move the word pointed to by (R5 0x30) to the wordpointed to by (R4 + 2):

MOVX 0xFFFD0( R5) , 2( R4)


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( ) ( )

Instruction code: 0x1FC0 0x4594


0 0 0 1 1 src 19:16 A/L 0 0 dst 19:16

0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0


MOVX R5 Indexed 16-bit Indexed R4

UBI

Indexed mode: MSP430X CPU (3/4)

Move the word pointed to by (R5 0x30) to the wordpointed to by (R4 + 2) (continued):MOVX 0xFFFD0( R5) , 2( R4)


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The instruction coding specifies that the word (B/ W = 0 andA/ L = 1) pointed to by the sum of register R5 contents(S- r eg = 0101) and the word X1 should be moved to thememory address pointed to by the sum of the register R4contents (D- r eg = 0100) and the word X2;

The four MSB indices are placed in the extension word of theinstruction and the other 16 bits are placed in the wordsfollowing the instruction;

The addressing mode used for the source and destinationoperands is specified by the bits Ad = 1 (Indexed mode) andAs = 01 (Indexed mode), because D- r eg = 0100 andS- r eg = 0101 respectively.


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UBI

Symbolic mode

The symbolic addressing mode uses the register PC todetermine the location of the operand based on an index;


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Similar to the previous addressing mode, there are threedifferent ways to use symbolic mode with the MSP30XCPU.

Symbolic mode in the memory address space below 64 kB;

Symbolic mode in the memory address space above 64 kB;

Symbolic mode using a MSP430X CPU instruction.

UBI

Symbolic mode: below 64 kB (1/3)

As in the indexed addressing mode, if the PC registerpoints to a memory address below 64 kB, the bits 19:16of the address calculated from the sum of the PC register

d th i d 16 bit i d t t


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and the signed 16-bit index are set to zero.

Move the contents of the address EDEN located at0x00200 to the address TONI located at 0x00202:

MOV EDEN, TONI



0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0

MOV PC Symbolic 16-bit Symbolic PC

UBI


Move the contents of the address EDEN located at0x00200 to the address TONI located at 0x00202 (cont.):MOV EDEN, TONI


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The instruction decoding specifies that the word (B/ W = 0)pointed to by the sum of the register PC contents(S- r eg = 0000) and the word X1 should be moved to thememory address pointed to by the sum of the register PC

contents (D- r eg = 0000) and the word X2; The words X1 and X2 are stored in the memory addresses

following the instruction;

The addressing mode used for the source and destinationoperands is specified by the bits Ad = 1 (Symbolic mode)

and As = 01 (Symbolic mode), because D- r eg = 0000 andS- r eg = 0000, respectively.

UBI


Move the contents of address the EDEN located at0x00200 to the address TONI located at 0x00202 (cont.):

MOV EDEN, TONI


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UBI

Symbolic mode: above 64 kB (1/4)

If the PC register points to a memory address above 64kB, bits 19:16 of the PC are used to calculate the operandaddress;


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The operand must be located in the memory rangePC 32 kB, because the index is a signed 16-bit value;

If outside this range, there may be an overflow or

underflow in the address space corresponding to memorybelow 64 kB.

UBI


Move the contents of the address EDEN located at0x10200 to register R5:

MOV EDEN, R5


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The instruction coding specifies that the word (B/ W = 0)

pointed to by the sum of the register PC contents(S- r eg = 0000) and the word X1 should be moved to theregister R5 (D- r eg = 0101);


0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1

MOV PC Register 16-bit Symbolic R5

UBI


Move the contents of the address EDEN located at0x10200 to register R5 (continued):

MOV EDEN, R5


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The word X1 is in the memory address following theinstruction;

The addressing mode used for the source and destination

operands is specified by the bits Ad = 0 (Register mode) andAs = 01 (Symbolic mode), because D- r eg = 0101 andS- r eg = 0000, respectively.

UBI


Move the contents of the address EDEN located at0x10200 to register R5 (continued):

MOV EDEN, R5


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