Abstract—Total Ionizing Dose (TID) testing performed on a RadHard-by-Design FET Driver on a 0.35μm triple-well process demonstrated radiation hardness to 300Krad(Si). Triple-well isolation provides superior performance, multiple and negative power supplies capabilities for robust mixed signal ASICs. Index Terms—Application specific integrated circuits, Mixed analog-digital integrated circuits, Radiation hardening, Space vehicle electronics I. INTRODUCTION AND EXECUTIVE SUMMARY Radiation Hardened by Design techniques (RHBD) provide the space market with access to commercial leading edge technologies for a variety of high performance integrated circuits requiring high speed, low power, high voltage, analog and mixed signal functions. This paper describes Total Ionizing Dose (TID) testing results of a RHBD, high voltage, fast slew rate, Power FET Driver circuit fabricated in a triple- well isolated process. The FET Driver circuit utilizes a commercial 0.35μm CMOS process using design rules in a completely non-invasive manner, i.e. no process alteration was required to achieve the total ionizing dose radiation hardness demonstrated to 300Krad(Si). II. BACKGROUND OF RADIATION HARDENED BY DESIGN Historically, the strategic space market has struggled to achieve the small size, weight, low power, or unique functions readily available to the commercial market due to the added requirement of radiation performance in various space environments. As previously published at NSREC, commercial foundry facilities have been utilized to produce Mary Hartwell, Semicustom Technology Development Manager, Aeroflex Colorado Springs, Inc.; phone: 719-594-8359, fax: 719-594-8468, email: [email protected]Kevin Ryan, Senior Design Engineer, Aeroflex Colorado Springs, Inc. phone: 719-594-8341, fax: 719-594-8010, email: [email protected]Steve Netherton, Fab Interface Engineer, Aeroflex Colorado Springs, Inc. phone: 719-594-8337, fax: 719-594-8329, email: [email protected]Peter Milliken, Director, Semicustom Products and Services, Aeroflex Colorado Springs, Inc. phone: 719-594-8382 fax: 719-594-8468, email: [email protected]David Kerwin, Director, Mixed Signal Products, Aeroflex Colorado Springs, Inc. phone: 719-594-8237 fax: 719-594-8468, email: [email protected]radiation hardened CMOS ASICs and standard products at the 0.6μm, 0.25μm and 0.18μm technology feature size without the need to develop or use any additional wafer processing steps. [1-4] III. ANALOG AND MIXED-SIGNAL FOR SPACE Commercial manufacturers limit their developmental participation in the space market because it represents a significantly lower percentage of their overall business. They produce their products using “best commercial practices” which tends to limit the testing, qualification and resulting reliability of these parts in comparison to high reliability, radiation hardened product manufacturers. The opportunity costs (resources necessary for core products) associated with additional design, manufacturing and screening to yield high reliability space products cannot be justified in most cases. The use of package shielding, which adds integration and weight costs, is one solution. Another solution in practice is independent “up-screening” by the space user community to ascertain the “usability” of particular COTS parts screened by design revisions and manufacturing lots for specific missions. It should be noted that commercial companies currently are the only source for high performance data conversion products. NASA and JPL, among others, have been testing and sharing their COTS radiation test results with the user community [5]. Their testing of these COTS devices, however, does not guarantee these parts’ availability, accessibility, or longevity to the space community. Finally, RHBD techniques facilitate the use of commercial wafer processes with proven radiation hardened circuit design and layout techniques, providing a “true” radiation hardened and guaranteed solution for the space market using commercial foundries. This is the technique used by Aeroflex Colorado Springs to develop a RadHard by Design, high voltage (10V), fast slew rate, very fast propagation delay, Power FET Driver circuit in a 0.35μm triple-well process. IV. COMPARISON OF HIGH VOLTAGE PROCESS TECHNOLOGY OPTIONS A. Conventional Transistor Structures Many mixed signal design applications require devices that operate at higher voltages than current digital ASIC devices (i.e. >3.3V or 5V). In this section, high voltage devices will Total Ionizing Dose Testing of a RadHard-by- Design FET Driver in a 0.35μm Triple-Well Process Mary Hartwell , Kevin Ryan, Steve Netherton, Peter Milliken and David Kerwin
Transcript
Abstract—Total Ionizing Dose (TID) testing performed on a
RadHard-by-Design FET Driver on a 0.35µm triple-well process demonstrated radiation hardness to 300Krad(Si). Triple-well isolation provides superior performance, multiple and negative power supplies capabilities for robust mixed signal ASICs.
Index Terms—Application specific integrated circuits, Mixed
analog-digital integrated circuits, Radiation hardening, Space vehicle electronics
I. INTRODUCTION AND EXECUTIVE SUMMARY Radiation Hardened by Design techniques (RHBD) provide
the space market with access to commercial leading edge technologies for a variety of high performance integrated circuits requiring high speed, low power, high voltage, analog and mixed signal functions. This paper describes Total Ionizing Dose (TID) testing results of a RHBD, high voltage, fast slew rate, Power FET Driver circuit fabricated in a triple-well isolated process. The FET Driver circuit utilizes a commercial 0.35µm CMOS process using design rules in a completely non-invasive manner, i.e. no process alteration was required to achieve the total ionizing dose radiation hardness demonstrated to 300Krad(Si).
II. BACKGROUND OF RADIATION HARDENED BY DESIGN Historically, the strategic space market has struggled to achieve the small size, weight, low power, or unique functions readily available to the commercial market due to the added requirement of radiation performance in various space environments. As previously published at NSREC, commercial foundry facilities have been utilized to produce
Mary Hartwell, Semicustom Technology Development Manager, Aeroflex Colorado Springs, Inc.; phone: 719-594-8359, fax: 719-594-8468, email: [email protected]
Kevin Ryan, Senior Design Engineer, Aeroflex Colorado Springs, Inc. phone: 719-594-8341, fax: 719-594-8010, email: [email protected]
Steve Netherton, Fab Interface Engineer, Aeroflex Colorado Springs, Inc. phone: 719-594-8337, fax: 719-594-8329, email: [email protected]
Peter Milliken, Director, Semicustom Products and Services, Aeroflex Colorado Springs, Inc. phone: 719-594-8382 fax: 719-594-8468, email: [email protected]
David Kerwin, Director, Mixed Signal Products, Aeroflex Colorado Springs, Inc. phone: 719-594-8237 fax: 719-594-8468, email: [email protected]
radiation hardened CMOS ASICs and standard products at the 0.6µm, 0.25µm and 0.18µm technology feature size without the need to develop or use any additional wafer processing steps. [1-4]
III. ANALOG AND MIXED-SIGNAL FOR SPACE Commercial manufacturers limit their developmental
participation in the space market because it represents a significantly lower percentage of their overall business. They produce their products using “best commercial practices” which tends to limit the testing, qualification and resulting reliability of these parts in comparison to high reliability, radiation hardened product manufacturers. The opportunity costs (resources necessary for core products) associated with additional design, manufacturing and screening to yield high reliability space products cannot be justified in most cases. The use of package shielding, which adds integration and weight costs, is one solution. Another solution in practice is independent “up-screening” by the space user community to ascertain the “usability” of particular COTS parts screened by design revisions and manufacturing lots for specific missions. It should be noted that commercial companies currently are the only source for high performance data conversion products. NASA and JPL, among others, have been testing and sharing their COTS radiation test results with the user community [5]. Their testing of these COTS devices, however, does not guarantee these parts’ availability, accessibility, or longevity to the space community. Finally, RHBD techniques facilitate the use of commercial wafer processes with proven radiation hardened circuit design and layout techniques, providing a “true” radiation hardened and guaranteed solution for the space market using commercial foundries. This is the technique used by Aeroflex Colorado Springs to develop a RadHard by Design, high voltage (10V), fast slew rate, very fast propagation delay, Power FET Driver circuit in a 0.35µm triple-well process.
IV. COMPARISON OF HIGH VOLTAGE PROCESS TECHNOLOGY OPTIONS
A. Conventional Transistor Structures Many mixed signal design applications require devices that operate at higher voltages than current digital ASIC devices (i.e. >3.3V or 5V). In this section, high voltage devices will
Total Ionizing Dose Testing of a RadHard-by-Design FET Driver in a 0.35µm Triple-Well
Process
Mary Hartwell, Kevin Ryan, Steve Netherton, Peter Milliken and David Kerwin
be described along with some concerns with respect to their radiation performance. Figs. 1, 2 and 3 illustrate the different transistor architectures for high voltage devices. Standard MOS (metal-oxide-semiconductor) transistor is shown in Fig. 1. High voltage for conventional self-aligned devices is supported by a thicker gate oxide, longer channel length and sometimes enhanced source-drain junctions. The thicker gate oxides pose a concern for Total Ionizing Dose (TID) because of the greater threshold voltage shifts (i.e.trapped holes) and sub-threshold swing degradation (i.e. surface states) after irradiation. Fig. 4 shows the relationship between maximum circuit voltage and gate oxide thickness. LDMOS (Laterally Diffused MOSFET) for high voltage applications is shown in Fig. 2. High voltage for LDMOS devices is supported by the lateral distance of Drain N+ to Pwell spacing. VDMOS (Vertically Diffused MOSFET) for high voltage applications is shown in Fig. 3. High voltage for VDMOS is supported by the diffused junction enclosure distance of the source areas. Due to the inherent size requirements of the LDMOS and VDMOS devices, the circuit area may become prohibitively large with their use. Also, there is a concern with LDMOS and VDMOS high surface leakage after TID irradiation making the hardening solution for these devices unknown at this time.
Fig. 1. Standard MOS Device Cross Section [6]
Fig. 2. LDMOS Device Cross Section [6]
Fig. 3. VDMOS Device Cross Section [7]
Fig. 4. Max Voltage vs. Gate Oxide Thickness
B. The Triple-Well Transistor Technology Advantage A triple-well process cross section is shown in Fig. 5. With
triple-well technology, the substrate supports independent Pwell and Nwell regions that can each be biased separately. Note the isolated p-well (ipw) within the deep Nwell region - defining the junction isolated Pwell or “triple-well” process. RHBD requires surface channel devices for layout techniques and increased size for TID, SEU, SEL, and DRU Hardness.
Fig. 5. Triple-Well Process Device Cross Section [8]
As gate oxide thickness increases, Vt shift with radiation exposure increases, thereby reducing total radiation dose tolerance
Key advantages to using triple-well isolation are its simultaneous use of multiple positive and negative power supplies with the die substrate grounded and its excellent substrate noise isolation characteristics. The variety of transistors offered in the 0.35µm process provides for both dynamic range and power conservation. The 3.3V transistors are the optimal choice for digital logic and portions of the mixed signal analog circuitry. The 5V transistors provide a broader dynamic range with the added benefit of the oxide being well within manageable limits for tolerating TID radiation, i.e. medium thick gate oxide is less susceptible to surface states and/or hole trapping. These self-aligned transistor processes also lend themselves well to hardened by design techniques. The 10V transistors provide a large dynamic range with total dose results presented later in this paper. The process also supports 13V and 18V transistors, which have not yet been evaluated. Through the triple-well process’ substrate noise isolation capability, Aeroflex has demonstrated better than -105dB cross-talk isolation at 1kHz between adjacent 20-bit sigma-delta analog-to-digital converters. Aeroflex’s Commercial Mixed Signal Products group has been designing high reliability medical and industrial ASIC’s with the MagnaChip’s 0.35µm Triple-well process for over five years.
V. RAD-HARD-BY-DESIGN FET DRIVER CIRCUIT IN MAGNACHIP 0.35µM TRIPLE-WELL ISOLATION
This paper summarizes the 0.35µm Triple-well isolated process Rad-Hard-by-Design FET Driver’s TID testing results. The radiation hardness reported in this paper is achieved solely through design hardening techniques. A test chip was fabricated at MagnaChip Semiconductor, a US company with wafer fabrication facilities in Cheongju, Republic of Korea on their 0.35µm CMOS wafer process. The 0.35µm process has been in production since 1998, and received DSCC QML-Q certification in 2005. Aeroflex has developed multiple non-radiation hardened mixed-signal designs using this process technology, including a Cryptographic Processor, a Computed Tomography X-Ray Detector, a Magnetic Stripe Reader and a Capacitive Sensor device. In addition, the MagnaChip 0.35µm Triple-well process supports options for higher voltages up to 18V. The higher voltage devices are achieved using a conventional transistor with thicker gate oxides and some enhanced design rules. See Fig. 4 for the relationship of gate oxide thickness and voltage. Hardened by design techniques can be used on this self-aligned high voltage transistor process and the expected transistor threshold voltage shifts can be mitigated through other design techniques. See Table I for a comparison of the performance of the Aeroflex FET Driver circuit with other Power FET Driver circuits. Aeroflex’s test chip design goals were chosen to evaluate MagnaChip’s 0.35µm process for the 10V transistor’s radiation environment response, measure the FET Driver’s AC performance, and assess the impact of simultaneous positive and negative power supplies. The advantage of this FET driver is its capability to drive a large capacitive load with positive and negative voltages with
fast rise and fall times and short propagation delays.
TABLE I FET DRIVER PERFORMANCE PARAMETERS
Parameter Aeroflex FET
Driver Industry
Comparison Industry
Comparison Rise Time 30nS 50nS 75nS Fall Time 30nS 50nS 75nS
Propagation Delay Time 29.22nS Not Specified 250nS
Capacitive Loading 3,125pF 1,000pF 4,300pF Voltage Swing 10V 10V-18V 12V-18V
VI. RADIATION HARDNESS TESTING RESULTS
A. Total Ionizing Dose (TID) Radiation Hardness Performance
1) AC Parameter Performance The 0.35µm technology TID radiation hardness was
accomplished through transistor layout with some area penalty (~25% area increase over best commercial practices), but with little transistor speed or power dissipation penalty. For the purpose of this evaluation, a FET driver circuit was designed that was comprised of both 3.3V and 10V transistors. The key design parameters used to evaluate this process were: rise and fall time, propagation delay and capacitive loading, . These same parameters were also used to evaluate total dose response. TID was performed using a cobalt-60 (60Co) gamma ray source. The test chips were tested at room temperature and maximum voltage, in accordance with Mil-Std-883 Method 1019.6, test condition A. TID hardness was demonstrated to 300Krad (Si). The results are summarized in Table II. Pre-rad and post-100Krad(Si) results are shown on Figs. 6, 7, 8, 9, 10 and 11. Note that the test was performed at -2V to +6V, 8V swing rather than 10V which the process supports, which resulted in slower performance.
TABLE II
AEROFLEX FET DRIVER TID RADIATION TEST RESULTS
Parameter Pre-Rad Post-
100Krad(Si) Post-
300rad(Si) Rise Time 30.0ns 32.1ns 58.6ns
Prop Delay low to high 29.2ns 29.9ns 66.0ns
Fall Time 30.0ns 28.7ns 29.2ns Prop Delay high
to low 22.9ns 13.9ns 17.2ns
Fig. 6 shows the pre-radiation rise time and propagation
delay. Fig. 7 shows the pre-radiation fall time and propagation delay.
Fig. 6. Pre-Rad Rise Time and Prop Delay
Fig. 7. Pre-Rad Fall Time and Prop Delay
Fig. 8 shows the post-100Krad(Si) radiation rise time and
propagation delay. Fig. 9 shows the post-100Krad(Si) radiation fall time and propagation delay.
Fig. 8. Post-100Krad (Si) Rise Time and Prop Delay
Fig. 9. Post-100Krad (Si) Fall Time and Prop Delay
Fig. 10 shows the post-300Krad(Si) radiation rise time and
propagation delay. Fig. 11 shows the post-300Krad(Si) radiation fall time and propagation delay.
Fig. 10. Post-300Krad (Si) Rad Rise Time and Prop Delay
Fig. 11. Post-300Krad (Si) Rad Fall Time and Prop Delay
2) DC Parameter Performance Data
The 0.35µm test chip contained n-channel enhancement mode MOSFET’s, in Standard (non-radiation hardened) and Rad-Hard-by-Design (RHBD) layouts; both with 75 Angstrom gate oxides. Both types of devices were tested for Leakage Current (Idoff), Linear Threshold Voltage (Vtlin), and Saturation Threshold Voltage (Vtsat) as a function of Total Ionizing Dose.
Fig. 12 shows Idoff for a standard n-channel transistor as a function of total dose for three device channel lengths - note the unacceptable leakage at 50Krad(Si) and at higher doses.
Fig. 12. Standard Transistor Idoff vs. Total Dose
Fig. 13 shows acceptable Idoff leakage for Aeroflex RHBD
transistors up to the highest tested dose of 300Krad(Si) for the same three gate lengths.
Fig. 13. RHBD Transistor Idoff vs. Total Dose
Fig. 14 shows Linear Threshold Voltage, Vtlin, for standard
transistors as a function of total dose for three channel lengths. The measurements of Vtlin are unreliable above 50Krad(Si), due to the excessive Idoff leakage.
Leakage (Idoff) vs. Total Ionizing Dose for Standard Transistor
transistors as a function of total dose for the same three device lengths. The largest Vtlin shift for the Aeroflex RHBD transistor was 6mV, which occurred at 300Krad(Si) for the shortest channel length (0.35µm).
Fig. 15. RHBD Transistor Vtlin vs. Total Dose
Fig. 16 shows Saturated Threshold Voltage, Vtsat, for
standard transistors as a function of total dose for three channel lengths – again, note the unacceptable Vtsat shifts greater than 50Krad(Si) (> 100mV shift).
Fig. 16. Standard Transistor Vtsat vs. Total Dose
Fig. 17 shows Vtsat for Aeroflex RHDB transistor as a
function of total dose for three channel lengths. The largest Vtsat shift for the Aeroflex RHBD transistor was 2mV at 300Krad(Si) for the shortest channel length device (0.35µm).
Fig. 17. RHBD Transistor Vtsat vs. Total Dose
Lastly, the subthreshold swing in mV/decade of the
Aeroflex RHBD n-channel transistor as a function of total dose is shown in Fig. 18. The data indicates very little change in subthreshold slope for the Id-Vg transfer curve of these transistors, indicating that very little surface state production occurs up to the highest total dose tested of 300Krad(Si).
Delta Vtlin vs. Total Dose for Standard Transistors
Fig. 18. RHBD Transistor Subthreshold Swing vs. Total Dose
B. Single Event Latchup and Single Event Gate Rupture The 0.35µm Test Chip and FET Driver Circuit were tested for Single Event Effects at Texas A&M University’s (TAMU) Cyclotron Institute using their K500 cyclotron. Both were immune to SEL to a linear energy transfer (LET) of 110 MeV-cm2/mg when tested at 125 °C and a maximum Vdd of 11V (considered worst-case conditions for SEL). These results indicate a Rad Hard by Design circuit layout in the triple-well process can be implemented that is immune to Single Event Latchup (SEL) and Single Event Gate Rupture (SEGR).
VII. SUMMARY A RadHard by Design FET Driver circuit, fabricated on a
0.35µm Triple-well CMOS process, was irradiated to 300Krad(Si) with acceptable deviation on the functional and AC propagation delay performance. A test chip was fabricated on the 0.35µm Triple-well CMOS process with excellent DC parametric performance after greater than 300Krad(Si). Triple-well isolation provides optimum signal integrity and allows for use of multiple and both positive and negative power supplies on the same chip; particularly important for analog and mixed signal circuits. The use of RadHard-by-Design techniques and Aeroflex’s QML backend screening, combined with a triple-well commercial foundry process, provides the space market with analog or mixed signal integrated circuit functions, high reliability and guaranteed radiation hardness assurance. [9]
REFERENCES [1] J. M. Benedetto, D. B. Kerwin, and J. Chaffee, “Radiation Hardening of
Commercial CMOS Processes Through Minimally Invasive Techniques”, IEEE Radiation Effects Data Workshop, in Snowmass, Colorado, July 21, 1997, pp. 105-109.
[2] D.B. Kerwin, J.M. Benedetto, “Radiation Hardening Of Submicron CMOS Wafers From Commercial Foundries”, GOMAC Digest of Papers, in Arlington, Virginia, March 16, 1998, pp. 109 – 112.
[3] D.B. Kerwin and J.M. Benedetto, “Total Dose And Single Event Effects Testing Of UTMC Commercial RadhardTM Gate Arrays”, IEEE Radiation Effects Data Workshop, in Newport Beach, California, July 24, 1998, pp. 80-85.
[4] J.M. Benedetto, D.B. Kerwin, “Total Dose Hardening Of Deep Sub-Micron Process for Mixed-Signal Applications”, GOMAC Digest of Papers, 2001, pp. 539-542.
[5] S. Agarwal, “Analog-to-Digital Converter parts Evaluation for Space Applications”, Jet Propulsion Laboratory, Office 507 Electronics Parts Engineering
[6] Copyright by Bart Van Zeghbroeck http://ece-www.colorado.edu/~bart/book/Copyright by Bart Van Zeghbroeck http://ece-www.colorado.edu/~bart/book/
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