R34DS0004EU0102 Rev.1.02 Page 1 of 23 Dec.11.19 ISL70061SEH, ISL73061SEH Radiation Hardened 10A PMOS Load Switch Datasheet The ISL70061SEH and ISL73061SEH (ISL7x061SEH) are radiation hardened single channel load switches featuring ultra-low r ON and controlled rise time. These devices use a PMOS pass device as the main switch that operates across an input voltage range of 3V to 5.5V and can support a maximum of 10A continuous current. Simple ON/OFF digital control inputs make the device capable of interfacing directly with low voltage control signals from an FPGA, MCU, or processor. Additional features include reverse current protection to stop current from flowing toward the input when the output SWO voltage increases above the input SWI voltage, a selectable 122Ω MOSFET to discharge the output, and Undervoltage Lockout (UVLO) protection that keeps the switch OFF when the input voltage is too low. The ISL7x061SEH devices operate across the military temperature range from -55°C to +125°C and are available in a 14 Ld hermetically sealed Ceramic Dual Flatpack (CDFP) package or in die form. Applications • Satellites power distribution management • Power system redundancy • Power sequencing • Power system fault management • Space VPX systems Features • Electrically screened to DLA SMD 5962-19208 • Integrated high speed load switch ○ Turn-off time of 3μs • Ultra-low ON-resistance (r ON ) of 14mΩ typical • Continuous 10A switch current • Controlled rise time to minimize inrush current • Reverse current protection • Simple ON/OFF logic control • Undervoltage lockout • Selectable 122Ω discharge MOSFET • Radiation acceptance testing - ISL70061SEH ○ HDR (50-300rad(Si)/s): 100krad(Si) ○ LDR (0.01rad(Si)/s): 75krad(Si) • Radiation acceptance testing - ISL73061SEH ○ LDR (0.01rad(Si)/s): 75krad(Si) • SEE hardness (see SEE report for details) ○ No SEB/SEL LET TH , SWI, SWO, ON, DON = 6.7V: 86MeV•cm 2 /mg Related Literature For a full list of related documents, visit our website: • ISL70061SEH and ISL73061SEH device pages Figure 1. Redundant Source Switch Application Figure 2. r ON vs Current vs Temperature ISL70003ASEH Load 1 ISL70061SEH ISL70061SEH ISL70003ASEH 0 5 10 15 20 25 1 2 3 4 5 6 7 8 9 10 r ON (mΩ) Switch Current (A) -55°C 25°C 125°C V SWI = 5.5V
The ISL70061SEH and ISL73061SEH (ISL7x061SEH) are radiation hardened single channel load switches featuring ultra-low rON and controlled rise time. These devices use a PMOS pass device as the main switch that operates across an input voltage range of 3V to 5.5V and can support a maximum of 10A continuous current. Simple ON/OFF digital control inputs make the device capable of interfacing directly with low voltage control signals from an FPGA, MCU, or processor.
Additional features include reverse current protection to stop current from flowing toward the input when the output SWO voltage increases above the input SWI voltage, a selectable 122Ω MOSFET to discharge the output, and Undervoltage Lockout (UVLO) protection that keeps the switch OFF when the input voltage is too low.
The ISL7x061SEH devices operate across the military temperature range from -55°C to +125°C and are available in a 14 Ld hermetically sealed Ceramic Dual Flatpack (CDFP) package or in die form.
Applications• Satellites power distribution management
• Power system redundancy
• Power sequencing
• Power system fault management
• Space VPX systems
Features• Electrically screened to DLA SMD 5962-19208
• Integrated high speed load switch
○ Turn-off time of 3µs
• Ultra-low ON-resistance (rON) of 14mΩ typical
• Continuous 10A switch current
• Controlled rise time to minimize inrush current
• Reverse current protection
• Simple ON/OFF logic control
• Undervoltage lockout
• Selectable 122Ω discharge MOSFET
• Radiation acceptance testing - ISL70061SEH
○ HDR (50-300rad(Si)/s): 100krad(Si)
○ LDR (0.01rad(Si)/s): 75krad(Si)
• Radiation acceptance testing - ISL73061SEH
○ LDR (0.01rad(Si)/s): 75krad(Si)
• SEE hardness (see SEE report for details)
○ No SEB/SEL LETTH, SWI, SWO, ON, DON = 6.7V: 86MeV•cm2/mg
Related LiteratureFor a full list of related documents, visit our website:
• ISL70061SEH and ISL73061SEH device pages
Figure 1. Redundant Source Switch Application Figure 2. rON vs Current vs Temperature
N/A ISL70061SEHX/SAMPLE (Notes 3, 4) N/A -55 to +125 Die N/A
N/A ISL73061SEHX/SAMPLE (Notes 3, 4) N/A -55 to +125 Die N/A
N/A ISL70061SEHEV1Z (Note 5) Evaluation Board
Notes:1. Specifications for Rad Hard QML devices are controlled by the Defense Logistics Agency Land and Maritime (DLA). The SMD numbers
listed must be used when ordering.
2. These Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
3. Die product tested at TA = + 25°C. The wafer probe test includes functional and parametric testing sufficient to make the die capable of meeting the electrical performance outlined in “Electrical Specifications” on page 7.
4. The /PROTO and /SAMPLE are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity. These parts are intended for engineering evaluation purposes only. The /PROTO parts meet the electrical limits and conditions across temperature specified in the DLA SMD and are in the same form and fit as the qualified device. The /SAMPLE parts are capable of meeting the electrical limits and conditions specified in the DLA SMD. The /SAMPLE parts do not receive 100% screening across temperature to the DLA SMD electrical limits. These part types do not come with a Certificate of Conformance because they are not DLA qualified devices.
5. Evaluation board uses the /PROTO parts and /PROTO parts are not rated or certified for Total Ionizing Dose (TID) or Single Event Effect (SEE) immunity.
Table 1. Key Features Between Family of Parts
DeviceChannel
TypeVCC Supply Bias Voltage
SWI Input Voltage Range rON tRISE
Selectable Output Discharge
MOSFETCurrent Rating
Reverse Current
Protection
ISL7x061SEH PMOS Not Required 3V to 5.5V 14mΩat VSWI = 5.5V
Human Body Model (Tested per MIL-STD-883 TM3015.7) 7 kV
Charged Device Model (Tested per JS-002-2014) 1 kV
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty.
CDFP Package K14.C with Solder (Notes 6, 7) 25 3.5
Notes:6. θJA is measured with the component mounted on a high-effective thermal conductivity test board (two buried 1 oz copper planes) using
“direct attach” features with package base mounted to PCB thermal land (with thermal vias below) with either a) Epoxy (10 mils thick with a “k” of 1W/m-K) or b) Solder (~2 mils thick). See TB379.
7. For θJC, the “case temp” location is the center of the package underside.
Parameter Minimum Maximum Unit
Maximum Junction Temperature - +150 °C
Storage Temperature Range -65 +150 °C
Parameter Minimum Maximum Unit
Temperature -55 +125 °C
SWI Input Voltage Range 3.0 5.5 V
ON, DON Logic Voltage Range 0 5.5 V
ISW 0 10 A
Typicals are at CSWI = 0.1µF and TA = +25°C; unless otherwise specified. Boldface limits apply across the operating temperature range, -55°C to +125°C; over a total ionizing dose of 100krad(Si) at +25°C with exposure at a high dose rate of 50 to 300rad(Si)/s (ISL70061SEH only); or over a total ionizing dose of 75krad(Si) at +25°C with exposure at a low dose rate of <10mrad(Si)/s.
Typicals are at CSWI = 0.1µF and TA = +25°C; unless otherwise specified. Boldface limits apply across the operating temperature range, -55°C to +125°C; over a total ionizing dose of 100krad(Si) at +25°C with exposure at a high dose rate of 50 to 300rad(Si)/s (ISL70061SEH only); or over a total ionizing dose of 75krad(Si) at +25°C with exposure at a low dose rate of <10mrad(Si)/s.
UVLOFalling VSWI = VON =3.0V, VDON = 0, RL = 25Ω to GND, Ramp VSWI / VON down simultaneously in -10mV steps until VSWO < 0.1V, Report this voltage as UVLOFALLING
-55 to +125 1.7 2.2 2.6 V
UVLO Rising Voltage
UVLORising VSWI = VON = 0.25V, VDON = 0, RL = 25Ω to GND, Ramp VSWI / VON up simultaneously in 10mV steps until VSWO > 1V, Report this voltage as UVLORISING
Typicals are at CSWI = 0.1µF and TA = +25°C; unless otherwise specified. Boldface limits apply across the operating temperature range, -55°C to +125°C; over a total ionizing dose of 100krad(Si) at +25°C with exposure at a high dose rate of 50 to 300rad(Si)/s (ISL70061SEH only); or over a total ionizing dose of 75krad(Si) at +25°C with exposure at a low dose rate of <10mrad(Si)/s.
tREV VSWI = 5.5V, VON = 5.5V, VDON = 0V; Start with VSWO = VSWI = 5.5V; Sweep VSWO from 5.5V to 5.6V with 5000V/s slew rate; Measure time from VRCP_ENTER to when IRCP has returned to 0A.(Note 12)
-55 to +125 - 4 8 µs
Post Radiation(+25)
- 4 12 µs
VSWI = 3.0V, VON = 3.0V, VDON = 0V; Start with VSWO = VSWI = 3.0V; Sweep VSWO from 3.0V to 3.1V with 5000V/s slew rate; Measure time from VRCP_ENTER to when IRCP has returned to 0A. (Note 12)
-55 to +125 - 5 10 µs
Post Radiation(+25)
- 5 14 µs
Notes:8. Typical values shown are not guaranteed.
9. Parameters with Min and/or Max limits are 100% tested at -55°C, +25°C, and +125°C, unless otherwise specified.
10. rON resistance of the die only, excludes packaging and bond wire resistance.
11. RCP and timing parameters are not tested during wafer die probe testing. Die limit specifications for these parameters are not available. Packaging and bond wire parasitic impedance do affect the specification performance of these parameters.
12. IRCP is the current referenced from SWO to SWI when VSWO > VSWI but VRCP_ENTER has not been met.
Figure 8. Control Timing Waveform Figure 9. SWO Timing Waveform
Figure 10. Timing Test Circuit
Typicals are at CSWI = 0.1µF and TA = +25°C; unless otherwise specified. Boldface limits apply across the operating temperature range, -55°C to +125°C; over a total ionizing dose of 100krad(Si) at +25°C with exposure at a high dose rate of 50 to 300rad(Si)/s (ISL70061SEH only); or over a total ionizing dose of 75krad(Si) at +25°C with exposure at a low dose rate of <10mrad(Si)/s.
ISL70061SEH, ISL73061SEH 4. Applications Information
R34DS0004EU0102 Rev.1.02 Page 15 of 23Dec.11.19
4. Applications Information
4.1 Functional DescriptionThe ISL7x061SEH are single channel, low voltage, high current load switches for use in space power switching applications. The integrated circuit is a PMOS pass device with a simple logic input to turn the pass device on or off.
The ISL7x061SEH devices are capable of 10A continuous current with a typical rON of 14mΩ with SWI = 5.5V and 16mΩ with SWI = 3.0V. The input voltage (VSWI) range of the devices is 3V to 5.5V and an internal UVLO keeps the devices in an OFF state when the VSWI is too low. To reduce voltage drops and minimize inrush current, the devices feature internal controlled on-time with a typical fixed rise time of 625µs at SWI = 5.5V. The ISL7x061SEH incorporate reverse current protection when the output voltage (VSWO) increases above the VSWI voltage. Additionally, there is a selectable 122Ω MOSFET between SWO and GND to discharge the output when the main pass device is OFF. When the DON logic input = High, the discharge FET circuitry is enabled.
4.2 rON of the Die vs Packaged PartBond wire resistance, package parasitic resistance, and package lead lengths are significant contributors to the switch rON resistance. The rON resistance of the die at 5.5V and 1A load is 7mΩ. At 5.5V and1A load the rON difference between a packaged part and the die is 6.8mΩ (13.8mΩ - 7mΩ). Based on this data, the package adds approximately 50% to the switch’s rON. Customers purchasing die and using their own packages must take into consideration the packaging resistance to ensure the rON meets their application requirements.
4.3 Undervoltage Lockout (UVLO)The devices have Undervoltage Lockout (UVLO) protection. The UVLO on the ISL7x0061SEH devices is based on the SWI voltage level. When there is not enough voltage to meet the UVLO threshold, the PMOS pass device is kept off. This occurs when the SWI voltage drops below UVLOFALLING threshold. When the ON pin is in the high state and the input voltage rises above the UVLORISING threshold, a controlled turn-on of the PMOS pass device is initiated.
4.4 ON Logic InputThe ON logic input controls the state of the PMOS pass device. The ON logic input is active high. When ON = High, the switch is ON and when ON = Low, the switch is OFF. The low logic levels make the ISL7x0061SEH ideal for interfacing with general purpose I/O voltages from CPU, FPGA, and microprocessors. The ON logic input has hysteresis to remove any switch bouncing or ON/OFF oscillations due to noise on the control signal. The pin has an internal 2MΩ pull-down resistor to ground and can be left floating.
4.5 DON Logic InputThe ISL7x061SEH devices have a selectable discharge MOSFET circuit at the SWO output that can be enabled when DON = High. It is disabled when DON = Low.
When DON = High and the PMOS pass device gets turned off (ON = Low), a 122Ω discharge MOSFET gets connected from the SWO output to ground. When the PMOS pass device is turned on (ON = High), the 122Ω discharge MOSFET gets disconnected. This functionality is for applications that need to quickly discharge the output when the PMOS pass device is turned off.
When DON = Low, the discharge MOSFET circuitry is disabled and does not get connected at the output when the PMOS pass device gets turned off. The DON pin has an internal 2MΩ pull-down resistor to ground and it can be left floating if this discharge function is not required.
The low logic levels of DON make it ideal for interfacing with general purpose I/O voltages from CPU, FPGA, and microprocessors. The DON logic input has hysteresis to remove any switch bouncing or ON/OFF oscillations due to noise on the control signal.
If DON = High and part is in the reverse current protection (RCP) state (VSWO ≥ VRCP_ENTER), the discharge FET circuitry becomes inactive and the 122Ω discharge MOSFET does not get connected at the output. When the RCP event is removed and the part resumes normal operation, the discharge circuitry is restored to normal operation.
ISL70061SEH, ISL73061SEH 4. Applications Information
R34DS0004EU0102 Rev.1.02 Page 16 of 23Dec.11.19
4.6 Controlled Rise TimeThe ISL7x061SEH devices have a fixed rise time (tRISE). With SWI at 5.5V, the typical tRISE is 625µs. This equates to a typical slew rate of 8.8V/ms. Figure 35 shows a scope plot of the tON/tRISE waveform of the load switch with SWI at 5.5V. The controlled rise time of the SWO voltage reduces the amount of inrush current when charging the load capacitance.
Use Equation 1 to calculate the inrush current.
where
• IINRUSH = inrush current (A)
• CL = load capacitance (F)
• SR = slew rate (V/s)
4.7 Reverse Current Protection (RCP)RCP circuitry is embedded to eliminate leakages from SWO to SWI in case of VSWO > VSWI. A comparator measures the dropout voltage on the switch between SWO and SWI and turns off the PMOS pass device if this voltage exceeds the VRCP_ENTER threshold. If the DON logic input = High or Low, the discharge MOSFET circuit is disabled in the reverse current state.
4.7.1 Reverse Current when PMOS Pass Device is DisabledThe load switch has been designed to have minimal reverse current when the PMOS pass device is turned OFF (disabled). The PMOS pass device is OFF under the following conditions:
• ON = Low
• VSWI < UVLOFALLING
• VSWO - VSWI > VRCP_ENTER
Figure 36 on page 17 shows the scope plot of SWO current as the SWO voltage is swept from 0V to 5.5V with VSWI = 3V and ON = DON = 0V. As you can see from the plot in the RCP voltage range of 3.04V to 5.5V, IRCP_LEAK is 5µA to 8µA.
ISL70061SEH, ISL73061SEH 4. Applications Information
R34DS0004EU0102 Rev.1.02 Page 17 of 23Dec.11.19
4.7.2 Reverse Current when PMOS Pass Device is EnabledFigure 37 (VSWI = 5.5V) and Figure 38 (VSWI = 3.3V) show the reverse current (IRCP) response when the PMOS pass device is ON (enabled) and the SWO voltage is increased above the SWI voltage (entering into RCP).
Note: The green, orange, and yellow traces in the graphs are the IRCP vs VSWO vs Temperature plots. The blue trace in the graphs show the voltage differential across the PMOS pass device (its Y axis scale is on the right side of the graphs).
As can be seen from the plots in the graphs, before VDIFF = VRCP_ENTER to turn the switch OFF, amps of current will flow from the SWO to SWI. At -58°C with VSWI = 5.5V, the current approaches 9A. This is expected because rON is lowest at cold temperature and VSWI = 5.5V. In addition, VRCP_ENTER is higher when VSWI = 5.5V. Looking at the graphs the VRCP_ENTER at VSWI = 5.5V is approximately 100mV.
IRCP can be calculated using Equation 2. IRCP is equal to the differential voltage across the switch (VDIFF) divided by the rON of the switch. VDIFF = VSWO - VSWI.
where
• IRCP = current referenced from SWO to SWI when VSWO > VSWI but VRCP_ENTER has not been met (A)
• VDIFF = differential voltage across the switch (V)
• rON = switch on resistance (Ω)
4.8 Turn-Off Inductive Voltage Transient When the PMOS pass device turns OFF during normal operation, inductive kickback generates a momentary voltage spike at the SWI input. A decoupling capacitor at the SWI pin can reduce the level of this voltage transient.
Figure 36. Leakage Current vs VSWO in the Disabled State
Figure 37. IRCP Enter vs VSWO vs Temperature Figure 38. IRCP Enter vs VSWO vs Temperature
ISL70061SEH, ISL73061SEH 4. Applications Information
R34DS0004EU0102 Rev.1.02 Page 18 of 23Dec.11.19
To prevent internal damage, the voltage transient must be less than the absolute maximum voltage rating of 6.5V. The transient can be limited to a safe level by designing the SWI board trace to have minimal loop inductance along with using the appropriate decoupling capacitance. Place the required decoupling capacitor/capacitors as close to the SWI pin as possible.
Use Equation 3 to calculate the decoupling capacitance required based on the trace loop inductance, load current, SWI supply voltage, and the maximum allowable SWI transient voltage spike.
where:
• C = decoupling capacitance on SWI to limit the maximum voltage spike (F)
• L = total loop inductance on the SWI side of the switch (H)
• I = load current (A)
• VSWI = SWI supply voltage (V)
• VSPIKE = maximum transient voltage spike on SWI (V)
Equation 3 example: System parameters: L = 0.14µH, VSWI = 5.5V, and I = 10A. To limit the VSPIKE to < 6.5V would require decoupling capacitance of >14µF. To limit the VSPIKE to 6V would require a decoupling capacitance of 56µF. If the system load current is I = 3A, it only requires a decoupling capacitance of 5µF to limit the VSPIKE to 6V.
Note: The previous discussion also applies to the SWO side of the PMOS pass device when turning OFF during a RCP event. This occurs during the transition when VSWO - VSWI > VRCP_ENTER. A transient voltage spike can be generated at the SWO and SWI pins.
4.9 Power Supply RecommendationsThe ISL7x0061SEH devices are designed to operate across an input voltage range of 3.0V to 5.5V. For proper electrical performance, the supply rail should be regulated and proper decoupling capacitors placed from the SWI trace to ground.
4.10 Layout
4.10.1 Layout GuidelinesFor best performance, make the SWI and SWO traces as short and wide as possible and place a solid ground power plane ≤5 mils under the traces to minimize the trace parasitic inductance. Place the decoupling capacitors as close as possible to the SWI and SWO pins to minimize the effects that the parasitic trace inductances may have on normal operation. See “Turn-Off Inductive Voltage Transient” on page 17. Due to the possibility of large power dissipation, connect the device thermal pad to the PCB through thermal vias to effectively remove heat from the part.
1.02 Dec.11.19 Updated the Features section on page 1 by changing the SEE hardness to No SEB/SEL LETH, SWI, SWO, ON, DON = 6.7V: 86MeV•cm2/mg.Updated absolute maximum rating for ISWPfrom 45A to 20A and changed pulse from ≤5µs to ≤1ms.Added Note 3.Updated test conditions for rDIS and tREV.
1.01 Oct.28.19 Updated the Ordering Information table on page 5 by changing the die temperature to read +25. Changed Table 1 on page 5 to “Key Features Between Family of Parts”. Updated the “RCP Enter Threshold Voltage” parameter by removing the Post Radiation (+25) row for VSWI = 5.5V.
6. Package Outline DrawingK14.C14 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE Rev 0, 9/12
SIDE VIEW
TOP VIEW
SECTION A-A
-D-
-C-
SEATING AND
BASE PLANE
-H-
BASEMETAL
PIN NO. 1ID AREA
0.022 (0.56)
0.015 (0.38)
0.050 (1.27 BSC)
0.005 (0.13)MIN
0.115 (2.92)
0.085 (2.16) 0.045 (1.14)
0.026 (0.66) 0.260 (6.60)
0.248 (6.30)
0.009 (0.23)
0.004 (0.10)
0.370 (9.40)
0.270 (6.86)
0.03 (0.76) MIN
0.006 (0.15)
0.004 (0.10)
0.009 (0.23)
0.004 (0.10)
0.019 (0.48)0.015 (0.38)
0.0015 (0.04)MAX
0.022 (0.56)
0.015 (0.38)
3
5
2
LEAD FINISH
1.adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark.
2. The maximum limits of lead dimensions (section A-A) shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied.
3.
4.shall be molded to the bottom of the package to cover the leads.
5.meniscus) of the lead from the body. Dimension minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder diplead finish is applied.
7.
8.
NOTES:
Dimensioning and tolerancing per ANSI Y14.5M - 1982.
Dimensions: INCH (mm). Controlling dimension: INCH.
Index area: A notch or a pin one identification mark shall be located
Measure dimension at all four corners.
For bottom-brazed lead packages, no organic or polymeric materials
Dimension shall be measured at the point of exit (beyond the
0.390 (9.91)
0.376 (9.55)
0.183 (4.65)
0.167 (4.24)
6
BOTTOM
METAL
6. The bottom of the package is a solderable metal surface.
BOTTOM VIEW
OPTIONAL
PIN 1 INDEX
BOTTOM METAL0.005 (0.127) REF.
OFFSET FROM CERAMIC EDGE
A
A
1
For the most recent package outline drawing, see K14.C.
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