Sp12 CMPEN 411 L12 S.1

CMPEN 411VLSI Digital Circuits

Spring 2012

Lecture 12: Logical Effort

[Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

Sp12 CMPEN 411 L12 S.2

PMOS/NMOS Ratio Effects

3

3.5

4

4.5

5

1 2 3 4 5

= (W/Lp)/(W/Ln)

x 10-11

= (W/Lp)/(W/Ln)

tpLH

tp

tpHL

of 2.4 (= 31 k/13 k)

gives symmetrical

response

of 1.6 to 1.9 gives

optimal performance

Sp12 CMPEN 411 L12 S.3

Example of Inverter Chain Sizing

CL/Cg,1 has to be evenly distributed over N = 3 inverters

F = CL/Cg,1 = 8/1

f =

In Out

CL = 8 Cg,1Cg,1

1

Sp12 CMPEN 411 L12 S.4

Heads up

This lecture

Logical Effort

- Reading assignment – textbook pp251-257, and handout

Next lecture

Designing energy efficient logic

- Reading assignment – Rabaey, et al, 5.5 & 6.2.1

Sp12 CMPEN 411 L12 S.5

First proposed by Ivan Sutherland and Bob Sproull in

1991

“Logical Effort: Designing for Speed on the back of an Envelope”, IEEE Advanced Research in VLSI, 1991

Both authors are vice president and fellow at Sun Microsystems

Gain-based synthesis based on Logical effort

Implemented in IBM’s logic synthesis tool BooleDozer

Also adopted by Magma’s logic synthesis tool

History

Sp12 CMPEN 411 L12 S.6

Inverter Delay

Divide capacitive load, CL, into

Cint : intrinsic - diffusion and Miller effect (Cg)

Cext : extrinsic - wiring and fanout

tp = 0.69 Req Cint (1 + Cext/Cint) = tp0 (1 + Cext/Cint)

=0.69(ReqCint + ReqCext)

where tp0 = 0.69 Req Cint is the intrinsic (unloaded) delay of the gate

Sp12 CMPEN 411 L12 S.7

Logical Effort Delay Model

Delay of logic gate has two components

d = f + p

f: effort delay

p: parasitic delay

Effort delay fg has two components:

f=gh g: logical effort

h: electrical effort = Cout/ Cin (the ratio of

output capacitance to input capacitance)

Sp12 CMPEN 411 L12 S.8

Gate Delay Components

Split delay of logic gate into three components

Delay = Logical Effort x Electrical Effort + Parasitic Delay

Logical Effort

Complexity of logic function (Invert, NAND, NOR, etc)

Define inverter has logical effort = 1

Depends only on topology not transistor sizing

Electrical Effort

Ratio of output capacitance to input capacitance Cout/Cin

Parasitic Delay

Intrinsic delay

Independent of transistor sizes and output load

Logic

Gate

Cin

Cout

Sp12 CMPEN 411 L12 S.9

Computing Logical Effort

Logical effort is the ratio of the input

capacitance of a gate to the input

capacitance of an inverter delivering

the same output current

Defined to be 1 for an inverter

g represents the fact that, for a given load, complex gates have to work harder than an inverter to produce a similar (speed) response

the logical effort of a gate tells how much worse it is at producing an output current than an inverter (how much more input capacitance a gate presents to deliver the same output current)

Sp12 CMPEN 411 L12 S.10

Computing Logical Effort

Sp12 CMPEN 411 L12 S.11

Logic Gate Delay

Sp12 CMPEN 411 L12 S.12

Logic Gate Delay

Sp12 CMPEN 411 L12 S.13

Example

Estimate the delay of an inverter driving 4 identical inverter: (FO4)

g= h= p= d=

Sp12 CMPEN 411 L12 S.14

Example

Sp12 CMPEN 411 L12 S.15

Path Delay of Complex Logic Gate Network

Total path delay through a combinational logic block

tp = dj = pj + hj gj

the minimum delay through the path determines that each stage should bear the same gate effort

h1g1 = h2g2 = . . . = hNgN

Sp12 CMPEN 411 L12 S.16

Application of Logical Effort

Alternative logic structures, which is the fastest?

F = ABCDEFGH

Sp12 CMPEN 411 L12 S.17

Application of Logical Effort

Alternative logic structures, which is the fastest?

F = ABCDEFGHg1=10/3 g2=1

g1=4/3 g2=5/3 g3=4/3 g4=1

g1=6/3 g2=5/3

Sp12 CMPEN 411 L12 S.18

Review: Design Technique 4

Isolating fan-in from fan-out using buffer insertion

CLCL

Sp12 CMPEN 411 L12 S.19

Questions

d = gh+p

How to derive the model from Elmore delay model?

Why logical effort g is independent of transistor sizing?

How to calculate parasitic delay p ? Why it is independent of

transistor sizing?

How to calculate single delay parameter:

What if the ratio of p-type to n-type transistor widths changes?

Sp12 CMPEN 411 L12 S.20

From Elmore model to Logical Effort Model

Cin

R

Cp Cout

Elmore Delay = R(Cp+Cout)

= R*Cout + R*Cp

= RCin*(Cout/Cin)+R*Cp

g h p

Sp12 CMPEN 411 L12 S.21

Parasitic Delay

Main cause is drain capacitances

These scale with transistor width so it is independent of transistor sizes

For inverter:

Parasitic Delay ~= 1.0 CdrainN

RonN

CgateN

CdrainPRonP

CgateP

Sp12 CMPEN 411 L12 S.22

How to calculate single delay parameter:

Characterize process speed with single delay parameter:

~= 15 ps for 0.18um ~=20 ps for 0.25 um

How to estimate it for a new process? (such as 0.13 or 0.09 um)

Sp12 CMPEN 411 L12 S.23

Inverter Chain Delay

For each stage:

Delay = Logical Effort x Electrical Effort + Parasitic Delay

= 1.0 (definition) x 1.0 (in = out) + 1.0 (drain caps)

= 2.0 units

Sp12 CMPEN 411 L12 S.24

Multistage Logic Network

Path logical effort, G = gi (gi = L.E. stage i)

Path electrical effort, H = Cout/Cin (hi = E.E. stage i)

Parasitic delay, P = pi (pi = P.D. stage i)

Path effort, F= fi = gi hi

D= F+P

Sp12 CMPEN 411 L12 S.25

Paths that Branch

Consider paths that branch:

G =

H =

GH =

h1 =

h2 =

F = GH?

5

15

1590

90

Sp12 CMPEN 411 L12 S.26

Paths that Branch

No! Consider paths that branch:

G = 1

H = 90 / 5 = 18

GH = 18

h1 = (15 +15) / 5 = 6

h2 = 90 / 15 = 6

F = g1g2h1h2 = 36 = 2GH

5

15

1590

90

Sp12 CMPEN 411 L12 S.27

Add Branching Effort

Branching effort:

pathon

pathoffpathon

C

CCb

Sp12 CMPEN 411 L12 S.28

Multistage Networks

Path electrical effort: H= Cout/Cin

Path logical effort: G = g1g2…gN

Branching effort: B = b1b2…bN

Path effort: F= GBH

Path delay D = F+P=GBH+P

Sp12 CMPEN 411 L12 S.29

Optimal Number of Stages

Minimum delay when:

stage effort = logical effort x electrical effort = 3.4-3.8 ~ 4

Fan-out-of-four (FO4) is convenient design size (~5)

Cin

Cout

FO4 delay: Delay of

inverter driving four

copies of itself

Sp12 CMPEN 411 L12 S.30

Method of Logical Effort

Compute the path effort: F = GBH

Find the best number of stages N ~ log4 F

Compute the stage effort f = F1/N

Sketch the path with this number of stages

Work either from either end, find sizes: Cin = Cout*g/f

Sp12 CMPEN 411 L12 S.31

Example of Inverter (Buffer) Staging

CL = 64 Cg,1Cg,1 = 1

1

CL = 64 Cg,1Cg,1 = 1

1 8

CL = 64 Cg,1Cg,1 = 1

1 4 16

CL = 64 Cg,1Cg,1 = 1

1 2.8 8 22.6

N f tp

1 64 65

2 8 18

3 4 15

4 2.8 15.3

Sp12 CMPEN 411 L12 S.32

Summary

Sp12 CMPEN 411 L12 S.33

Next Lecture and Reminders

Next lecture

Designing energy efficient logic

- Reading assignment – Rabaey, et al, 5.5 & 6.2.1