CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 07:...

Sp12 CMPEN 411 L07 S.1

CMPEN 411VLSI Digital Circuits

Spring 2012Lecture 07: Pass Transistor Logic

[Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]


Heads up

This lecture

Pass transistor logic

- Reading assignment – Rabaey, et al, 6.2.3

Next lecture

MOS transistor dynamic behavior

- Reading assignment – Rabaey, et al, 3.2.3 & 3.3.3-3.3.5

Wiring capacitance

- Reading assignment – Rabaey, et al, 4.1-4.3.1


Review: Static Complementary CMOS

VDD

F(In1,In2,…InN)

In1

In2

InN

In1

In2

InN

PUN

PDN

PUN and PDN are dual logic networks

High noise margins

VOH and VOL are at VDD and GND, respectively

Low output impedance, high input impedance

No static power consumption

Never a direct path between VDD and GND in steady state

Delay a function of load capacitance and transistor on resistance

Comparable rise and fall times (under the appropriate relative transistor sizing conditions)


Review: Static Complementary CMOS

VDD

F(In1,In2,…InN)

In1

In2

InN

In1

In2

InN

PUN

PDN

PUN and PDN are dual logic networks

Question:

Why PUN use only PMOS and PDN use only NMOS?

ANSWER:

NMOS transistors pass a

______ 0 but a _____ 1

PMOS transistors pass a

______ 1 but a ______ 0


NMOS Transistors in Series/Parallel

Primary inputs drive both gate and source/drain terminals

NMOS switch closes when the gate input is ______

Remember - NMOS transistors pass a ______ 0 but a ______1

A B

X YX = Y if ______

X Y

A

B X = Y if _______


PMOS Transistors in Series/Parallel

Primary inputs drive both gate and source/drain terminals

PMOS switch closes when the gate input is low

Remember - PMOS transistors pass a ______ 1 but a _____0

A B

X YX = Y if _______________

X Y

A

B X = Y if ____________


Pass Transistor (PT) Logic

A

B

FB

0

A

0

B

B= _____

F = _____

Gate is ______– a path exists to both supply rails under

all circumstances

____ transistors instead of 2N (for CMOS)

No static power consumption

Ratioless

Bidirectional (versus undirectional)


VTC of PT AND Gate

A

0

B

BF= AB

0.5/0.25

0.5/0.25

0.5/0.25

1.5/0.25

0

1

2

0 1 2

B=VDD, A=0VDD

A=VDD, B=0VDD

A=B=0VDDV

out,

V

Pure PT logic is not regenerative - the signal

gradually degrades after passing through a number

of PTs (can fix with static CMOS inverter insertion)


Differential PT Logic (DPL/CPL)

A

B

AB

PT NetworkF

A

B

AB

Inverse PT

Network F

F

F

F=AB

A

A

B F=AB

B

B B

AND/NAND

A

A

B F=A+B

BF=A+B

BB

OR/NOR

A

A F=AB

F=AB

BB

XOR/XNOR

A

A

Why NFET?

Sp12 CMPEN 411 L07 S.10

CPL Properties

Differential so complementary data inputs and outputs are always available (so don’t need extra inverters)

Still static, since the output defining nodes are always tied to VDD or GND through a low resistance path

Design is _________; all gates use the same topology, only the inputs are permuted.

Simple XOR makes it attractive for structures like ______

Fast (assuming number of transistors in series is small)

Additional routing overhead for complementary signals

Sp12 CMPEN 411 L07 S.11

CPL Full Adder

A

A

BB CinCin

!Sum

Sum

Cout

!CoutA

A

B

B

B

B Cin Cin

Cin

Cin

Sp12 CMPEN 411 L07 S.12

CPL Full Adder

A

A

BB CinCin

!Sum

Sum

Cout

!CoutA

A

B

B

B

B Cin Cin

Cin

Cin

Sp12 CMPEN 411 L07 S.13

NMOS Only PT Driving an Inverter

Vx does not pull up to VDD, but _________

In = VDD

A = VDD

Vx = ___

M1

M2

B

SD

Threshold voltage drop causes static power consumption (M2 may be weakly conducting forming a path from VDD to GND)

Notice VTn increases for pass transistor due to body effect (VSB)

VGS

Sp12 CMPEN 411 L07 S.14

Voltage Swing of PT Driving an Inverter

Body effect – large VSB at x - when pulling high (B is tied to GND and S charged up close to VDD)

So the voltage drop is even worse

Vx = VDD - (VTn0 + ((|2f| + Vx) - |2f|))

In = 0 VDD

VDD

xOut

0.5/0.25

0.5/0.25

1.5/0.25

0

1

2

3

0 0.5 1 1.5 2

Time, ns

Voltage, V

In

Out

x = 1.8VD

S

B

Sp12 CMPEN 411 L07 S.15

Cascaded NMOS Only PTs

B = VDD

Out

M1

yM2

Swing on y = VDD - VTn1 - VTn2

xM1

B = VDD

OutyM2

Swing on y = VDD - VTn1

C = VDD

A = VDD

C = VDD

A = VDD

Pass transistor gates should never be cascaded as on

the left

Logic on the right suffers from static power dissipation

and reduced noise margins

x = VDD - VTn1

G

S

G

S

Sp12 CMPEN 411 L07 S.16

Solution 1: Level Restorer

For correct operation Mr must be sized correctly (ratioed)

Level Restorer

M1

M2

A=0 Mn

Mr

x

B

Out =1

off

= 0A=1 Out=0

on

1

Full swing on x (due to Level Restorer) so no static power consumption by inverter

No static backward current path through Level Restorer and PT since Restorer is only active when A is high

Sp12 CMPEN 411 L07 S.17

Transient Level Restorer Circuit Response

0

1

2

3

0 100 200 300 400 500

Vo

lta

ge

, V

Time, ps

W/Lr=1.75/0.25

W/Lr=1.50/0.25

W/Lr=1.25/0.25W/Lr=1.0/0.25

W/Ln=0.50/0.25

W/L2=1.50/0.25

W/L1=0.50/0.25

node x never goes below VM

of inverter so output never

switches

Restorer has speed and power impacts: increases the capacitance at x, slowing down the gate; increases tr (but decreases tf)

Sp12 CMPEN 411 L07 S.18

Solution 2: Multiple VT Transistors

Technology solution: Use (near) zero VT devices for the NMOS PTs to eliminate most of the threshold drop (body effect still in force preventing full swing to VDD)

Impacts static power consumption due to subthreshold currents flowing through the PTs (even if VGS is below VT)

Out

In2 = 0V

In1 = 2.5V

A= 2.5V

B = 0V

low VT transistors

sneak path

on

off but

leaking

Sp12 CMPEN 411 L07 S.20

Solution 3: Transmission Gates (TGs)

Full swing bidirectional switch controlled by the gate signal C, A = B if C = 1, minimum size (ratioless)

A B

C

C

A B

C

C

B

C = VDD

C = GND

A = VDD B

C = VDD

C = GND

A = GND

Most widely used solution

Sp12 CMPEN 411 L07 S.21

TG Multiplexer

GND

VDD

In1 In2S S

S S

S

S

S

In2

In1

F

F

F = !(In1 S + In2 S)

Sp12 CMPEN 411 L07 S.22

Transmission Gate XOR

B

A A B

How many FETs for CMOS implementation? 10-12

Sp12 CMPEN 411 L07 S.23

Transmission Gate XOR

B

A A B

1

off

off

an inverter

B !A

0

on

on

A !B

Sp12 CMPEN 411 L07 S.24

TG Full Adder

Sum

Cout

A

B

Cin

How many transistors?

Sp12 CMPEN 411 L07 S.25

Differential TG Logic (DPL)

A

A

B

B

B

AND/NAND

F=AB

F=AB

XOR/XNOR

A

A

B

B

A

A

B

F=AB

F=AB

A

A

B

B A B A

GND

GND

VDD

VDD

B

Sp12 CMPEN 411 L07 S.26

6-transistor SRAM Storage Cell

!BL BL

WL

M1

M2

M3

M4

M5

M6Q

!Q

Will cover how the cell works in detail later

Sp12 CMPEN 411 L07 S.28

Next Lecture and Reminders

Next lecture

MOS transistor dynamic behavior

- Reading assignment – Rabaey, et al, 3.2.3 & 3.3.3-3.3.5

Wiring capacitance

- Reading assignment – Rabaey, et al, 4.1-4.3.1

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CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 07:...

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