DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference 2004 ITRS Public Conference PIDS...

DRAFT - NOT FOR PUBLICATION 14 July 2004 – ITRS Summer Conference

2004 ITRS Public ConferencePIDS ITWG

Emerging Research Devices

San Francisco, CAJuly 14, 2004

Jim Hutchby - SRC


2

George Bourianoff Intel/SRC Joe Brewer U. Florida Toshiro Hiramoto Tokyo U. Jim HutchbySRC Mike Forshaw UC London Tsu-Jae King UC Berkeley Rainer Waser RWTH A In Yoo Samsung John Carruthers OGI Lothar RischInfineon Ming-Jinn Tsai ERSO/ITRI Wei-Tsun Shiau UMC Peter Zeitzoff ISMT

Makoto Yoshimi SOITEC Kristin De Meyer IMEC Tak Ning IBM Philip Wong IBM Luan Tran Micron Victor Zhirnov SRC/NCSU Simon Deleonibus LETI Thomas Skotnicki ST Me Yuegang Zhang Intel Kentaro Shibahara Hiroshima U. Byong Gook Park Seoul N. U. Fred Boeuf ST Me Dan Hammerstrom OGI

ITRS PIDS Emerging Research Devices Working Group


3

Charles Black IBM John Carruthers OGI Alex Demkov Freescale Mike Forshaw UCL Gerhard Klimeck Purdue Mike GarnerIntel Bruno Ghysiene SOITEC Jeff Grossman LLNL David Muller Cornell Dan Herr SRC Susan Holl Intel

Jim HutchbySRC Lalita Manchanda SRC/Agere Rafael Reif MIT Sadasivan Shankar Intel Shinichi Takagi U. Tokyo Eric Vogle NIST Kang Wang UCLA Rainer Waser Aachen U. In Yoo Samsung Victor Zhirnov SRC/NCSU

ITRS PIDS Emerging Research Materials Working Group


4

Mike Forshaw UCL John Carruthers OGI George Bourianoff Intel/SRC Tobias Noll Aachen U.

Victor Zhirnov SRC/NCSU Dan Hammerstrom OGI Vwani Roychowdery UCLA

ITRS PIDS Emerging Research Architectures Working

Group


5

Emerging Research DevicesIntroduction and Scope

Cast a broad net to introduce readers to new material, device and architecture concepts for information processing ---

Concept

Identify

Include

Stimulate

-- not hardened solutions

-- not endorse

-- and quantify

-- and assess/critique

Prioritize -- and define research needs(new)


6

Requirements & Motivations for Information Processing Beyond CMOS

Fundamental Requirements Energy restorative functional process (e.g. gain) Compatible with CMOS At or above room temperature operation

Compelling Motivations Functionally scaleable > 100x beyond CMOS limit High information processing rate and throughput Minimum energy per functional operation Minimum, scaleable cost per function


7

Emerging Research DevicesIntroduction and Scope

2004/2005

Broadened Scope Compared to 2003 Chapter ---

New quantitative performance metrics

In-depth critical assessment --- key application driven questions/issues

--- potential versus to-date performance

Knowledge requirements roadmap --- requirements-driven research needs (new)


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Non-classical CMOS

Emerging Research DevicesOrganization & Component Tasks (2003)


ResearchLogic and Memory

Devices

Functional Organization

(Architectures)

Transfer to PIDS/FEP in

2005


9

Scope of Emerging Research Devices2003

back-gate

channel

isolation

buried oxide

channel

top-gate

Well doping

channelDepletion layer

isolation

halo

Bulk CMOS Double-Gate CMOS

Quantum cellular automataMolecular devices

Nanotubes

Emerging Information Processing Concepts

New Memory and LogicTechnologies

New ArchitectureTechnologies


10

Device Transport-enhanced Devices

Ultra-thin Body Source/Drain Engineered Devices

Concept Strained Si, Ge, SiGe, SiCGe or still other semiconductor; on bulk or SOI

Fully depleted SOI with body thinner than 10 nm

Ultra-thin channel and localized ultra-thin BOX

Schottky source/drain

Non-overlapped SD extensions on bulk, SOI, or DG devices

Application/Driver

HP CMOS

HP, LOP, and LSTP CMOS


HP CMOS


Strained Si, Ge, SiGe

isolation

buried oxide

Silicon Substrate

BOX

Bulk wafer BOX (<20nm)

S D Ground Plane

FD Si film

Gate

Schottky barrierisolation

Silicon

silicideGate

nFET

pFET

Bias

Non-overlapped region

S D

Single Gate Non-classical CMOS

Transfer to PIDS/FEP in 2005


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Device Multiple Gate FET

N-Gate (N>2) FET

Double-gate FET

Concept Tied gates (number of channels >2)

Tied gates, side-wall conduction

Tied gates planar conduction

Independently switched gates, planar conduction

Vertical conduction

Application/Driver HP, LOP, and LSTP CMOS



LOP and LSTP CMOS


Source Drain

Gate

Source Drain

Gate

Source Drain

Gate

STI

n+

Si-substrate

SOURCE

GATE

DRAIN

n+

STI

n+

Si-substrate

SOURCE

GATE

DRAIN

n+

Multiple Gate Non-classical CMOS

Transfer to PIDS/FEP in 2005


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Present Day Baseline Technologies

Phase Change Memory*

Floating Body DRAM

Nano-floating Gate

Memory**

Single/Few Electron Memories*

*

Insulator Resistance Change Memory**

Molecular Memories**

Storage Mechanism

Device Types

DRAM NOR Flash

OUM 1TDRAM eDRAM

Engineered tunnel barrier or nanocrystal

SET MIM oxides

Bi-stable switch Molecular NEMS

Availability 2004 2004 ~2006 ~2006 ~2006 >2007 ~2010 >2010

Cell Elements

1T1C 1T 1T1R 1T 1T 1T 1T1R 1T1R

Emerging Research Memory Devices


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Memory Device Technologies

Performance [A]

Architecture compatible

[B]*

Stability and reliability

[C]

CMOS compatible

[D]**

Operate temp

[E]***

Energy efficiency

[F]

Sensitivity parameter)

[G]

Scalability [H]

Floating Body DRAM

2.3/2.3 3.0/3.0 2.0/2.7 3.0/3.0 3.0/3.0 2.0/3.0 2.3/2.9 2.8/2.7

Phase Change Memory

2.6/2.9 2.2/3.0 2.3/2.2 2.2/3.0 3.0/3.0 1.8/2.7 2.1/2.1 2.7/2.2

Nano-floating Gate Memory

3.0/2.2 2.9/3.0 2.0/2.7 3.0/3.0 3.0/3.0 2.1/2.8 1.6/2.0 2.4/2.0

Insulator Resistance Change Memory

2.4/2.1 2.7/2.7 2.2/2.4 2.1/2.8 3.0/2.9 2.8/2.0 2.1/2.0 2.7/2.4

Molecular Memory

1.6/1.2 1.8/2.0 1.8/1.4 1.9/2.1 2.8/2.3 2.3/1.9 2.1/1.7 2.6/2.2

Single/Few Electron Memory

1.1/1.3 1.9/1.3 1.1/1.0 2.4/1.9 1.3/1.3 2.4/1.2 1.3/1.0 2.6/1.4

Technology Performance and Risk EvaluationEmerging Research Memory Devices


14

Emerging Research Memory Devices

Present Day Baseline Technologies

Phase Change Memory*

Floating Body DRAM

Nano-floating Gate

Memory**

Single/Few Electron Memories*

*

Insulator Resistance Change Memory**

Molecular Memories**

Storage Mechanism

Device Types

DRAM NOR Flash

OUM 1TDRAM eDRAM

Engineered tunnel barrier or nanocrystal

SET MIM oxides

Bi-stable switch Molecular NEMS

Availability 2004 2004 ~2006 ~2006 ~2006 >2007 ~2010 >2010

Cell Elements

1T1C 1T 1T1R 1T 1T 1T 1T1R 1T1R

Move to PIDS/FEP in

2005


15

Emerging Research Logic Devices

Device

FET RSFQ3-5 1D structures

Resonant Tunneling Devices

SET6 Molecular QCA7 Spin transistor


16

Scaling Limit of Charge Based SwitchAn Example of Critical Assessment

Observations

Transistor critical dimension limited to ~ 1 nm (In the 2003 ITRS physical gate length = 7 nm for 2018)

Power density, not critical dimension, limits gate density to ~ 1 x 109 gates/cm2

For the ITRS density and switching time, CMOS is approaching the maximum power efficiency


17

Logic Device Technologies

Performance [A]

Architecture compatible

[B]*

Stability and

reliability [C]

CMOS compatible

[D]**

Operate temp

[E]***

Energy efficiency

[F]

Sensitivity parameter)

[G]

Scalability [H]

1D Structures 2.3/2.2 2.2/2.9 1.9/1.2 2.3/2.4 2.9/2.9 2.6/2.1 2.6/2.1 2.3/1.6

RSFQ Devices

2.7/3.0 1.9/2.7 2.2/2.8 1.6/2.2 1.1/2.7 1.6/2.3 1.9/2.8 1.0/2.1

Resonant Tunneling Devices

2.6/2.0 2.1/2.2 2.0/1.4 2.3/2.2 2.2/2.4 2.4/2.1 1.4/1.4 2.0/2.0

Molecular Devices

1.7/1.3 1.8/1.4 1.6/1.4 2.0/1.6 2.3/2.4 2.6/1.3 2.0/1.4 2.6/1.3

Spin Transistor

2.2/1.7 1.7/1.6 1.7/1.7 1.9/1.4 1.6/2.0 2.3/2.1 1.4/1.7 2.0/1.4

SETs 1.1/1.2 1.7/1.2 1.3/1.1 2.1/1.4 1.2/1.8 2.6/2.0 1.0/1.0 2.1/1.7

QCA Devices 1.4/1.3 1.2/1.1 1.7/1.8 1.4/1.6 1.2/1.4 2.4/1.7 1.6/1.1 2.0/1.4

Technology Performance and Risk EvaluationEmerging Research Logic Devices


18

Emerging Research DevicesOrganization & Component Tasks (2004/2005)


EmergingLogic and Memory

Devices

EmergingArchitectures

EmergingMaterials

Add to ERD in 2004


19

Scope of Emerging Research Devices2005

Quantum cellular automataMolecular devices

Nanotubes

Emerging Information Processing Concepts

New Memory and LogicTechnologies

New ArchitectureTechnologies

New Materials

Model Knowledge


20

Emerging Research DevicesSummary

ERD transferring new potential solutions to PIDS/FEP

Non-Classical CMOS

Phase Change and Floating Body DRAM

Creating a new section on Emerging Research Materials

Enhancing technology evaluation and guiding activities

Quantitative critique of emerging technologies

New roadmap of scientific and technology information required to advance emerging information processing technologies

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