EECE488: Analog CMOS Integrated Circuit Design Set 7...

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1SMEECE488 Set 7 - Opamp Design

EECE488: Analog CMOS Integrated Circuit Design

Set 7

Opamp DesignReferences: “Analog Integrated Circuit Design” by D. Johns and K. Martin

and “Design of Analog CMOS Integrated Circuits” by B . Razavi

All figures in this set of slides are taken from the above books

Shahriar MirabbasiDepartment of Electrical and Computer Engineering

University of British [email protected]


General Considerations

• Gain

• Small-signal bandwidth

• Large-signal performance

• Output swing

• Input common-mode range

• Linearity

• Noise/offset

• Supply rejection

2


One-Stage Op Amps


One-Stage Op Amp in Unity Gain Configuration

3


Cascode Op Amps


Unity Gain One Stage Cascode

4


Folded Cascode Op Amps


Folded Cascode Stages

5


Folded Cascode (cont.)


Folded Cascode (cont.)

| Av |≈ gm1{[( gm3 + gmb3)ro3(ro1 ||ro5)] ||[( gm7 + gmb 7)ro7ro9 ]}

6


Telescopic versus Folded Cascode


Example Folded-Cascode Op Amp

7


Single-Ended Output Cascode Op Amps


Triple Cascode

Av app. (gmro)3/2

Limited Output Swing

Complex biasing

8


Output Impedance Enhancement

1221 oomout rrgAR =


Gain Boosting in Cascode Stage

9


Differential Gain Boosting



10




Two-Stage Op Amps

11


Single-Ended Output Two-Stage Op Amp


Two-Stage CMOS Opamp

• Popular opamp design approach

• A good example to review many important design concepts

• Output buffer is typically used to drive resistive loads

• For capacitive loads (typical case in CMOS) buffer is notrequired.

A1 –A2 1

Differentialinput stage

Secondgain stage

Outputbuffer

VoutVin

Cc

12


Two-Stage CMOS Opamp Example


Gain of the Opamp

• First Stage

Differential to single-ended

• Second Stage

Common-source stage

• Output buffer is not required when driving capacitive loads

13


Gain of the Opamp

Third Stage

• Source follower

• Typical gain: between 0.7 to1

• Note: go=1/ro and GL=1/RL

• gmb is body-effect conductance (is zero if source can be tied tosubstrate)


Frequency Response

Q5

Q3 Q4

Q2Q1

300

300300

150

150

vin–

vin+

Vbias

–A2 A3 vout

CCv1

i = gm1 vin

v2

Ceq CC 1 A2+( )=

A3 1≅

14


Frequency Response

Simplifying assumptions:

• CC dominates

• Ignore Q16 for the time being (it is used for lead compensation)

Miller effect results in

• At midband frequencies


Frequency Response

• Overall gain (assuming A3 ≈1)

which results in a unity-gain frequency of

• Note: ωta is directly proportional to gm1 and inverselyproportional to CC.

15


Frequency Response

• First-order model

20 A1A2( )log

Gain

(dB)

0 Freq

ωta

ωta gm1 CC⁄≅

20– dB/decade

Phase

(degrees)

0 Freqωta

180–

90–

ωp1

ωp1

(log)

(log)


Slew Rate

• Maximum rate of output change when input signal is large.

• All the bias current of Q5 goes either into Q1 or Q2.

Q5

Q3 Q4

Q2Q1

300

300300

150

150

vin–

vin+

Vbias

–A2 A3 vout

CCv1

i = gm1 vin

v2

A3 1≅

16


Slew Rate


Slew Rate

• Normally, the designer has not much control over ωta

• Slew-rate can be increased by increasing Veff1

• This is one of the reasons for using p-channel input stage:higher slew-rate

17


Systematic Offset Voltage

• To ensure inherent (systematic) offset voltage does not exist,nominal current through Q7 should equal to that of Q6 when thedifferential input is zero.

Q5

Q3 Q4

Q2Q1

Q6

Q7

VDD300

300300

150 150

300

300

Vin– Vin+

Vout

VSS

Ibias

Vbias


Systematic Offset Voltage

• Avoid systematic offset by choosing:

• Found by noting

and

then setting

18


N-Channel versus P-Channel Input Stage

• Complimentary opamp can be designed with an n-channel inputdifferential pair and p-channel second-stage

• Overall gain would be roughly the same in both designsP-channel Advantages• Higher slew-rate: for fixed bias current, Veff is larger (assuming

similar widths used for maximum gain)• Higher frequency of operation: higher transconductance of

second stage which results in higher unity-gain frequency• Lower 1/f noise: holes less likely to be trapped; p-channel

transistors have lower 1/f noise• N-channel source follower is preferable (less voltage drop and

higher gm)N-channel Advantage• Lower thermal noise — thermal noise is lowered by high

transconductance of first stage


Feedback and Opamp Compensation

)(1

)()(

sH

sHs

X

Y

β+=

• Feedback systems may oscillate

• The following two are the oscillation conditions:

180)(

1|)(|

−=∠=

ωβωβ

jH

jH

19


Stable and Unstable Systems


Time-domain response of a feedback system

20


One-pole system

Bode plot of the Loop gain

0

0

1)(

ωs

AsH

+=

( )00

0

0

11

1)(

A

sA

A

sX

Y

βω

β

++

+=

( )00 1 AS p βω +−=


Multi-pole system

Bode plot of the Loop gain

12 101.0 pp ωω >

21


Phase Margin

20 LG jω( )( )log

Loop Gain

(dB)

0ωt

-20 dB/decade

Phase

(degrees)

0Freq

ωt

180–

90–

ωp1

ωp1

(log)Loop Gain

PM

Freq(log)

GM(gain margin)

(phase margin)


Phase Margin

Closed loop frequency response

175

1 1 je)(H −×=ωβ

β5.11

)( =sX

Y

22


Phase Margin (Cont.)

Phase Margin = 45°

)(HPM GXωβ∠+=180



Phase Margin = 45°

23



• At PM = 60o results in a small overshoot in the step response.• If we increase PM, the system will be more stable but the time

response slows down.


Frequency Compensation

• Push phase crossing point out

• Push gain crossing point in

24


Telescopic Opamp (single-ended) -example


Compensation (Cont.)

• Assume we need a phase margin of 45 o (usually inadequate) and other non-dominant poles are at hig h frequency.

25


Compensation of a two-stage opamp

Miller Effect Ceq = CE + (1+ Av2)CC

f pE = 1

2πRout [CE + (1+ Av 2)CC ]


Compensating Two-Stage Opamps

Q5

Q3 Q4

Q2Q1

Q6

Q7

VDD300

300300

150 150

300

300

Vin-Vin+ Vout2

Vbias1

CcQ16

Vbias2

26



• Q16 has VDS16 = 0 therefore it is hard in the triode region.

• Small signal analysis: without RC, a right-half plane zero occursand worsens the phase-margin.

gm1vin

gm7v1

v1

R1 C1

RC CC

R2 C2



• Using RC (through Q16) places zero at

• Zero moved to left-half plane to aid compensation

• Good practical choice is

• satisfied by letting

27


Design Procedure

Design example: Find CC with RC=0 for a 55o phase margin

– Arbitrarily choose C’C=1pF and set RC=0

– Using SPICE, find frequency ωt where a –125° phase shiftexists, define gain as A’

– Choose new CC so ωt becomes unity-gain frequency of theloop gain, resulting in a 55o phase margin.

Achieved by setting CC=CCA’

– Might need to iterate on CC a couple of times using SPICE


Design Procedure

Next: Choose RC according to

– Increasing ωt by about 20 percent, leaves zero near final ωt

– Check that gain continues to decrease at frequencies above thenew ωt

Next: If phase margin is not adequate, increase CC while leavingRC constant.

28


Design Procedure

Next: Replace RC by a transistor

SPICE can be used for iteration to fine-tune the devicedimensions and optimize the phase margin.


Process and Temperature Independence

• Can show non-dominant pole is roughly given by

• Recall zero given by

• If RC tracks inverse of gm7 then zero will track ωp2:

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• Need to ensure Veff16/Veff7 is independent of process andtemperature variations

• First set Veff13=Veff7 which makes Va=Vb

Q11

Q12

Q13

Q6

CC

25

25

25

300

300

Q16Va

Vb

Vbias

Q7

Vb



30


Stable Transconductance Biasing


Stable Transconductance Biasing

• Transconductance of Q13 (to the first order) is determined bygeometric ratios only.

• Independent of power-supply voltages, process parameters,temperature, etc.

• For special case (W/L)15=4(W/L)13

gm13=1/RB

• Note that high-temperature will decrease mobility and henceincrease effective gate-source voltages.

• Roughly 25% increase for 100 degree increase

• Requires a start-up circuit (might have all 0 currents)

Date post:	10-Jun-2018
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EECE488: Analog CMOS Integrated Circuit Design Set 7...

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