1

High dynamic performance of BLDC motor with 1

front end converter using FPGA based controller 2

for electric vehicle application 3

Praveen YADAV1, Rajesh POOLA

2, Khaja NAJUMUDEEN

3 4

1,2Department of Electrical Engineering, Motilal Nehru National Institute of 5

Technology, Allahabad, India. 6

3Faculty at Department of Electrical and Electronics Engineering, Dhanalakshimi 7

Srinivasan College of Engineering, Coimbatore, India. 8

E-mail:praveeny84@gmail.com,ecarajesh@gmail.com, 9

kaja.najumudeen06@gmail.com 10

11

Abstract: 12

This paper focus on a novel operation of Brushless dc (BLDC) motor fed by 13

Proportional Integral (PI) controlled buck-boost converter supplemented with battery to 14

provide required power to drive BLDC motor. The operational characteristics of proposed 15

BLDC motor drive system for constant as well as step changes in dc link voltage of front 16

end converter, controlled by Xilinx System Generator (XSG) based PI controller, for two 17

quadrant operations are derived. Thus Field Programmable Gate Array (FPGA) based PI 18

2

controller manages the energy flow through battery and the front end converter. Moreover, 1

speed to voltage conversion logic, made to control BLDC motor through PI controller, 2

improves the performance and gives optimum control under the unstable driving situation 3

or varying load condition when complete system becomes a subject of application to 4

Electric Vehicles (EV’s) and Hybrid Electric Vehicles (HEV’s). The dual closed loop 5

control implemented, for end to end speed control of proposed drive system, facilitates the 6

system with high accuracy integrated with excellent dynamic and steady state performance. 7

In this paper, the proposed controller has been designed for 5 kW/480 V BLDC motor 8

drive system. The feasibility of the proposed dual loop control topology for BLDC motor 9

drive system is validated and verified with extensive dynamic simulation in 10

MATLAB/SIMULINK and XSG environment. 11

Keywords: BLDC motor drive, EV’s, FPGA, front end converter, HEV’s, PI controller, 12

Xilinx system generator (XSG). 13

Nomenclature:14

Vdc = output voltage of buck boost

converter

Vin = dc input voltage to buck boost

converter

D = duty cycle

fs = switching frequency

R = load resistance

ΔiLo = range of variation of inductor

current

ΔVco = range of variation of dc link

voltage

ia, ib, ic = a, b and c phase currents

3

Ls = inductance of the stator windings

Vab, Vbc = ab and bc phase to phase

voltage

Rs = resistance of the stator windings

ψ = amplitude of the flux induced by the

permanent magnets of the rotor in the

stator phase

P = number of pole pairs

ωr = angular velocity of rotor

Ea, Eb, Ec = a, b and c phase

electromotive forces

Te = electromagnetic torque

Vn = maximum voltage from buck boost

converter

k = kth

sample

1. Introduction

Since last two decades the issues like sustainable development and environmental 1

pollution due to vehicular emission are accelerating the modern science and technology 2

and have given thrust to the research on Electric Vehicles (EV’s) and Hybrid Electric 3

Vehicle (HEV’s). Brushless DC motor drives have been found more suitable for EV’s, 4

HEV’s and other low power applications [1, 2, 3]. BLDC motor has many advantages over 5

the conventional induction and DC motors; such as better speed and torque characteristics, 6

high efficiency and reliability, low electromagnetic interference (EMI), high power to 7

weight and torque to current ratio, long operation life etc. [4,5]. Compared to induction 8

machine BLDC motor have lower inertia, allowing for faster dynamic response to 9

reference commands. Moreover the advancement in the power electronic devices and 10

DSP/FPGA based processors have added more features to these motor drives to make them 11

more prevalent in industrial installation [6-8]. Hysteresis current control and pulse 12

4

width modulation (PWM) control coupled with continuous control theory produced 1

the most widely used BLDC motor control techniques. The control of BLDC motor in 2

medium as well as high speed applications is much easier as compared to induction 3

motors. Hysteresis current control is essential in achieving adequate control of 4

instantaneous torque and hence yielding faster speed response. Digital PWM control 5

technique implemented for speed control of BLDC motor have maximum speed error 6

below 5% [9-10]. So this control technique is not suited for application which 7

requires high precision. Conduction angle control and current mode control of BLDC 8

motor also have significant error in speed control, though less than digital PWM 9

control [11]. Conventional BLDC motors with six switch inverter, excited through bipolar 10

based soft switching currents, are suitable for low/medium power and medium speed 11

applications as well. In order to use these motors effectively at their optimal efficiency and 12

in safe operating zone they must be driven at their nominal power requirement [12]. Power 13

electronic converters provide the featured solution to meet the demand of the regulated 14

electrical power for efficient and dynamic operation of BLDC motor drives. Most of the 15

controllers designed for speed control of BLDC motors consider the unidirectional power 16

flow converter as it facilitates the easy control and reduced cost of the drives [13]. 17

Moreover the use of the battery to feed to front end converter of BLDC motor drive, not 18

only removes the lack of specific power, but also enables an excellent performance of the 19

drive system in both acceleration and regenerative braking in EV’s applications [14].The 20

converter also adjusts the dc input voltage to the front end converter of BLDC motor 21

verses the motor speed in order to reduce the ripple of the motor current waveform [15]. 22

5

This fact is of a particular importance in case of slotless axial-flux PMDC motor drives, 1

which have been proposed recently for medium-speed and high torque motor drive 2

applications such as the direct driving of EV’s wheel [16]. Conventional proportional 3

integral (PI) control technology is not meeting the requirement of very fast dynamic 4

response of the EV’s under rapid changes in operating modes of the drive system. The 5

evolution of high speed and high density FPGA based processor is now providing the best 6

alternative to the ASIC and microprocessor based implementation of complex control 7

algorithm. The improved and appreciable dynamic and steady state performance of BLDC 8

motors supplemented with FPGA based controller will make them suitable for position 9

control in machine tools, robotics and high precision servos, aerospace, 10

healthcare/biomedical equipments, speed control and torque control in various industrial 11

drives and process control applications. 12

In this paper, a novel FPGA based dual speed control technique has been proposed 13

targeting very precise speed control applications. The complete paper is structured as 14

follows. The overall work is briefly introduced in the section 2. Section 3 deals with the 15

mathematical modeling of buck boost converter, induction profile of BLDC motor and 16

front end converter. Proposed dual loop speed control, designed to meet transient and 17

steady state constraint with an objective of excellent speed control of BLDC motor drive 18

system, is discussed in details in section 4. Section 5 deals with simulation analysis of 19

proposed control strategy in MATLAB/SIMULINK and Xilinx system generator 20

environment and performance evaluation of the entire drive system under steady state and 21

6

dynamic conditions. Finally conclusions are made with discussion of the results and merits 1

of the proposed control scheme in section 6. 2

2. Structure of the proposed controlled dc-dc converter fed BLDC motor drive 3

Figure 1 shows front end converter fed BLDC motor drives with dual control loop 4

designed on FPGA processor to control the variable dc link voltage and hence to achieve 5

the desired speed control. The battery used to feed the buck-boost converter circuit, acts as 6

source and sink during acceleration and regeneration mode of EV’s respectively. The 7

validation of the proposed model for EV’s application governs the choice of buck-boost 8

converter for this application. Additionally, the selection of buck-boost converter reduces 9

the switching losses of VSI operated at low frequency for electronic commutation of 10

BLDC motor drive [17]. The discrete rotor position, sensed through hall sensor, is fed back 11

to FPGA processor- 12

(i) wherein, speed to voltage conversion is carried out. Voltage error 13

equivalence, Ve(k),of speed error, Ne(k) is given to PI controller which 14

generates the control signal, D for the operation of buck-boost converter. 15

(ii) to generate switching signal Mi at a frequency, f for the operation of front 16

end converter. 17

3. Mathematical modeling 18

3.1. Buck-boost converter 19

The equation (1) governs the relation between input (Vin) and output voltage (Vdc) 20

during continuous conduction mode of buck boost converter [18]. 21

7

*

1

indc

V DV

D

(1) 1

The value of the inductance L0 is given by (2) 2

0

0

1 * in

L s

D VL

i f

(2) 3

The value of the capacitance 0C is given by (3) 4

0

0

0

cs

DC

VRf

V

(3) 5

6

7

3.2. The Induction profile of BLDC motor drive system 8

The motor under investigation is a Permanent Magnet Synchronous Machine (PMSM) 9

with the permanent magnet mounted on the rotor and concentrated stator windings 10

resulting in trapezoidal induced back EMF’s with maximum possible width of flat top 11

portion [19]. To ensure the smooth torque production a constant current is forced through 12

each phase winding during the interval when the back EMF is at its maxima as shown in 13

Figure 2. For the unipolar excitation with soft switching current, positive current flows 14

through the phase windings for positive back EMF’s with each conduction period lasting 15

for 120˚. However, no current flows through phase windings when back EMF’s vary with 16

8

time. This results in two phases conducting at a time and producing the torque. So for 1

trapezoidal variation of induced back EMF’s and with an assumption that phase 2

inductances are constant, the equation governing the above described induction profile of 3

BLDC motor in abc reference frame [20] are given by 4

1

2 3 ( 2 )3

aab bc s a r a b c

s

diV V R i p E E E

dt L (4) 5

1

3 ( 2 )bab bc s b r a b c

q

diV V R i p E E E

dt L (5) 6

c a bdi di di

dt dt dt

(6) 7

a a b b c ce

E i E i E iT

(7) 8

3.3. Front end converter 9

Figure 3 shows three phase front end converter for speed control of BLDC motor 10

drive system through electronic commutation. Each leg has two IGBT switches, 11

accompanied by anti parallel flywheel diodes, which are complement in their switching 12

action. For understanding the underlying principles involved in working of this front end 13

converter circuit, phase A is taken under consideration. 14

From Figure 3, the voltage VaN across phase A with respect to neutral point (N) of dc link 15

capacitor [21] is expressed by Eq. (8) 16

4 1 1 1 1cos cos3 cos5 cos7 cos9 ...

2 3 5 7 9

dcaN o o o o o

VV t t t t t

(8) 17

9

The voltage VnN, between neutral of stator winding and neutral point (N) of dc link 1

capacitor, is given by (9) 2

4 1 1cos3 cos9 ....

2 3 9

dcnN o o

VV t t

(9) 3

So, the voltage Van that appears across phase A with respect to winding’s neutral n, is 4

given by (10) 5

an aN nNV V V (10) 6

4 1 1cos cos5 cos7 ....

2 5 7

dcaN o o o

VV t t t

(11) 7

It can be inferred from equation (11) that the most dominant 3rd

order harmonics is 8

eliminated. 9

4. Proposed dual loop speed control 10

When precise speed control becomes the prime concern, then multiple pathways 11

become an essential ingredient to achieve the stated objective. Here in the proposed BLDC 12

drive system the speed is being controlled 13

1. by controlling the input voltage to the front end converter with the help of proposed 14

PI controller and 15

2. by triggering the switching pulse of front end converter proportional to EMF 16

detection 17

10

The design of efficient controllers is needed for the optimal operation of power converters 1

to improve the close loop dynamic and steady state performance of BLDC drive system. 2

Conventional way of implementing digital controller based on FPGA and developing 3

control algorithm using high level language like Verilog Hardware Description Language 4

(VHDL) is a cumbersome and tedious job. Newly evolved FPGA based Xilinx System 5

Generator provides a very realistic solution for the aforesaid problem. Automatic code 6

generation, dedicated hardware intellectual properties of the Xilinx block sets for FPGA 7

core and simulation of real time physical system in safer environmental zone makes it 8

appropriate platform for our research. So designing the controller based on FPGA (Xilinx 9

system generator, a type of real time digital simulator) ensures a very rapid prototyping to 10

our proposed methodology [22]. 11

The subject of application of proposed BLDC drive system to EV’s and HEV’s, 12

where predominantly step changes in speed occur, governs the selection of PI controller for 13

excellent dynamic response of the system with zero steady state error. Here discrete time 14

FPGA based PI controller is controlling the DC link voltage to the front end converter and 15

thus speed of the BLDC drive system. So the dynamics of the entire drive system is 16

completely governed by controller. 17

4.1. Modelling of XSG based digital PI controller 18

In Figure 4, if Nr(k), Nr*(k) and Ne(k) denote the actual rotor speed, reference speed 19

and speed error respectively, input to the speed to voltage converter is given by (12)

20

( ) *( ) ( )e r rN k N k N k (12) 21

11

And voltage error Ve(k), equivalent to speed error is given by (13) 1

( ) * ( )ne e

VV k N k

N

(13) 2

The output, switching command U (k), of PI controller at kth

instant is expressed as 3

1 ( ) ( 1) ( ) ( 1) *k k p e e i e eU U K V k V k K V k V k k (14) 4

Where PI controller constant KP = 0.6 and KI= 5 and ∆k is sampling interval. 5

Control signals D, for the operation of buck-boost converter, are generated by comparison 6

of U (k) with 20 kHz triangular wave. 7

4.2. Delay control of switching sequences in front end converter 8

The second way to control the speed of motor is to vary the triggering rate of switches. 9

The speed of the motor can be changed here by manipulating the time interval between 10

switching of different phases. To control speed via this method, the circuitry required is 11

shown in Figure 5. 12

To achieve variable rate of switching between the different phases switching pulses are 13

generated in synchronism with discrete rotor position sensed by the hall sensor. As shown 14

in Figure 6, the hall sensor will detect discrete rotor position after every 60 degree rotation 15

and will produce pulses which are converted into equivalent back EMF signals by decoder. 16

Firing circuit with back EMF signal produces the switching pulses, shown in Table 1, for 17

the front end converter. 18

12

So, the change in speed is accompanied by electronic commutation where the 1

inductance energy of any one phase reaches the maximum value during each 30 electrical 2

degree, inductance holds this energy for next 120 electrical degrees and which finally is 3

released in next 30 electrical degrees through anti parallel fly wheel diode. This 4

commutation process for phase A is shown in Figure 7. 5

5. Description of simulation setup and performance evaluation of the proposed 6

control scheme. 7

To validate the proposed methodology, extensive dynamic simulations are carried out in 8

1. MATLAB/SIMULINK environment using power system toolbox for power 9

circuitry in floating point representation. 10

2. XSG environment using Xilinx block set tools for control circuit in fixed point 11

representation. 12

The overall block diagram with closed loop control using proposed FPGA based PI 13

controller is shown in Figure 8 which outlined the communication between FPGA 14

based PI controller and rest of electric drive system. The control circuit consists of 15

three parts 16

1. Speed to voltage conversion 17

2. PI controller and saturation. 18

3. Delay control of switching in front end converter 19

And the power circuit consists of 20

1. Buck Boost converter 21

13

2. VSI fed BLDC drive system 1

Reference speed is digitally set and actual rotor speed is sensed and speed to voltage 2

conversion logic loop, shown in Figure 8, is used to convert speed error into voltage 3

equivalence error which is further utilized by proposed PI controller to generate gate 4

signal for discrete IGBT switch used in buck boost converter. IGBT switch is rated 5

for 60 A, 700V and 20 kHz frequency. In this way voltage is drawn from power 6

converter for the desired speed response of BLDC drive system. Simulation results 7

and performance of proposed system are discussed in later section. 8

The detailed data of power circuit considered for simulation are given in Table 2.The 9

performance of the BLDC motor drive system categorized into steady state and 10

dynamic performance. The performance indices: 11

Primary-(a) Percentage average speed error (b) Maximum speed ripples (c) 12

Percentage maximum speed error and 13

Secondary-(a) Stator back EMF’s E(V) (b) Stator current I(A) (c) Electromagnetic 14

torque Te(N-m) (d) DC link voltage Vdc(V) from buck boost converter, are selected to 15

study the effectiveness of proposed control scheme. 16

5.1. Steady state analysis 17

This analysis is aimed to determine if the actual motor speed reaches commanded 18

speed at steady state. Based on the speed error and its voltage equivalence correct 19

proposed controller execute the steps required to decide the duty cycle required for 20

IGBT switch of buck boost converter in next cycle. 21

14

5.1(a). Speed ripple and percentage speed error calculation 1

The average speed error and maximum speed error are the function of speed ripples. 2

It is therefore essential to find out the speed ripples at steady state for both, the 3

dynamic and steady state performance evaluation. 4

%Average Speed Error = Average speed ripple

Average speed*100 5

%Maximum Speed Error = Maximum speed ripple

Reference speed*100 6

The results, shown in Figure 9 (a)-(c), illustrate that the ability of proposed 7

controller in tracking the commanded speed is reasonably good under different sets 8

of operating condition. Results, in reference to Figure 9(a)-(c) and Table 3, are 9

summarized as below- 10

1. It is very clear that average speed lies very close to commanded speed and 11

maximum speed ripple is well below 6 rpm. 12

2. The percentage average speed error and percentage maximum speed error are 13

always less than 1%. 14

3. It is also notable that average error and maximum error are decreasing 15

reasonably fast with increase in commanded speed. 16

4. For lower speed range (900-1100 rpm), ripples are almost constant, during 17

steady state, in their magnitude. Due to this reason average error and 18

15

maximum error are almost equal to each other which can be seen from Table 1

3. 2

From Table 3 a chart have been shown in Figure 10, in order to give a clear 3

insight about the effectiveness of the proposed control scheme. Chart is drawn for 4

1. Percentage average error Vs average speed and 5

2. Percentage Maximum speed error Vs reference speed 6

From chart it can clearly be seen that average as well as maximum speed error 7

keep on decreasing with increase in reference speed. 8

Further the steady state performance of proposed control scheme for BLDC 9

drive, against constant load of 3 N-m, at two different commanded speed, are also 10

shown in Figure 11 -12. 11

It can be seen form Figures 11(a) and 12(a) that controller is sufficiently fast in 12

tracking reference speed in approximately 0.25 sec. The enlarged view of back EMF’s 13

and phase current are shown in Figures 11(b)-(c) and 12(b)-(c), which are constant 14

for preset load of 3 N-m. Since the load is assumed to be constant as shown in Figures 15

11(d) and 12(d), the phase current is also constant. The dc link voltage follows the 16

changes made in commanded speed as can be observed from Figures 11(e) and 12(e). 17

5.2. Dynamic performance 18

In order to test the dynamic performance of the proposed control scheme, the 19

desired response of BLDC drive system is investigated under sudden change in 20

16

reference speed, issued at t = 1.5 sec. The response of the system is shown in Figure 13 1

(a) and an enlarged view of speed response, after step change in commanded speed, is 2

shown in Figure 13 (b). 3

The results depicted in Figure 13 (b) show that the actual speed attains steady 4

state value very close to commanded speed, in less than 40 ms, after a step change in 5

reference or commanded speed (3000 to 1500 rpm) is enforced. 6

The enlarged view of actual speed spectrum is also shown in Figure 13 (c)-(d) to 7

assess the average and maximum speed ripple at steady state under issued change in 8

commanded speed. The effectiveness and efficiency of the proposed control scheme in 9

terms of chosen performance indices such as average and maximum speed error, 10

maximum speed ripple has been presented in Table 3. It can clearly be observed from 11

Figure 13 (c)-(d) and Table 3 that maximum speed ripple stays well within 5 rpm and 12

percentage average error and percentage maximum error stays less than or equal to 13

0.23 and 0.26 respectively. Thus the simulation results validate the utility and 14

effectiveness of the proposed control scheme in terms of precise tracking of reference 15

speed. Furthermore, the time taken by the controller to track the commanded speed, 16

after the system has been subjected to a step change in speed, is less than 40 ms, 17

which is appreciably fast response of controller. 18

Moreover, for a step change in commanded speed issued at t = 1.5 s and t = 1.6 s, 19

the dynamic behavior of the proposed BLDC drive system is investigated against 20

secondary performance indices which are shown in Figure 14 (i) (a). It can be 21

17

observed from Figure 14 (i) (c) that, under the issued changes, the electromagnetic 1

torque regains its steady state value with acceptable values of overshoot in less than 2

0.5 s after the commanded speed has been changed. As the load torque has been 3

assumed to be constant this makes stator phase current also constant, which can be 4

easily seen from Figure 14 (i) (b). It can also be seen from Figure 14 (i) (d) that the dc 5

link voltage exactly follows the corresponding changes made in commanded speed. 6

Any change in reference speed is followed by actual speed and the corresponding 7

change in stator phase back EMF’ is shown in Figure 14 (ii).8

6. Conclusions

The Dual loop control scheme, based on FPGA, for speed control of BLDC

motor, targeting precise speed control and medium power application such as EV’s

and HEV’s, has been presented in this paper. The proposed control scheme has

following advantages

1. Simulation results discussed so far illustrate the effectiveness of control

scheme in tracking the commanded speed in a very less time and quiet less

speed ripple as well.

2. The main attractive feature of the proposed work is the easy and quick

realization in real time applications when this control logic is implemented

on XSG platform.

3. The Proposed FPGA based PI controller is sufficiently fast in its action of

generating the desired DC link voltage, from buck boost converter, and

hence the desired speed control.

18

4. Moreover the average speed error and maximum speed error are

evaluated in order to determine certain more application of proposed

system. So the observed dynamic performance of BLDC drive system has

demonstrated the ability of proposed control scheme to be selectively used

for application which requires very high speed accuracy along with fast

dynamic response such as biomedical /health care equipments, printing

technology, aerospace applications.

This controller provides far superior performance when proposed drive system is

used for high speed application over the classical zero crossing sensorless approach which

is applicable only in low speed applications. Indeed, the availability of discrete rotor

position through Hall Effect sensor and disturbance torque information greatly improves

the efficiency and robustness of the system, while decreasing the acoustic noise. This

paper, thus, illustrate feasibility of an accurate speed controller along with the estimator

portion of the controller. The implementation of dual control loop to control speed either

via changing DC link voltage with PI controller or by changing the time interval for

conduction state of phases facilitates end to end speed control. Hence the proposed model

realized the speed controller for a brushless DC Motor, which is demanded increasingly,

using the FPGA based control scheme. Finally the performance of the system is evaluated

in MATLAB/SIMULINK software integrated with Xilinx System Generator.

19

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22

List of Figures

BATTERY

BUCK-BOOST

CONVERTERFRONT END

CONVERTER

FPGA PROCESSOR

BLDC MOTOR

D Mi, f

Ea

Nr

Figure 1. Block diagram of the proposed drive system

30 90 150 210 270 330

180 360

Torque

Phase A

Phase B

Phase C

Stator Phase Back EMF’s

Phase Current

Output Torque

UNIPOLAR Excitation

Ma

gn

itu

de

Rotor angle(deg)

Figure 2. Induction profile of BLDC drive system showing Back-EMF’s, Phase

current and output torque waveform with unipolar excitation

23

Ra

Eb

EcN n

T1 T3

T2 T4 T6

T5

C1

C2

La

RcLc

RbLb

Ea

DC

in

pu

t

vo

lta

ge

PMSM

Figure 3. Circuit topology of a voltage control three phase inverter

speed

sensor,

Nr(k)

Speed to

voltage

conversion

PI

controller

Ve(k)

FPGA PROCESSOR

U(k) PWM

generator

Ref.

Speed,

Nr*(k)+

-Ne(k)

Control

signal

(D)

Figure 4. Block diagram of proposed speed control algorithm.

Hall

sensorDecoder

Firing

circuit

Equivalent

EMF’ s

signal

FPGA PROCESSOR

Control

signal

(mi,f)

Figure 5. Switching signal generator for VSI.

24

100 60

2060 120

30120 180

40180 240

50240 300

60300 360

0

0

1

Ha

Hb

Hc

1

1

0Ha

H bH

c

1

0

1

HaH

bHc

1

0

0

Ha

Hb

Hc

0

1

1Ha

H bH

c

0

1

0

HaH

bHc

0

NA

8

NA

1

1

1

HaH

bHc

0

0

0

Ha

Hb

Hc

Figure 6. State representation of hall sensor functionality

N

T1

T6

C1

C2

DC

inpu

t

volt

age

Ra La Ea

Figure 7. Equivalent circuit of phase A of BLDC drive system

25

Figure 8. Simulation circuit diagram in MATLAB/SIMULINK and Xilinx System

Generator environment

Nr(

rpm

) N

r(rp

m)

Nr(

rpm

)

905

900

895

1005

1000

995

1107

1102

1097

759.5 764 768.5 773 777.5

Time(ms)

755

(a)

(b)

(c)

Figure 9 (a)-(c). Simulated speed response of considered BLDC drive for reference

speed of (a) 900 rpm (b) 1000 rpm (c) 1100 rpm, at 30% of rated load condition.

26

Figure 10. Performance evaluation of proposed control scheme in terms of average

and maximum error at different commanded speed.

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0 500 1000 1500 2000 2500 3000 3500

%A

vg

. /

%M

axim

um

Err

or

Speed (rpm)

%Avg. speed error vs Avg.

Speed (rpm)

%Max. speed error vs Ref.

speed (rpm)

27

0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 2.50

350

Vd

c(V

) T

e(N

-m)

0

0

-3

3

Ia(A

)E

a(V

)

150

0

-150

Nr(

rpm

) 2500

0

2

4

Time(s)

Speed

Back EMF

Current

Torque

DC Link Voltage

Steady

state

(a)

(b)

(c)

(d)

(e)

Figure 11. Steady state performance of proposed BLDC motor drive at 2000 rpm and

at 30% of full load condition

28

0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 2.50

250

500

Vd

c(V

) T

e(N

-m)

0

0

-2

-4

2

4

Ia(A

)E

a(V

)

250

0

-250

Nr(

rpm

) 3500

0

2

4

Time(s)

Speed

Back EMF

Current

Torque

Dc link voltage

Steady

state

(a)

(b)

(c)

(d)

(e)

Figure 12. Steady state performance of proposed BLDC motor drive at 3000 rpm and

at 30% of full load condition.

29

Nr(

rpm

) N

r(rp

m)

1200

3000

1500

.50 .75

Time(s)

.25 1.0 1.25 1.5 1.75 2.0 2.25 2.5 2.75

Time(s)

1.500 1.540

1600

2000

2400

2800

3200

766.25 2000

Time(ms)

755 777.5

Nr(

rpm

)

Nr(

rpm

)

1500

14952995.7

3007.7

Time(ms)

2011.25

X axis: Time(ms)

1 div-2.25 ms

X axis: Time(ms)

1 div-2.25 ms

1.5201.4801.460

(a)

(b)

(c) (d)

2022.5

Figure 13. Simulated result, at 30% of full load condition (a) for a step change in

reference speed from 3000 to 1500 rpm, (b) enlarged view for step change showing

response time and tracking, (c)-(d) zoomed view of actual speed to account for ripples

30

0 0.25 0.5 0.75 1.0 1.25 1.5 1.75 2.0 2.25 2.50

250

500

Vd

c(V

) T

e(N

-m)

0

0

-2

-4

2

4

Ia(A

)N

r(rp

m)

3500

0

4

Time(s)

2000

Speed

Current

Torque

DC link voltage

Transient region

Step Change (480 320)V

Transient region

(a)

(b)

(c)

(d)

(i)

Ea(

V)

300

0

-3001.4 1.5 1.525 1.55 1.575 1.6 1.7

Time(s)

Enlarged View of Back EMF

Dynamic region

(ii)

Figure 14. (i) Dynamic performance of proposed BLDC motor drive during step 1

change in speed (ii) Enlarged view of back EMF for phase A, at step change in 2

commanded speed issued at t = 1.5 and t = 1.6, at 30% of rated load. 3

31

List of Tables 1

Table 1. Switching states of the VSI feeding a BLDC motor drive based on the Hall-2

effect position signals 3

State of switches

T1 T2 T3 T4 T5 T6

NA 0 0 0 0 0 0

0-60 0 0 0 1 1 0

60-120 0 1 1 0 0 0

120-180 0 1 0 0 1 0

180-240 1 0 0 0 0 1

240-300 1 0 0 1 0 0

300-360 0 0 1 0 0 1

NA 0 0 0 0 0 0

4

Table 2. Parameters of power circuit considered for simulation 5

S.No. Parameter Numerical Value

BLDC MOTOR DRIVE

1 No. of pole pairs 2

2 Rated Power (Prated) 5 KW

3 Rated Torque (Trated) 10 N.m

4 Rated DC Link Voltage

(Vrated) 480 V

5 Torque Constant (Kt) 1.4 N.m/A

6 Voltage Constant 160 V/k rpm

7 Stator Phase Resistance (Rs) 2.85 ohm

8 Stator Phase Inductance (Ls) 8.5 mH

BUCK BOOST CONVERTER

9 Buck Boost Inductor (L0) 20 mH

10 Buck Boost Capacitor (C0) 800 uF

11 Input Voltage (Vin) 12 V

12 Switching Frequency(fs) 20 kHz

6

32

Table 3. Summary of Simulated Results 1

Proposed

control

technique

Performance

indices

Nr*

(rpm)

Navg

(rpm)

%Average

error

|Maximum

speed ripple|

%Maximum

error

Steady state

performance

900 898.35 0.623 5.62 0.624

1000 999.80 0.40 4.0 0.40

1100 1101.35 0.42 4.62 0.42

Dynamic

performance

1500 1500.1 0.23 3.9 0.26

3000 3001.7 0.11 4.5 0.15

2