0800 - 0830

Instructor(s)

0930 - 1700

0730 - 1730

0730 - 0815

0830 - 0915

1045 - 1110

1110 - 1250

Session Chairs : Loh Wei Keat Session Chairs : Mohd. Nasir Tamin Session Chairs : Dennis Chandran Session Chairs : Klaus Müller

Christopher Breach Eu Poh Leng Daniel Chir Phee Boon Hor

1250 - 1400

1400 - 1445

1445 - 1530

1530 - 1600

1600 - 1720

Session Chairs : LC Tan Session Chairs : Mohd. Nasir Tamin Session Chairs : YS Won Session Chairs : Amir Wagiman

Annette Teng Mohd Sabri Mohd Zin Lem Tien Heng Wang Mei Yong

0930 - 1700

0730 - 0830

0915 - 1000

1000 - 1030

1030 - 1230

Session Chairs : Luu Nguyen Session Chairs : LC Tan Session Chairs : A.S.M.A. Haseeb Session Chairs : Hsiang-Chen Hsu

Shankar Shridhar PM Tan Kim See Mohd Jaffri Razai SW Wang

1230 - 1345

1430 - 1550

Session Chairs : Amir Wagiman Session Chairs : Loh Wei Keat Session Chairs : Klaus Müller Session Chairs : Goh Geok Ling

Prof. Abdul Hamid Annette Teng Chwee Liong Tee Dennis Chandran

1550 - 1620

Session Chairs : Mark Whitmore Session Chairs : Lem Tien Heng Session Chairs : Luu Nguyen Session Chairs : Lim Peng Soon

See Beng Keh Prof. Ahmad Jamal   SW Wang YS Won

Invited Speaker Sessions:Dr. Yutaka Tsukada, Ultra Low CTE (0 ppm/C) Polyimide Film and Its Potential Application - Session D2 (1600 - 1620)John Hunt, Integrated Wafer Level Packaging - An Emerging Synergism - D3 (1040 - 1100)Shankar Shridhar, DFMEA/PFMEA : What They Never Teach You In Formal School - Session D4 (1430:1510)Amir Nur Rashid Wagiman, Miniaturization Innovation Evolution of Electronics Packaging – What’s Coming Next …? - Session D5 (1620 - 1640)

Buffet Lunch at Bendahara Ballroom.

SESSION A3

Award Presentation and Conference Closing Ceremony - Bunga Raya Grand Ballroom

Techniques and Tools II Thermal

Techniques and Tools I

ROOM DAHLIA ROOM MELATI

Guests and participants arrival into Grand Ballroom.

1345 - 1430

Keynote Address II: Current Technology Barriers and Future Direction for Packaging Density Increase.

Dr. Yutaka Tsukada, Proffesor and General Manager, Ritsumeikan/Osaka University, i-PACKS, JAPAN

Coffee Breaks/Poster Session

Keynote Address VII: Small Signal Electrical Testing in Package Engineering

Keynote Address V: Packaging Trends in Mobile Electronics, Towards Wafer Level Packaging.

ROOM DAHLIA ROOM MAWAR

Forum on Industry/University Collaboration - Hosted by Intel Malaysia

ROOM MELATI

Registration at Secretariat Room, Level 7

ROOM MELATI

Buffet Lunch at Bendahara Ballroom.

Keynote Address VI: Importance of Reliability In Electronics.

Tabletop display outside of Conference Room, Level 7

ROOM MAWAR

Conference Opening Address by the President, IEEE-CPMT Society, Dr. Rolf Aschenbrenner

Dr. Bill Chen, Senior Technical Advisor, ASE Inc., USA

ROOM TERATAIROOM MELATI

CONFERENCE SESSIONS (DAY 1) : 1 DECEMBER 2010, WEDNESDAY

Dr. Ho Hong Meng Semicon Fine Wire, SINGAPORE

Dr. Joe Fjelstad Verdant Electronics, USA

Tabletop display outside of Conference Room, Level 7

Dr. Yutaka Tsukada Ritsumeikan/Osaka University,

i-PACKS, JAPAN

EXHIBITION - 1 DECEMBER 2010, WEDNESDAY

Dr. John LauIndustrial Technology Research

Institute, TAIWAN

Materials I

Keynote Address IV: Automotive Electronics – Packaging As Enabler Technology.

IEMT 2010 PROGRAM OVERVIEW : 30 NOV- 2 DEC 2010

Registration at Secretariat Room, Level 7

0830 - 1730 (Inclusive of lunch and cofee breaks)

Morning Session ROOM MAWAR Afternoon Session

SHORT COURSES : 30 NOVEMBER 2010, TUESDAY

Flip Chip Technology

ROOM MELATI (FULL DAY)

State-Of-The-Art and Trends in 3D IC/Si Integrations and WLP

ROOM TERATAI (FULL DAY)

Advanced Copper WirebondingPast, Present and Future of

Packaging

EXHIBITION - 2 DECEMBER 2010, THURSDAY

1830 - 2300

SESSION A5 SESSION C5

Opening Ceremony & Keynote Addresses at Bunga Raya Grand Ballroom

Opening Speech by Azhar Aripin, Chairman, IEEE-CPMT Malaysia Chapter

Welcome Speech by Fuaida Harun, IEMT2010 General Chair

Xavier Baraton, Director of Corporate Packaging & Automation, ST Microelectronics, SINGAPORE

ROOM DAHLIA

ROOM MELATI

Design

1620 - 1740

SESSION A4

ROOM DAHLIA ROOM MAWAR

Test

ROOM MAWAR

Process I

SESSION B1

Solder Joint Reliability And Modeling

Keynote Address III: The Practice of Engineering in The Year of The Tiger.

Advanced Packaging I

0915 - 1000

1000 - 1045

SESSION C1

ROOM DAHLIA ROOM MAWAR

SESSION A1

Keynote Address I: Innovation and Collaboration - Keeping up with Market Demands And Transitions.

Kim Hyland, Sr. Director, Global Manufacturing Operations Engineering, Cisco, USA

SESSION D1

Interconnect III

SESSION D4Interconnect II

ROOM TERATAI

SESSION D5

Coffee Break/Poster Session

SESSION B5

MechanicsSESSION B4 SESSION C4

ROOM TERATAI

ROOM TERATAI

SESSION D3Interconnect I

CS Liu, Senior Vice President, Worldwide Manufacturing, National Semiconductor, USA

SESSION B3 SESSION C3Reliability Electric & Power Delivery Materials III

Registration at Secretariat Room, Level 7

Dr. Joe Fjelstad, President, Verdant Electronics, USA

Coffee Breaks/Poster Session

0830 - 0915

Heterogeneous Integration - A Key Enabling Technology

Dinner/Cultural Show & Tour/Boat Ride

(Dinner/Cultural Show in the Grand Ballroom and Then Proceed to The Nearby Boat Station)

CONFERENCE SESSIONS (DAY 2) : 2 DECEMBER 2010, THURSDAY

SESSION D2Advanced Packaging II

ROOM TERATAI

Dr. Knoblauch Andreas, Director Package Development Automotive, Infineon, GERMANY

Coffee Break/Poster Session

Process II Thermal/Mechanical Modeling Materials IISESSION A2 SESSION B2 SESSION C2

Short Courses – Nov 30th

Short Course I – Full Day

Dr. John H. Lau ITRI, Taiwan

State-of-The-Art and Trends in 3D IC/Si Integrations and WLP

Course Objective: Moore's law has been the most powerful driver for the development of the microelectronic industry. This law emphasizes on lithography scaling and integration (in 2D) of all functions on a single chip, perhaps through system-on-chip (SoC). On the other hand, the integration of all these functions can be achieved through system-in-package (SiP) or, ultimately, 3D IC/Si integration, which is a very complicate subject. It involves component and system designs, FAB, packaging assembly and testing, material suppliers, and equipment suppliers. The key enabling technologies for 3D IC integration are, e.g., electrical, thermal, and mechanical designs and tests, known good die (KGD), TSV (through silicon via) forming and filling, wafer thinning and handling, thin chip strength measurement and improving, lead-free microbump forming and assembly, low temperature C2W and W2W bonding, and thermal management. In this course, all these enabling technologies (except electrical) will be discussed. Most of the materials are based on the technical papers published within the past 3 years by others and the instructor. Course Outline ? Overview of 3D packaging ? Overview of 3D IC integration ? Overview of 3D Si integration ? TSV forming (DRIE and laser) ? TSV dielectric, barrier, and seed-metal layers ? TSV filling and CMP ? Fabrication and characterization of TSV

interposers/chips ? Fabrication and characterization of 3D IC chip

stacking ? Reliability of TSV interposers/chips ? Effects of TSV interposer on thermal

performances ? Effects of TSV interposer on mechanical

performances ? Stress sensor for thin-chip strength

measurement ? Wafer thinning and thin-wafer handling ? Low-cost lead-free microbumps (=25µm pitch):

fabrication and characterization ? Low-cost lead-free microbumps (=25µm pitch):

assembly and reliability

? Low temperature (=180oC) lead-free C2C bonding

? Low temperature (=180oC) lead-free C2W bonding

? Low temperature (=180oC) lead-free W2W bonding

? CMOS image sensor with TSV ? 3D MEMS and IC integration ? 3D LED and IC integration ? Equivalent thermal conductivities for copper-

filled TSV interposer/chip ? Thermal management (design charts and

guidelines) for 3D stacked chips ? Integrated liquid cooling solutions for 3D IC

stacked modules ? Hot spots in thin chips for 3D IC stacking ? Supply chain for 3D IC integration ? Critical issues in adopting TSV and 3D IC

integration ? Overview of optoelectronics ? Overview of optical PCBs ? Summary

Short Course II – Full Day

Dr. Hong Meng Ho

Semicon Fine Wire, Singapore

Advanced Copper Wire Bonding Technology

Abstract Wire bonding is the most dominant form of first-level chip interconnects in microelectronics with gold wire bonding taking the lead fo r the past few decades. Today, it is evident that the shift from gold to copper wire bonding is genuinely picking up, due to both a surge in gold prices and recent developments in copper wire bonding technology. The course will be divided into two main sections:- The first section would discuss the technology trends, the building blocks for copper wire bonding, the key process factors to achieve a reliable copper wire bond and what are the implementation challenges with downstream processes such as interaction with mold compound and its package reliability aspects. The second section would discuss the recent developments in equipment, copper wire material and capillary and how these help realize copper wire bonding in production implementation and how the gaps between gold and copper wire bonding are shorten.

Course Outline First Section ? Industry trends and drivers for copper wire

bonding ? Basic process differences in wire bonding

process for gold and copper wires

? Building blocks for copper wire bonding ? Copper Free Air Ball (FAB) and its impact on

First Bond ? First and Second Bonds challenges and solutions

for copper wire bonding ? Looping challenges for copper wire bonding ? Cu/Al intermetallic compound ? Interaction between copper wire bonding and

mold compound ? Reliability aspects of copper wire bonded

devices Second Section ? Wire bonding equipment developments and its

influencing factors ? Copper wire material developments (bare and

coated wire) and its influencing factors ? Capillary developments and its influencing

factors ? Challenges for high density BGA and QFN

packages ? Challenges for ultra fine pitch copper wire

bonding and its solutions ? Challenges for copper wire bonding on Low-K

and BOAC bondpad structures

Short Course III – Part A (Half Day)

Dr. Joseph Fjelstad

President, Verdant Electronic, USA

Past, Present and Future of Electronic Packaging

Abstracts As the first interconnection element after the semiconductor chip itself, IC packaging technologies are the primary gate keepers of electronic system perfo rmance. There are a myriad of different types of packages available, each normally targeted for a specific range of semiconductor devices. With so many options, understanding the basics of IC packaging - how they are constructed, what drives cost and what limits performance - is critical to the successful product design. Some of the most common IC packages, from chip scale to BGA packages as well as some of the many 3D stacked and folded structures, will be reviewed and discussed. The instructor will also review wafer level packaging. Finally, a look at the future of IC packaging will be provided to stimulate thought on how to actively engage and direct the future of IC packaging in mindful ways. Course Content ? A brief history of IC packaging ? Overview of IC packaging technologies and

the many roles of IC packaging ? Construction and manufacturing processes for

common IC packages ? MCM and SiP structures ? Impact of IC package design on the assembly

processes ? Testing strategies for IC packages including Test

in Tray ? Trends in the integration of IC, package and

PCB substrate ? IC packaging types and applications ? Wafer Level Packaging ? Stacking of chips and packages ? TSV technologies and their impact ? Reliability testing and electrical performance ? Impact of lead free solder on IC packaging and

assembly ? Standards for packaging substrates ? The future of IC packaging - what's new and

what's next

Short Course III – Part B (Half Day)

Dr. Yutaka Tsukada

Ritsumeikan/Osaka University, i-PACKS, Japan

Flip Chip Technology

Course outline 1. History and basics of flip chip technology ? Advantages of flip chip bonding ? Applications on ceramic and organic substrates ? C4 and Underfill reinforced flip chip bonding

2. Elements of design and manufacturing ? Chip and carrier bumping ? Joint and substrate ? Underfill and cooling

3. Packaging configuration ? BGA and SiP (MCM) ? Wafer Level package ? Known Good Die

4. Reliability and life ? Stress test and life estimation ? Typical failure mode ? Failures factorial analysis

5. Current issues for density increase ? Thermal stress ? Joint fatigue life ? Joint electro-migration

6. Requirement for new materials and future direction ? 2D packaging joint and substrate ? 3D chip stack packaging ? Optical/Electrical packaging

7. Japanese packaging technology trend (Special Topics) ? SiP, WLP, PoP, Embedded component ? Product miniaturization

Keynote Speakers – Dec 1st & 2nd

Rolf Aschenbrenner President, IEEE-CPMT Society Fraunhofer Institute For Reliability and Microintegration, GERMANY Heterogeneous Integration – A Key Enabling Technology

Kim Hyland Sr. Director, Global Manufacturing Operations Engineering, Cisco, USA Innovation and Collaboration - Keeping up with Market Demands And Transitions

Dr. Yutaka Tsukada Ritsumeikan/Osaka University, i-PACKS, JAPAN Current Technology Barriers and Future Direction for Packaging

Dr. William Chen Senior Technical Advisor, ASE Group, USA The Practice of Engineering in The Year of The Tiger

Dr. Andreas Knoblauch Director Package Development Automotive, Infineon, GERMANY Automotive electronics – Packaging As Enabler Technology

Xavier Baraton Director of Corporate Packaging & Automation ST Microelectronics, SINGAPORE Packaging Trends in Mobile Electronics - Towards Wafer Level Packaging

Dr. Joseph Fjelstad President, Verdant Electronic, USA The Importance of Reliability in Electronics

C. S. Liu Senior Vice President, Worldwide Manufacturing National Semiconductor, USA IC Testing Technology role on Packaging Development

Invited Paper Speakers - Dec 1st & 2nd

Dr. Yutaka Tsukada Ritsumeikan/Osaka University, i-PACKS, JAPAN Ultra Low CTE (0 ppm/C) Polyimide Film and its Potential Application

John Hunt Director of Engineering ASE Inc, USA Evolutionary Development of Wafer Level Packaging

Shankar Shridhar EQIS Pty Ltd., AUSTRALIA FMEA/PFMEA : What They Never Teach You In formal School.

Amir Nur Rashid Wagiman Senior Manager, Materials Technology Development Intel Technologies, MALAYSIA Miniaturization Innovation Evolution of Electronics Packaging – What’s Coming Next …?

TECHNICAL SESSIONS – DECEMBER 1st and 2nd

1110-1250 Session A1 – Process I Co-Chairs : Loh Wei Keat Christopher Breach A1.1 1110 Investigation of Bond Pad Etching

Chemistries for Passivation Crack. Rusli Ibrahim, Michael Leoni, Au Yin Kheng,

Kenny Poh Zi Song & Eu Poh Leng Freescale Semiconductor Sdn. Bhd., MALAYSIA

A1.2 1130 Investigations of the Effects/Influences of

Dicing Techniques, Process Parameters, and Material Selections on Low-K Wafer Dicing Developments/Improvements.

Koh Wen Shi, Yow K.Y, Rachel Khoo, Calvin Lo Freescale Semiconductor Sdn. Bhd., MALAYSIA

A1.3 1150 Development of Wafer Sawing Capability on

2 mil Saw Street 4 mil Thickness with TiNiAg Back Metal.

PA Kam & SW Wang ON Semiconductor, Sdn. Bhd., MALAYSIA

A1.4 1210 Impacts to Fine Pitch Copper Wire Bonding

Quality by External Airflow. Lau Seng Heng, Lee Say Yeow, Loh Lee Jeng,

Loh Kian Hwa & Ng Wen Chang Carsem (M) Sdn. Bhd., MALAYSIA

A1.5 1230 Ultra Low Loop Conversion from Gold to

Copper Wire. Lee Kuan Fang, Kwon OD, Don Capistrano &

Oranna Yauw Kulicke & Soffa Pte. SINGAPORE

1110-1250 Session B1 – Solder Joints Reliability & Modeling

Co-Chairs : Mohd. Nasir Tamin Eu Poh Leng B1.1 1110 Integrated nCTF Pad Design On PCB For

BGA Solder Joint Reliability Enhancement. Fook Loon Wooi & Ooi Ing Chuan

Intel Product Sdn. Bhd., MALAYSIA B1.2 1130 2nd Level Reliability Drop Test Robustness

for Wafer Level Packages Queck Kian Pin, Yong Wei Wei & Heitzer

Ludwig Infineon Technologies Sdn. Bhd., MALAYSIA

B1.3 1150 Effect Of Convection And Conduction Oven To The Intermetallic Formation And Solder Joint Reliability.

Yong Wei Wei & Ronnie Tan Chin Wei Infineon Technologies Sdn. Bhd., MALAYSIA

B1.4 1210 No-clean Polymer Flux Evaluations and its

Impact on BGA Solder Joint Quality and Reliability

Serene Lee Choon Mei , Carlo Marbella & Tan Ai Min Infineon Technologies Asia Pacific Pte Ltd, SINGAPORE

B1.5 1230 Progressive Damage In Sn-4Ag-0.5Cu Solder

Joints During Flexural Fatigue Of A BGA Package.

N.M. Shaffiar1, W.K. Loh2, N. Kamsah1 & M.N. Tamin1

1Universiti Teknologi Malaysia, MALAYSIA 2Intel Technology Sdn. Bhd., MALAYSIA

1110-1250 Session C1 – Materials I Co-Chairs : Dennis Prem Kumar Chandran Daniel Chir

C1.1 1110 Alternative Robust Reliability Solution For Silver Finishing

Soon-Lock Goh1, Swee-Kah Lee1, Din-Ghee Neoh2 & Sia-Wing Kok2 1Infineon Technologies Sdn. Bhd., MALAYSIA 2Atotech Sdn. Bhd., MALAYSIA

C1.2 1130 Electroless Over Pad Metallization for High

Temperature Interconnections S. Qu11, K. Pham1, L. Nguyen1, A. Prabhu1, A.

Poddar1, Y. C. How2, C. S. Lee2 & K. C. Ooi2 1National Semiconductor, USA 2National Semiconductor Sdn. Bhd., MALAYSIA

C1.3 1150 Adaptation of Brass Core Leadframe

Material in IC Packaging Koo Kok Kiat & Tan Ai Min

Infineon Technologies Asia Pacific Pte Ltd, SINGAPORE

C1.4 1210 Solving Eventual Bonding Quality To

Enhance Adhesion For QFN Packages Suresh Kumar1, Siva Rao1, MT Cheong2, Mohd

Azmeer2 & Harun Fuaida3 1Universiti Teknikal Malaysia Melaka, MALAYSIA 2Carsem Semiconductor Sdn. Bhd., MALAYSIA 3Infineon Technologies Sdn. Bhd., MALAYSIA

C1.5 1230 Interfacial Reactions of SAC305 and SAC405 Solders on Electroless Ni(P)/ Immersion Au and Electroless Ni(B)/ Immersion Au Finishes.

Siti Rabiatull Aisha1, A. Ourdjini1, N. M. Wah1, H. C How2 & Y. T. Chin2 1University Technology Malaysia, MALAYSIA 2Intel Technology Sdn. Bhd., MALAYSIA

1110-1250 Session D1 – Advanced Packaging I Co-Chairs : Klaus Müller Phee Boon Hor

D1.1 1110 Meeting the Assembly Challenges in New Semiconductor Packaging Trend

LY Lim Fairchild Semiconductor (Malaysia) Sdn. Bhd., MALAYSIA

D1.2 1130 Plasma Process Considerations in Emerging

Semiconductor Packaging Technologies Daniel Chir

Nordson MARCH, SINGAPORE D1.3 1150 Fabrication of Silica/Epoxy Thin Film

Composite for Electronic Packaging Application.

Foo, Y.L.E.1, Mariatti, M1, Azizan, A.1, & Sim, L.C.2 1Universiti Sains Malaysia,, MALAYSIA 2 Intel Technology Sdn. Bhd., MALAYSIA

D1.4 1210 Keep On Shrinking Interconnect Size: Is It

Still The Best Solution ? S. de Rivaz1, A. Farcy2, T. Lacrevaz1, B.

Flechet1 & D. Deschacht3

1Université de Savoie, FRANCE 2STMicroelectronics, FRANCE 3Université Montpellier II, FRANCE

D1.5 1230 3D Packaging Technology: Enabling the Next

Wave of Applications. Mario A. Bolanos

Texas Instruments Sdn. Bhd., MALAYSIA 1600-1720 Session A2 – Process II Co-Chairs : LC Tan Annette Teng

A2.1 1600 Chipping Free Process For Combination Of Narrow Saw Street (60um) And Thick Wafer (600um) Sawing Process

Mohd Syahrin Amri1, David Liew2 & Fuaida Harun2 1Universiti Teknikal Malaysia Melaka, MALAYSIA 2Infineon Technologies Sdn. Bhd., MALAYSIA

A2.2 1620 Alternative Dicing Die Attach Film Method For High Volume Small Dice Application

KF Lim National Semiconductor Sdn. Bhd., MALAYSIA

A2.3 1640 Thermal Simulation Study of Die Attach

Delamination Effect on Plastic Package Thermal Resistance

CH Mak & Eugene Lee National Semiconductor Sdn. Bhd., MALAYSIA

A2.4 1700 High-speed Vision Challenge for 100% Online

On-Strip Inspection Chen Wanliang, Xiang YongRong & Ruan

Jianhua Leshan Phoenix Semiconductor Co. Ltd., CHINA

1600-1720 Session B2 – Thermal/Mechanical Modeling Co-Chairs : Mohd. Nasir Tamin Mohd Sabri Mohd Zin

B2.1 1600 Application of Finite Element Analysis to Reduce Problem of Ground Ring Delamination

Foo Yeong Lee, Leong Kong Yang & Chai Chee Meng Infineon Technologies Sdn. Bhd., MALAYSIA

B2.2 1620 Integrated Mechanical Modeling for

Reliability Analysis of Polymeric Materials and Leadframe Dimensional Impact in High Density IC Packaging

SK Chin & Eric Erfe Carsem (M) Sdn. Bhd., MALAYSIA

B2.3 1640 Advanced Finite Element Model on Copper

Wire Wirebonding Hsiang-Chen Hsu, Hong-Shen Chang & Shen-Li

Fu I-Shou University, TAIWAN

B2.4 1700 Impact of Molding Parameters in PBGA

Warpage Loh Wei Keat, Quah Chin Aik, Lee Chee Kan &

Lee Chek Loon Intel Technology Sdn. Bhd., MALAYSIA

1600-1720 Session C2 – Materials II Co-Chairs : YS Won Lem Tien Heng

C2.1 1600 Phase Diagram, Thermodynamics and Microstructure of Al-Mg System

Souilah Zahi Multimedia University, MALAYSIA

C2.2 1620 Halogen Free Flame Retardants for Epoxy Substrate in Electronic Applications

Lim, P.W.K1., Mariatti, M.1, Chow, W.S.1 & Mar, K.T.2

1Universiti Sains Malaysia,, MALAYSIA 2Intel Technology (M) Sdn. Bhd., Pulau Pinang, Malaysia

C2.3 1640 Measurement of Thermal Resistance of TIMs,

Heat Sinks and Interfaces in Thermal Management Systems for IC Packages

Sivanand Somasundaram & Andrew A. O. Tay National University of Singapore, SINGAPORE

C2.4 1700 Tombstoning Reduction by Reflow Profile

Optimisation, SMT Pad Design and Stencil Design

Ho Tuck Ming & Tan Kong Ming Carsem (M) Sdn. Bhd., MALAYSIA

1600-1720 Session D2 – Advanced Packaging II Co-Chairs : Amir Wagiman Wang Mei Yong

D2.1 1600 Ultra Low CTE (0 ppm/C) Polyimide Film and its Potential Application

Dr. Yutaka Tsukada Ritsumeikan/Osaka University, i-PACKS, JAPAN

D2.2 1620 A Study Of Deep Body Implant Into The Base

Of Vertical NPN Bipolar Transistors Tan Chan Lik, Cheng Chin Siong, Ong King Ang

& Hussein Mohammed Reza Infineon Technologies Sdn. Bhd., MALAYSIA

D2.3 1640 Leaded Module - The Next Industry Trend

For Best In Class Thermal Performance And Ease Of Use

KY Woo & Eugene Lee National Semiconductor, MALAYSIA

D2.4 1700 C45 Ultra Low k Wafer Technology with Cu

Wire Bonding Eu Poh Leng & Chin Teik Siong

Freescale Semiconductor Sdn. Bhd., MALAYSIA

1030-1230 Session A3 – Reliability Co-Chairs : Luu Nguyen Shankar Shridhar

A3.1 1110 Influence Of Wafer Probing Against Initial Bonding

Tan Kim Guan1 , Harun Fuaida1, Suresh Kumar2 & Siva Rao2 1Infineon Technologies Sdn. Bhd, MALAYSIA 2Universiti Teknikal Malaysia Melaka, MALAYSIA

A3.2 1030 A Reliable Low Cost Assembly Technology

for 0201 Compatible QFN, X3 Thin QFN WL Law, Nicole Yong, SH Liew, Daniel Phuah,

KF Chung & PN Ng Carsem Sdn. Bhd., MALAYSIA

A3.3 1050 Metal Line And Via Electromigration

Improvement With Wafer Level Tests Ng Hong Seng & Evie Kho Siaw Hei

X-FAB Sarawak Sdn. Bhd., MALAYSIA A3.4 1130 Low Profile TSOP Approach For MSL1

Delamination Free Chow Ti Leong & Chin Wai Lum

ON Semiconductor, Sdn. Bhd., MALAYSIA A3.5 1150 Interaction of Multiple Delaminations and Die

in a Plastic IC Package Siow Ling Ho, Jiyin Yu & Andrew A. O. TAY

National University of Singapore, SINGAPORE A3.6 1210 A Consideration on the Electrical

Overstress(EOS) Failure Mechanism in the Interconnection System of Liquid Crystal Display(LCD) Panel

Jae-Hyung Kim, Dong-Nam Kim, Ho-Cheol Jang & Byung-Ju Lee Technology Leaders & Innovators Inc., KOREA

1030-1230 Session B3 – Electric & Power Delivery Co-Chairs : LC Tan PM Tan Kim See

B3.1 1030 Design an Integrated Microprocessor Supervisory Chip for Monitoring Power Failure

N.Intan, M.Amir Abas IEEE Member & S.Sakrani Universiti Kuala Lumpur British Malaysian Institute, MALAYSIA

B3.2 1050 Simulation- Measurement Correlation Study of Single Ended Interfaces by using Signal Integrity and Power Integrity co-Simulation

Wong Tai Loong & Lim Chin Chuan Intel Microelectronics Sdn. Bhd., MALAYSIA

B3.3 1110 Filler Size Influence on Moldabilty of High

Density QFN Package Chew Pei Yi, Kathleen Ong, Queck Kian Pin &

Lee Swee Kah Infineon Technologies Sdn. Bhd, MALAYSIA

B3.4 1130 Integrated Solution for High Speed Data

Filtering Using Package-in-Package Approach

Bih Wen Fon & Atapol Prajuckamol ON Semiconductor, MALAYSIA

B3.5 1150 Approaches And Developments In MEMs

Power Harvesting Generators Mohammed Dhia

University Tenaga Nasional, MALAYSIA B3.6 1210 The Very First Strain Range Bound Guidance

Methodology for System Level Shock Evaluation

Ian Chin Intel Technology Sdn. Bhd., MALAYSIA

1030-1230 Session C3 – Materials III Co-Chairs : A.S.M.A. Haseeb Mohd Jaffri Razai

C3.1 1030 Concurrent Design for Robust and Cost-Efficient Semiconductor Manufacturing

Foo Yeong Lee, Lim Siew Lin & Wang Mei Yong Infineon Technologies Sdn. Bhd., MALAYSIA

C3.2 1050 High Temperature Storage Performance for

Au Sn Diffusion Soldering with 75Au25Sn at 175C Aging Temperature on Cu Leadframe Substrate

Zakaria.Abdullah & Mohamed Abd Rahman Infineon Technologies Sdn. Bhd., MALAYSIA

C3.3 1110 Effect Of Pickling Temperature On Adhesion

Strength Of Ti Oxide Layer On Titanium Alloy Substrate

S. Izman, Mohemmed Rafiq Abdul-Kadir, Mahmood Anwar, E. M. Nazim & E. K. Khor University Technology Malaysia, MALAYSIA

C3.4 1130 Molding Technology Development of Large

QFN Packages Jhen Wei Seah

ON Semiconductor, Sdn. Bhd., MALAYSIA

C3.5 1150 Effect On Interfacial Reactions And Die Attach Properties Of Zn-Al-Mg-Ga High Temperature Pb-Free Solder By Introducing Ni Metallization On Cu Substrate

A. Haque1, Y. S. Won2, B. H. Lim2, A. S. M. A. Haseeb1 & H. H. Masjuki1 1University of Malaya, MALAYSIA 2ON Semiconductor, Sdn. Bhd., MALAYSIA

C3.6 1210 Study on IMC Morphology and Impact to

Solder Joint Performance for Different Halogen Free (HF) Flux in Semiconductor Application

Ooi Wan Koon1, Mohd Jaffri Razai1, Chan Boon Pin2 & Dr. Nurul Akmal Mohd Sharif2

1Intel Technology Sdn. Bhd., MALAYSIA 2University Science Malaysia, MALAYSIA

1030-1230 Session D3 – Interconnect I Co-Chairs : Hsiang-Chen Hsu SW Wang

D3.1 1030 Evolutionary Development of Wafer Level Packaging.

John Hunt ASE Inc, USA

D3.2 1050 Enablers of Robust Sub-40 micrometer Ultra

Fine Pitch Ball Bonding. Shawn D. Sarbacker, Ph.D.

Kulicke & Soffa Industries, Inc., USA D3.3 1110 Cu Wire Bonding on Cu-Ni-Pd bond pad and

leads : From Development to Robust Production.

Hanafi Said Texas Instruments Sdn. Bhd., MALAYSIA

D3.4 1130 The Challenges of High Density Wires in

C45SOI 40µm Package Low Boon Yew & Siong Chin Teck

Freescale Semiconductors Sdn. Bhd., MALAYSIA

D3.5 1150 A Study on Fine Pitch Au and Cu WB

Integrity vs Ni thickness of Ni/Pd/Au bond pad on C90 Low k Wafer Technology for High Temperature Automotive

Eu Poh Leng1, Au Yin Kheng1, Poh Zi Song1, Yong C.C.1, Tran Tu.Anh2, John Arthur2, Harold Downey2 & Varughese Mathew2

1Freescale Semiconductor Sdn. Bhd., MALAYSIA 2Freescale Semiconductor Inc., USA

D3.6 1210 Wire Sweep Characterization of Multi-tier Copper Wire Bonding on Thermally-Enhanced Plastic Ball Grid Array Packages

Serene SH Teh, BY Low, CS Foong & CT Siong Freescale Semiconductor Sdn. Bhd., MALAYSIA

1430-1550 Session A4 – Techniques & Tools I Co-Chairs : Amir Wagiman Prof. Abdul Hamid

A4.1 1430 Optimization Of An Isotropic Etching Process On Silicon Wafers.

Rozzeta Dolah, Hamidon Musa & Astuty Amrin University Teknology Malaysia, MALAYSIA

A4.2 1450 The Development of New SMT Printing

Techniques for Mixed Technology (Heterogeneous) Assembly.

Mark Whitmore & Clive Ashmore DEK Printing Machines Ltd, UK

A4.3 1510 3DFlex: A Flexible System For Total Visual

Inspection of Bumped Devices. Yuri L. de Meneses, Jerome Paratte, Peeyush

Bhatia & Serge Kunzli Ismeca Semiconductor SA, SWITZERLAND

A4.4 1530 Alternate Package Coplanarity Requirement

and Its Correlation to Reflow Warpage Lee, Yung Hsiang, Ong, Kang Eu, Loh, Wei Keat

& Wong, Shaw Fong Intel Technology Sdn. Bhd., MALAYSIA

1430-1550 Session B4 – Mechanics Co-Chairs : Loh Wei Keat Annette Teng

B4.1 1430 An Analysis on Oxidation, Contamination, Adhesion, Mechanical Stress and Electro- Etching Effect Towards DIP Package Delamination

Wang H.T & Heng CW Infineon Technologies Sdn. Bhd., MALAYSIA

B4.2 1450 Separation of the Bar : Systemic Solution of

Runner Bar Cull Remain Problem through Leadframe Design Change

Richard “Chay” Tan, Jose Mario Gemal & Leo Lim ON Semiconductor Philippines Inc., PHILIPPINES

B4.3 1510 Wafer Sort Yield Improvement by Localizing and Applying Optical Proximity Correction on a Metal Bridging Issue

Russell M. Dumlao1, Karsten P. Ulland2, Ma. Shiela Angeli C. Marcos1 & David Beasterfield2 1ON Semiconductor Philippines Inc., PHILIPPINES 2ON Semiconductor Philippines Inc., USA

B4.4 1530 Package Warpage Challenges for 144 Lead

LQFP and Its Impact on Lead Coplanarity Teng Seng Kiong, Ibrahim Ruzaini, M

Kesvakumar & Foong Chee Seng Freescale Semiconductors Sdn. Bhd., MALAYSIA

1430-1550 Session C4 – Tests Co-Chairs : Klaus Müller Chwee Liong Tee

C4.1 1430 Built In Self Test (BIST) Survey-An Industry Snapshot of HVM Component BIST usage at Board and System Test

Zoë Conroy1 & Hui Li2

1Cisco Systems Inc., USA 2Agilent Technologies, SINGAPORE

C4.2 1450 RF Shields That Can Be Integrated With IC

Test Handlers C. L. Lim

Avago Technologies Sdn. Bhd., MALAYSIA C4.3 1510 Shorten Electrical Test Time With Double

Ramping Test Method Ho Tze Yuan & Lee Tai Keong

Infineon Technologies Sdn. Bhd., MALAYSIA C4.4 1530 LED WtW Platform (World LED Fastest

Wafer Rebuilt Platform With Unique Foil to Foil Process)

Massimo Scarpella Ismeca Semiconductor SA, SWITZERLAND

1430-1550 Session D4 – Interconnect II Co-Chairs : Goh Geok Ling Dennis Prem Kumar Chandran

D4.1 1430 (40 min)

FMEA/PFMEA : What They Never Teach You In formal School

Shankar Shridhar EQIS Pty Ltd., AUSTRALIA

D4.2 1510 Environmental Friendly Package

Development By Using Copper Wirebonding CL Gan, TT Toong, CP Lim & CY Ng

Altera Corporation Sdn. Bhd., MALAYSIA

D4.3 1530 Moisture Induced Corrosion in Gold and Copper Ball Bonds

C. D. Breach1 & R. Holliday2 1ProMat Consultants, SINGAPORE 2World Gold Council, UNITED KINGDOM

1620-1740 Session A5 – Techniques & Tools II Co-Chairs : Mark Whitmore See Beng Keh

A5.1 1620 Color Detection For Defect Inspection On Electronic Devices

Pierrick Abrial, Yuri L. de Meneses & Peeyush Bhatia Ismeca Semiconductor SA, SWITZERLAND

A5.2 1640 TRIZ: Application of Advanced Problem

Solving Methodology (ARIZ) in Manufacturing

Yeoh Tay Jin & Yeoh Teong San Intel Technology Sdn. Bhd., MALAYSIA

A5.3 1700 Correlation Effects of ATE Transfers: An

Empirical Study Ma. Shiela Angeli C. Marcos & Imee Rose M.

Tagaca ON Semiconductor Inc., PHILIPPINES

A5.4 1720 Success Story Of Collaboration Between Intel

And Malaysian Universities To Establish And Enhance Teaching And Research In Electronic Packaging

Dennis Prem Kumar Chandran, Sow, Yeek Kooi, Mohd Hasri Mohd Harizan, Chee Choong Kooi, Teoh Teik Hoy, Chong Kim Foong Intel Technology Sdn. Bhd., MALAYSIA

1620-1740 Session B5 – Thermal Co-Chairs : Lem Tien Heng Prof. Ahmad Jamal

B5.1 1620 Resolving Thermal Resistance Problem of Analog Device in Conjunction with the ONxx Shrink Die Technology

Yolando G. Yabut & Albert Reyes ON Semiconductor Philippines Inc., PHILIPPINES

B5.2 1640 Design And Modeling Of A 40W Microwave

Switch In QFN 2x2 Package Chin-Leong Lim

Avago Technologies, MALAYSIA B5.3 1700 Thermal Resistance (Rth) Enhancement by

Optimizing TO Package Thermal Contact Lee Teck Sim & Darakorn Sae Le

Infineon Technologies (Malaysia) Sdn. Bhd.

B5.4 1720 Cooling Performance of Piezoelectric Fan in Notebook System

Ng Kar Mun1 & Hiroaki Wada2 1Intel Asia-Pacific Research & Development Ltd., CHINA 2Murata Manufacturing Co. Ltd., JAPAN

1620-1740 Session C5 – Design Co-Chairs : Luu Nguyen SW Wang

C5.1 1620 Package Autoclave Delamination Study by Substrate Design Improvement

Jinmei Liu, Junhua Luo & Jinzhong Yao Freescale Semiconductor Ltd., CHINA

C5.2 1640 Power Gating Techniques on Platform

Controller Hub Fern Nee Tan, Sze Geat Pang, Lee Kee

Yong & Chee Siong Lee Intel Technology Sdn. Bhd., MALAYSIA

C5.3 1700 Package Crack Resolution Through Low

Stress Dambar Punch Design: A Six Sigma DMAIC Approach

Angelo R. Uy, Marvin V. Picardal, Patrocinio Enriquez & Arnold C. Alaraz ON Semiconductor Philippines Inc., PHILIPPINES

C5.4 1720 Frequency and Time Domain

Characterization of Substrate Coupling Effects in 3D Integration Stack

E. Eid1, T. Lacrevaz1, C. Bermond1, S. Capraro1, J. Roullard1, B. Fléchet1, L. Cadix12, A. Farcy2, P. Ancey2, F. Calmon3, O. Valorge3 & P. Leduc4

1Université de Savoie, FRANCE 2STMicroelectronics, FRANCE 3Institut des Nanotechnologies de Lyon, FRANCE 4CEA-LETI, FRANCE

1620-1740 Session D5 – Interconnect III Co-Chairs : Lim Peng Soon YS Won

D5.1 1620 Miniaturization Innovation Evolution of Electronics Packaging – What’s Coming Next …?

Amir Nur Rashid Wagiman Intel Technologies, MALAYSIA

D5.2 1640 Challenges in Copper 2nd Bond Quality on

Nickel Palladium Leadframe Tan Kian Heong & Fuaida Harun

Infineon Technologies Sdn. Bhd., MALAYSIA

D5.3 1700 Development of Copper-Copper Bonding by Ultrasonic Welding for IGBT Modules

Kazumasa Kido, Fumihiko Momose, Yoshitaka Nishimura & Tomoaki Goto Fuji Electric Systems Co. Ltd., JAPAN

D5.4 1720 A Tiny SO Package Cu Wire Neck Fatigue Fracturing Elimination

Song Xiaoqing, Wei Haili & Zhao Hongbin Leshan Phoenix Semiconductor Co. Ltd., CHINA

POSTER PAPERS

Poster Paper Presentations will be held on the 1st and 2nd of December at the Foyer outside the conference rooms. All poster papers will be put up on display together on the display boards. Authors of the papers are required to be present at their presentation posters at the time specified. There will be two-day sessions for the poster paper presentations.

CONFERENCE DAY 1 – DECEMBER 1ST , LEVEL 7 P1-1 The Theory, Practice And Application Of Thermal Resistance Measurements Of IGBT Devices. Low Khai Yen Charles Infineon Technologies Sdn. Bhd., MALAYSIA P1-2 Multiple Quantum Well Gainnas For Ridge-Waveguide Laser Diodes. Nor Azlian Abdul Manaf, Mohd Sharizal Alias, Sufian Mousa Mitani & Farha Maskuriy Telekom Malaysia Research and Development, MALAYSIA P1-3 A Proposed Approach In Applying Optical Character Recognition And String Concatenation Loop Programming For Thermal Image Processing.

Chan Wai Ti1, Dr. Ir. Sim Kok Swee

1 & Dr. Tso Chih Ping

2

1Multimedia University, MALAYSIA

2Nanyang Technological University, SINGAPORE

P1-4 Comparison of Energy Harvesting Power Management Technique and Applications Mohd Sofwan Mohd Resali University Tenaga National, MALAYSIA CONFERENCE DAY 2 – DECEMBER 2ND, LEVEL 7 P2-1 Improved Corner Rounding Method for Trenched MOSFET. Ng Hong Seng X-FAB Sarawak Sdn. Bhd., MALAYSIA P2-2 A Lean Approach In Processor Platform Validation (PPV) Effective Test Interface Unit (TIU) Performance Improvement. Chia Saw Ean Intel Technology Sdn. Bhd., MALAYSIA P2-3 Extending The Technology Envelope Of Equipment Fungibility With Single Minute Exchange Die Novel Solution. Octovia Peter Intel Technology Sdn. Bhd., MALAYSIA

Institute of Electrical and Electronics Engineers

34th International Electronics Manufacturing Technology Conference (IEMT 2010) Renaissance Hotel, Melaka, Malaysia 30th November- 2nd December, 2010

IEEE Component, Packaging and Manufacturing Technology Society

CONFERENCE REGISTRATION FORM A. Participant’s Information (use additional sheet if needed). Name Designation Preferred Name on Badge IEEE Membership No. 1. ------------------------------------ ----------------------------- ---------------------------------- ------------------------------ 2. ------------------------------------ ----------------------------- ---------------------------------- ------------------------------ B. Contact Information Organization : Dept : Tel : Fax : Mailing Address : City/State : Zip : Country : Email :

R E G I S T R A T I O N F E E D E T A I L S PART I : CONFERENCE REGISTRATION (Please tick ( v ) on the appropriate box/boxes accordingly).

CONFERENCE ON 1 ST & 2ND DECEMBER 2010 (2 FULL DAYS). EARLY BIRD REGISTRATION FEE (BEFORE 1 ST NOVEMBERBER 2010)

CATEGORIES CONFERENCE FEE SHORT COURSE FEE CONFERENCE + SHORT COURSE

[ ] SPEAKERS [ ] RM570 As below [ ] RM970

[ ] IEEE MEMBER [ ] RM700 [ ] RM500 [ ] RM1100

[ ] NON IEEE MEMBER [ ] RM880 [ ] RM600 [ ] RM1350

[ ] FULL TIME STUDENTS [ ] RM520 [ ] RM450 [ ] RM920

LATE FEE CHARGE – A late fee charge of RM100 will be imposed to all registrations that are submitted after 1 st November 2010

Note: 1 Ringgit (MYR) is approximately US$0.31 TOTAL AMOUNT ? Conference registration fee on 1st and 2nd December 2010 includes daily luncheons, 2 coffee breaks, program book and softcopy of proceedings. ? Short Course registration fee on 30th November 2010 includes one luncheon, 2 coffee breaks and a set of course notes.

PART II : SHORT COURSE REGISTRATION (Please tick ( v ) on the respective box accordingly) SHORT COURSE ON 30TH NOVEMBER 2010 (1 FULL DAY)

MORNING SHORT COURSE (8:15 – 12:15 PM) AFTERNOON SHORT COURSE (1:30 – 5:30 PM)

[ ] Short Course I Topic : State-of-The-Art and Trends in 3D IC/Si Integrations and WLP. Instructor : Dr. John Lau Industial Technology Research Institute, TAIWAN [ ] Short Course II Topic : Advanced Copper Wire Bonding Technology. Instructor : Dr. Ho Hong Meng Semicon Fine Wire, SINGAPORE [ ] Short Course III (Part I) Topic : Past, Present and Future of Electronic Packaging. Instructor : Dr. Joseph Fjelstad Verdant Electronics, USA

[ ] Short Course III (Part II) Topic : Flip Chip Technology. Instructor : Dr. Yutaka Tsukada Ritsumeikan/Osaka university, i-PACKS, JAPAN

PAYMENT DETAILS (IN MALAYSIAN RINGGIT) Registration is limited so please register early. To register, fill out registration form, and send along with check or bank draft payment. Please do not mail if previously faxed. All payment for the registration is to be made payable in Ringgit Malaysia to : IEEE MALAYSIA SECTION.

[ ] Cheque/Bank Draft Cheque/Bank Draft No : Bank Name : (Only cheque or bank draft drawn in Malaysian bank are acceptable)

[ ] Credit Card Payment Type of card [ ] Visa [ ] MasterCard

Card Holder’s Name (as it appears in the card) Signature : Credit Card Number : Card Expiry Date : / Card ID No. I hereby authorized IEMT 2010 to charge the amount of RM Date :

Special Meal Request (if any) : [ ] Vegetarian

Mail or fax registration form to : 34th IEMT2010 Secretariat, (Attention : Ms. Tracy Ow) Infineon Technologies (Malaysia) Sdn. Bhd. FTZ , Batu Berendam, 75350 Melaka, Malaysia Tel : +6-06-230 3480 Fax : +6-06-231 4233 Email : Tracy.Ow@infineon.com Conference website : http://ewh.ieee.org/r10/malaysia/cpmt/iemt.htm