+ All Categories
Home > Documents > Quadratic VLSI Placement

Quadratic VLSI Placement

Date post: 30-Jan-2016
Category:
Upload: jennis
View: 51 times
Download: 7 times
Share this document with a friend
Description:
Quadratic VLSI Placement. Manolis Pantelias. General. Various types of VLSI placement Simulated-Annealing Quadratic or Force-Directed Min-Cut Nonlinear Programming Mix of the above Quadratic placers Try to minimize a quadratic wirelength objective function - PowerPoint PPT Presentation
27
Quadratic VLSI Placement Manolis Pantelias
Transcript
Page 1: Quadratic VLSI Placement

Quadratic VLSI Placement

Manolis Pantelias

Page 2: Quadratic VLSI Placement

General

Various types of VLSI placement Simulated-Annealing Quadratic or Force-Directed Min-Cut Nonlinear Programming Mix of the above

Quadratic placers Try to minimize a quadratic wirelength objective function

Indirect measure of the wirelength but can be minimized quite efficiently

Results in a large amount of overlap among cells Additional techniques needed

Page 3: Quadratic VLSI Placement

ProudProud

R. S. Tsay, E. Kuh and C. P. Hsu, “Proud: A

Sea-of-Gates Placement Algorithm”

Page 4: Quadratic VLSI Placement

Objective function

Don’t minimize the wirelength but the squared wirelength:

cij between module i and module j could be the number of nets connecting the two modules

Connectivity matrix C = [cij] B = D – C D is a diagonal matrix with:

Only the one-dimensional problem needs to be considered because of the symmetry between x and y

Page 5: Quadratic VLSI Placement

Electric Network Analogy

Objective function xTBx can be interpreted as the power dissipation of an n-node linear resistive network

Vector x corresponds to the voltage vector x = [x1 x2]T, x1 is of dimension m and is to be determined, x2 is

due to the fixed I/O pads B contains the conductance of the nodes

–bij is the conductance between node i and node j

Page 6: Quadratic VLSI Placement

Electric Network Analogy (Cont’d)

Placement problem is equivalent to that of choosing voltage vector for which power is a minimum B11x1 + B12x2 = 0 B21x1 + B22x2 = i2

Solve for Ax1 = b Where A = B11, b = - B12x2

Solved with iterating method (successive over-relaxation or SOR)

Page 7: Quadratic VLSI Placement

Placement and Partitioning

How to avoid module overlap? Solution: Iterative partitioning in a hierarchical way Add module areas from left to right until roughly half of the total

area, that defines partition-line Make modules to the right of partition-line fixed, modules to the

left of partition-line movable Project fixed modules to center-line Perform global placement in the left-plane (of center-line)

Page 8: Quadratic VLSI Placement

Placement and Partitioning (Cont’d)

Make all modules in the left-plane fixed, project to the center line

Make modules to the right of cut-line movables

Perform global placement in the right-plane Proceed with horizontal cuts on each half Continue until each block contains one and

only module

Page 9: Quadratic VLSI Placement

BGS Iteration

For a given hierarchy perform the previous partitioning more than once Assume a vertical cut y1 splits into y1a, y1b for each half

y1a* and y1b

* are perturbed solution from y1a and y1b because of the partitioning process

2-5 iterations give very good results at each hierarchy

Page 10: Quadratic VLSI Placement

Problems

A bad decision at a higher level affects the placement results of lower levels

Difficult to overcome a bad partitioning of a higher level Backtracking?

Page 11: Quadratic VLSI Placement

KraftWerkKraftWerk

Hans Eisenmann and F. Johannes,

“Generic Global Placement and Floorplanning”

Page 12: Quadratic VLSI Placement

Force Directed Approach

Transform the placement problem to the classical mechanics problem of a system of objects attached to springs.

Analogies: Module (Block/Cell/Gate) = Object Net = Spring Net weight = Spring constant. Optimal placement = Equilibrium configuration

Page 13: Quadratic VLSI Placement

An Example

Resultant Force

Page 14: Quadratic VLSI Placement

Force Calculation

Hooke’s Law: Force = Spring Constant x Distance

Can consider forces in x- and y-direction separately:

(xi, yi)

(xj, yj)

)(F)(F

)()(F

Cost Net )()( Distance

y

x

22

22

ijij

ijij

ijijij

ij

ijijij

yycxxc

yyxxc

cyyxxd

FFx

Fy

Page 15: Quadratic VLSI Placement

Problem Formulation

Equilibrium: j cij (xj - xi) = 0 for all module i.

However, trivial solution: xj = xi for all i, j. Everything placed on the same position!

Need to have some way to avoid overlapping. Have connections to fixed I/O pins on the

boundary of the placement region. Push cells away from dense region to sparse

region

Page 16: Quadratic VLSI Placement

Kraftwerk Approach Iteratively solve the quadratic formulation:

Spread cells by additional forces:

Density-based force proposed Push cells away from dense region to sparse region

The force exerted on a cell by another cell is repelling and proportional to the inverse of their distance.

The force exerted on a cell by a place is attracting and proportional to the inverse of their distance

0

)(Min 21

dCp

constpdCpppf TT

0 fdCp

)','(' and ),( where

'''

')','(

2),( 2

yxryxr

dydxrr

rryxD

kyxf

// equivalent to spring force

// equilibrium

Page 17: Quadratic VLSI Placement

Some Details

Let fi be the additional force applied to cell i The proportional constant k is chosen so that the

maximum of all fi is the same as the force of a net with length K(W+H)

K is a user-defined parameter K=0.2 for standard operation K=1.0 for fast operation

Can be extended to handle timing, mixed block placement and floorplanning, congestion, heat-driven placement, incremental changes, etc.

Page 18: Quadratic VLSI Placement

Some Potential Problems of Kraftwerk

Convergence is difficult to control Large K oscillation Small K slow convergence

Example:

Layout of a multiplier

Density-based force is expensive to compute

'''

')','(

2),( 2 dydx

rr

rryxD

kyxf

Page 19: Quadratic VLSI Placement

FastPlaceFastPlace

Natarajan Viswanathan and Chris Chu, “FastPlace: Efficient Analytical

Placement using Cell Shifting, Iterative Local Refinement and a Hybrid Net

Model”

Page 20: Quadratic VLSI Placement

FastPlace Approach

Framework:repeat

Solve the convex quadratic program Reduce wirelength by iterative heuristic Spread the cells

until the cells are evenly distributed

Special features of FastPlace: Cell Shifting

Easy-to-compute technique Enable fast convergence

Hybrid Net Model Speed up solving of convex QP

Iterative Local Refinement Minimize wirelength based on linear objective

Page 21: Quadratic VLSI Placement

Cell Shifting1.1. Shifting of bin boundary Shifting of bin boundary

Uniform Bin Structure Non-uniform Bin Structure

2.2. Shifting of cells linearly within each Shifting of cells linearly within each binbin Apply to all rows and all columns independently

Page 22: Quadratic VLSI Placement

Cell Shifting – Animation …

NBi

Bini

Bini+1

OBiOBi-1 OBi+1

Ui Ui+1

j

k

l

Bini

Bini+1

OBiOBi-1 OBi+1

j

k

l

NBi

Page 23: Quadratic VLSI Placement

Pseudo pin and Pseudo net

Need to add forces to prevent cells from collapsing back

Done by adding pseudo pins and pseudo nets

Only diagonal and linear terms of the quadratic system need to be updated

Takes a single pass of O(n) time to regenerate matrix Q (which is common for both x and y problems)

Pseudo net

Additional Force

Pseudo pin

Target Position

Original Position

Pseudo net

Pseudopin

Page 24: Quadratic VLSI Placement

Iterative Local Refinement

Iteratively go through all the cells one by one For each cell, consider moving it in four directions by a certain

distance Compute a score for each direction based on

Half-perimeter wirelength (HPWL) reduction Cell density at the source and destination regions

Move in the direction with highest positive score (Do not move if no positive score)

Distance moved (H or V) is decreasing over iterations

Detailed placement is handledby the same heuristic

H H

V

V

Page 25: Quadratic VLSI Placement

Clique, Star and Hybrid Net Models

Runtime is proportional to # of non-zero entries in Q Each non-zero entry in Q corresponds to one 2-pin net Traditionally, placers model each multi-pin net by a clique Hybrid Net Model is a mix of Clique and Star Models

Star Node

Clique Model Star Model

Hybrid Model

# pins Net Model2 Clique3 Clique4 Star5 Star6 Star… …

Page 26: Quadratic VLSI Placement

Equivalence of Clique and Star Models

Lemma: By setting the net weights appropriately, clique and star net models are equivalent.

Proof: When star node is at equilibrium position, total forces on each cell are the same for clique and star net models.

Star Node

Weight = γWWeight = γW Weight = γ kWfor a k-pin netWeight = γ kWfor a k-pin net

Clique Model Star Model

Page 27: Quadratic VLSI Placement

Comparison

FastPlace is fast compared to Kraftwerk (based on published data) 20-25x faster

With cell shifting technique can converge in around 20 iterations.

KraftWerk may need hundreds of iterations to converge.

10% better in wirelength hybrid net model


Recommended