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Repetitive short-circuit measurement on SiC MOSFET

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I GSS monitoring during RSC First RSC test at 80%.E C gate oxyde failure in ~160SC Gate leakage current increase show gate degradation Key parameters changes Gate leakage current characterization Repetitive short-circuit measurement on SiC MOSFET ECSCRM 03/09/2018 Q. Molin 1,a* , M. Kanoun 2,b , C. Raynaud 3,c , H. Morel 3,d 1 Supergrid Institute, 21 rue Cyprian, Villeurbanne 69611 CEDEX, France 2 EDF R&D, Moret-sur-Loing 77818, France 3 Univ Lyon, INSA Lyon, CNRS, Ampere, F-69621, France a [email protected], b [email protected] , c [email protected], d [email protected] Up to 20 kV short -circuit test Devices under test : 1.7 kV 45 mΩ In order to perform repetitive short-circuit test, the critical energy needs to be evaluated V DS = 400 V I SC ≈ 450 A = 0 = 1.5 SuperGrid Institute, 23 Rue Cyprian, 69100 Villeurbanne - FRANCE Abstract Short circuit test bench overall description Critical energy estimation Conclusions Robustness study for the 1.7 kV SiC MOSFET is presented. After evaluation of the critical energy required for failure, devices were submitted to repetitive short-circuits conditions. Because the power switches experienced very stressful mode, the monitoring of key parameters is required to understand failures which in all occurrence are related to the gate oxide weakness. The strong impact of drain to source bias voltage on the critical energy during short-circuit mode is also investigated. Additionally, test bench and protocols are detailed. Capacitance bank Si IGBT power module DUT gate drive Current shunt SiC MOSFET under test Gate leakage current monitoring Drain to source voltage impact on critical energy Test protocol: 300SC by E SC steps E SC increased until failure When V DS is increased then the energy required to degrade the gate oxide is decreased SiC MOSFET short -circuit withstanding capacity is worrying. Once 80%.E C of a component is reached, around a few hundred are needed for gate failure If the 80%.V BR condition is respected for 1.7 kV MOSFET t sc can be approximated to ~3 μs There is some critical dispersion on critical energy 1,5 J < E C < 2 J Strict measurement protocol are needed Parameters Before RSC After 1000 RSC I GSS 39.4 pA >1 mA V th 2.86 V 2.98 V R DSon 40 mΩ 80.5 mΩ R g 1.95 Ω 19.8 Ω V BR 2.21 kV 2.21 kV
Transcript
Page 1: Repetitive short-circuit measurement on SiC MOSFET

IGSS monitoring during RSC

First RSC test at 80%.EC

gate oxyde failure in ~160SC

Gate leakage current increase show gate degradation

Key parameters changes

Gate leakage current characterization

Repetitive short-circuit measurement on SiC MOSFET

ECSCRM03/09/2018

Q. Molin1,a*, M. Kanoun2,b, C. Raynaud3,c, H. Morel3,d

1 Supergrid Institute, 21 rue Cyprian, Villeurbanne 69611 CEDEX, France

2 EDF R&D, Moret-sur-Loing 77818, France

3 Univ Lyon, INSA Lyon, CNRS, Ampere, F-69621, France

[email protected], [email protected],

[email protected], [email protected]

Up to 20 kV short-circuit test

Devices under test : 1.7 kV 45 mΩ

In order to perform repetitive short-circuit test, the criticalenergy needs to be evaluated

VDS = 400 V

ISC ≈ 450 A

𝐸𝐶 = 0𝑡𝑠𝑐 𝑉𝐷𝑆 ∙ 𝐼𝑆𝐶 ∙ 𝑑𝑡

𝐸𝐶 = 1.5 𝐽

SuperGrid Institute, 23 Rue Cyprian, 69100 Villeurbanne - FRANCE

Abstract

Short circuit test bench overall description Critical energy estimation

Conclusions

Robustness study for the 1.7 kV SiC MOSFET is presented. After evaluation of the critical energy required for failure,devices were submitted to repetitive short-circuits conditions. Because the power switches experienced very stressfulmode, the monitoring of key parameters is required to understand failures which in all occurrence are related to the gateoxide weakness. The strong impact of drain to source bias voltage on the critical energy during short-circuit mode is alsoinvestigated. Additionally, test bench and protocols are detailed.

Capacitance

bank Si IGBT power

module

DUT gate

drive

Current shunt

SiC MOSFET

under test

Gate leakage current monitoring Drain to source voltage impact on critical energy

Test protocol:

300SC by ESCsteps

ESC increaseduntil failure

When VDS is increased then the energy required to degrade the gate oxide is decreased

SiC MOSFET short-circuit withstanding capacity is worrying.

Once 80%.EC of a component is reached, around a few hundred are needed for gate failure

If the 80%.VBR condition is respected for 1.7 kV MOSFET

tsc can be approximated to ~3 µs

There is some critical dispersion on critical energy

1,5 J < EC < 2 J

Strict measurement protocol are needed

Parameters Before RSC After 1000 RSCIGSS 39.4 pA >1 mAVth 2.86 V 2.98 VRDSon 40 mΩ 80.5 mΩRg 1.95 Ω 19.8 ΩVBR 2.21 kV 2.21 kV

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