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RFIC DESIGN ELEN 351 Session4

Dr. Allen SweetJanuary 29, 2003

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Power Amplifier Classes Indicate Efficiency and Linearity

• Class A: Most linear, max efficiency is 50%• Class AB: linear, max efficiency is 60%• Class B: More nonlinear, max efficiency is

75%• Class C: Very nonlinear, max efficiency is

85%• Classes D, E, F: Switching modes, 85-95%

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Linearity Metrics

• Scaled Linearity = (OIP3 – P-1 dB)• Linear Efficiency = 10 LOG (OIP3/Pdc)• Adjacent Channel Power Ratio = (Main

Channel average power – Adjacent Channel average power)

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GaAs HBT Performance Expectations

• PAE: Matched/Feedback amps:45% to 65%, Darlington amps: 15% to 25%

• (OIP3 – P-1 dB): 10 dB to 20 dB• 10 LOG (OIP3/Pdc): 5 dB to 15 dB• ACPR: 50 dB to 65 dB

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Matching for Maximum Gain

Zl

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Smith Chart Display of S11 and S22 and Zl for Maximum Pout

Match for Gain Match for Power

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MESFET Power Amplifier Load Line Analysis

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Load Line Resistance CalculationWith no Restrictions on Voltage

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Load Line for a One Finger GaAs HBT Using the G.P Model

Bias Point

Bias Point

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Calculate HBT PA Load Line Resistance Based on Pout

• Assume the Requirement is for Pout=1 watt from a class A amplifier.

• Assume 50% conversion efficiency and Vcc=6.0 volts. Pdc=2 watts, and Ic=2watts/6 volts= 333 mA.

• The number of emitter fingers is N=333/10 = 33 fingers.

• Load Resistance = Rl = 580/33 = 17.5 Ohms

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Pure Class A Load Line Analysis

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Simulated Wave Forms for Pure Class A Operation

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Simulated Pin vs Pout for Pure Class A Operation

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Class AB Operation (Low DC Current)

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Class AB Current and Voltage Wave Forms

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Pin vs Pout for Class AB Operation

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Load Line Analysis for Low Voltage Class A Operation

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Current and Voltage Wave Forms for Low Voltage Operation

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Pin vs Pout for Low Voltage Operation

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Ways to Test an Amplifier’s Stability/Instability

• K factor: K>1.0 is Unconditionally stable, 0<K<1.0 is conditionally stable, and K<0 is Unstable.

• S11 or S22 greater than 1.0 (or positive if expressed in dB’s) is unstable.

• Stability circles (ADS element under Simulation-S parameter Palette) Show Unstable Impedance Regions.

• BE SURE TO TEST STABILITY OVER A WIDE RANGE OF FREQUENCIES.

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Circuit Elements which Enhance an Amplifier’s Stability

• Parallel or Series Feedback.• Place a series R-L network in shunt with the

amplifier’s input, to cure low frequency instabilities.

• Place a series R-C network in shunt with the amplifier’s input to cure high frequency instabilities.

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Amplifier Stability Analysis Demonstrating a Problem

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Improved Stability after Modifying Component Values

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Simulating Power, Linearity and DC with ADS Harmonic Balance • Use Harmonic Balance and a One Tone

Frequency Source to Simulate Pin vs Pout.• Use Harmonic Balance and an N Tone

Frequency Source to Simulate OIP3.• Use DC Control Icon to Annotate DC

conditions.

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ADS Harmonic Balance Schematic For Simulating Pin vs

Pout

Name output node on Schematic Vout

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ADS Display Trace Expression for Pin vs Pout

Choose dBm,Not dB for power

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ADS Harmonic Balance Schematic for Simulating OIP3

Note: be sure to Name the output Node vout

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ADS Display Trace for OIP3 Simulations

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Types of GaAs HBT PAs

• Darlington: Simple, Inherently Stable, Medium Power, 15% to 25% Efficient, Very Broad Bandwidth. Minimum off chip components

• Feedback: Simple, High Power, High Efficiency (50% to 60%), Some off chip Components Required.

• Balanced: +3 dB Power Combining, Inherently Good in/out matches, Many off chip components.

• Push Pull: +3 dB Power Combining, Natural Impedance Transformation for matching. Off chip

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Darlington Amplifiers

• Simple Topology: Two Transistors, 4 Resistors, No on chip Capacitors, No on chip Inductors.

• Flat, Broadband Gain Response Extends down to D.C. and Rolls off at a High Corner Frequency determined by the device sizes. Inherently Stable.

• Power and OIP3 trade off with corner Frequency.• Device Area determines Gain and Power.• Gain to 20 dB, P-1 db to +25 dBm, OIP3 to +45

dBm, but not all at once.• Use for Low and Medium Power Stages.

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Darlington Amplifier Topology

IN

OUT

NormallyZero Ohms

Vbe for both Transistors must beAbout 1.4 volts

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Darlington Amplifier Frequency Response

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Homework #3: A Darlington Amplifier with Layout Parasitic

Elements

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Darlington Amplifier DC Simulation

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Menu Pick for DC Annotation

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Blow up of Darlington Circuit

Input PadOutputPad

R1

R2R3

R5

EmitterBase Line

Collector lineBase Line Q1

Q2

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Darlington Amplifier Simulated Performance

Peaking is causedBy transmission linesIn the transistors bases

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Darlington Schematic for Simulating OIP3

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Darlington OIP3 Simulation

dBm

(OIP3 – P-1)= 10 dB

10LOG(OIP3/Pdc)=5 dB

Linearity Metrics:

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Darlington Schematic for Simulating Pin vs Pout

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Simulated Pin vs Pout for the Darlington Amplifier

P-1 dB PAE=21 %

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Darlington Amplifier Layout

W=50 microns Resistors haveA Resistance in Ohms equal toTheir length in microns

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Layout Detail 1M1 to M2 VIA

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Layout Detail 2M1 to M2 VIAS

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Feedback Amplifiers

• Highest Power, Efficiency, and Linearity.• Feedback promotes Stability and Suppresses

Harmonics and Spurious signal.• Well matched over Narrow Band Segments only.• Output Matching is done off chip to reduce losses

at the high power side of the Amplifier• PAE up to 60%.• P-1 dB up to +32 dBm• OIP3 up to +50 dBm

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Feedback Amplifier Topology with Resistive Base Bias

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Feedback Amplifier Topology with Current Mirror Base Bias for Improved Temp Stability

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Layout of a Large (A=24) Transistor

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Ballast Resistors in Large Transistors

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Balanced Amplifiers

• Power Combine any two Identical Amplifiers to Double their Output Power.

• Excellent Broadband Match, no matter how poorly the individual Amplifiers are Matched.

• Many off chip components, some are Large.

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Balanced Amplifier Topology

Reflections

Reflections

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Push Pull Amplifiers

• Power Combine any two Identical Amplifiers to Double their Power output.

• Push Pull Topology uses Baluns or Transformers that provide a natural Impedance Transformation for Matching. A 2:1 Impedance ratio Transformer provides a 4:1 Matching Impedance Ratio.

• The Virtual Ground Along the Amplifier’s Center line can simplify layout by eliminating the need for some Substrate Via Grounds.

• Many Off Chip Components, some are Large.

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Push Pull Amplifier Topology

Virtual ground point

N:1 N:150/2N

50/2N

50/2N

50/2N