IC DEVICE TECHNOLOGY OVERVIEW There are a variety of major manufacturing process technologies (Figure 4-1) used in design and fabrication of silicon-based integrated circuits (ICs). These include metal-oxide-semiconductor (MOS), bipolar, and combined bipolar and complementary-MOS (BiCMOS). While silicon-based processing dominates in semiconductor manufacturing, gallium arsenide (GaAs), a compound- semiconductor material, is a niche alternative to silicon for some applications. INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-1 4 IC DEVICE AND PACKAGING TECHNOLOGY TRENDS IC Manufacturing Process Technologies 1997 Status Obsolete Virtually obsolete Mainstream MOS technology, with continued growth. Fastest silicon-based process, but losing to GaAs. Virtually obsolete. Virtually obsolete. Virtually obsolete, having lost to MOS ASICs designs. Mainstream analog technology, but competition from CMOS, and GaAs. Offers both MOS and bipolar advantages, but slipping from high cost/complexity. Still niche technology, but future potential. — <1 86 <1 — <1 8 5 1 11218W Source: ICE Marketshare (Percent of Total Dollars) 1970 1980 5 37 10 3 8 13 24 — — — <1 69 <1 <1 1 11 18 1 2002 (FCST) 1997 (EST) 1990 — 10 65 3 2 4 15 1 <1 MOS (total): PMOS NMOS/HMOS CMOS Bipolar (total): ECL TTL S/LS TTL LINEAR BiCMOS: GaAs: 31 2 2 3 29 7 26 — — 35 52 75 ~69 ~87 65 48 24 ~12 ~10 Figure 4-1. Market Share Overview of IC Manufacturing Process Technologies
Transcript
IC DEVICE TECHNOLOGY OVERVIEW
There are a variety of major manufacturing process technologies (Figure 4-1) used in design andfabrication of silicon-based integrated circuits (ICs). These include metal-oxide-semiconductor(MOS), bipolar, and combined bipolar and complementary-MOS (BiCMOS). While silicon-basedprocessing dominates in semiconductor manufacturing, gallium arsenide (GaAs), a compound-semiconductor material, is a niche alternative to silicon for some applications.
INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-1
4 IC DEVICE AND PACKAGING TECHNOLOGY TRENDS
ICManufacturing
ProcessTechnologies
1997 Status
Obsolete
Virtually obsolete
Mainstream MOS technology, with continuedgrowth.
Fastest silicon-based process, but losing toGaAs. Virtually obsolete.
Virtually obsolete.
Virtually obsolete, having lost to MOS ASICsdesigns.
Mainstream analog technology, but competition from CMOS, and GaAs.
Offers both MOS and bipolar advantages, butslipping from high cost/complexity.
Still niche technology, but future potential.
—
<1
86
<1
—
<1
8
5
1
11218WSource: ICE
Marketshare(Percent of Total Dollars)
1970 1980
5
37
10
3
8
13
24
—
—
—
<1
69
<1
<1
1
11
18
1
2002(FCST)
1997(EST)
1990
—
10
65
3
2
4
15
1
<1
MOS (total):
PMOS
NMOS/HMOS
CMOS
Bipolar (total):
ECL
TTL
S/LS TTL
LINEAR
BiCMOS:
GaAs:
31
2
2
3
29
7
26
—
—
35 52 75 ~69 ~87
65 48 24 ~12 ~10
Figure 4-1. Market Share Overview of IC Manufacturing Process Technologies
Within MOS and bipolar manufacturing process technologies, device design variations haveemerged and declined as IC applications and complexities have changed. Historically, back in1970 bipolar was the major technology of choice; it was used for almost 66 percent of the total ICmarket. By 1980, that share had fallen to less than 50 percent. Last year, in 1997, bipolar ICsaccounted for less than 14 percent of the IC dollar volume shipped.
Interestingly, while bipolar ICs rep-resent a small proportion of today’sIC market, they still represent nearlyhalf the ICs (i.e., unit volume)shipped in 1997 (Figure 4-2). Inaddition, bipolar linear technology,which is the mainstream technologyfor analog ICs, easily accounts forthe largest number of IC unitsshipped in all technology categories.
BiCMOS offers IC designers bothbipolar and CMOS advantages; ICscan be designed with the bestdevices for each part of the circuit.However, the process complexity ofBiCMOS, which requires morewafer-fabrication processing steps,has kept it from rising in the semi-conductor industry and is the reasonbehind its anticipated decline.
From 1997 to 2002, ICE forecasts that BiCMOS ICs will show a –3 percent cumulative-averageannual growth rate (CAGR), declining from its current level at $18.9 billion to $16.1 billion or onlyfive percent of the forecasted 2002 IC market. Specifically, this decline is a result of one manufac-turer, Intel’s plan to convert its Pentium and Pentium Pro microprocessors from BiCMOS toCMOS technology.
The emphasis in 1998 is still on CMOS technology, as it has been throughout the 1990s. ICE esti-mates that CMOS-based ICs will represent 69 percent of the final IC market for 1997 (Figure 4-3).By the year 2002, the market share forecast for CMOS ICs will likely increase to 86 percent of thetotal IC dollar volume.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION4-2
199757.3B(EST)
BipolarAnalog
41% Bipolar47%
MOS*53%
MOSLogic24%
MOSMemory
13%
MOSMicro12%
MOS/BiMOSAnalog
4%
BipolarDigital
6%
* Includes BiCMOSSource: ICE 21390B
Figure 4-2. MOS and Bipolar IC Unit Volumes
No technology of the past has dominated the IC market like CMOS does today; it is the technol-ogy behind news-grabbing multi-million transistor ICs and the systems that use them. The wide-spread use of CMOS comes from the combination of high density (i.e., sub-micron circuitfeatures), low power dissipation, and scalability. The latter gives a manufacturer the capability toreduce the size of a given IC design one or more times thereby enhancing manufacturing produc-tivity and corporate profitability.
The dominance of CMOS, at the expense of other IC design and process technologies, cannot beignored (Figure 4-4). However, as it first did in 1996, in 1997 the market share of CMOS ICsdropped from its previous year value. This is not an indicator of declining CMOS applications,but is due to continuing lower prices for MOS memories, dynamic random access memories(DRAMs) in particular. It can also be attributed to a growing BiCMOS IC market, a result of thestrength in demand for BiCMOS-based Pentium microprocessors, prior to Intel’s planned switchto CMOS. Clearly, the dominance of CMOS ICs will turn its market share up again in 1998 as itclimbs to 86% by 2002.
While physics dictates that CMOS technology is inherently slower than the emitter-coupled logic(ECL) bipolar technology, for example, so much research and development has gone into CMOSdesign and process technologies, that today its speed and output drive capabilities rival that ofsome bipolar devices (Figure 4-5).
All IC manufacturing processes go through a bell-curve life cycle (Figure 4-6). What is interestingabout CMOS technology is that it has been at the maturity stage since the mid-1980s with littlemovement. ICE expects that CMOS will still be in its maturity stage well into the twenty-first cen-tury. Through the end 1997, there was no new technology that showed the potential to dethroneCMOS as the mainstream IC process in the foreseeable future. Cost effectiveness, steadily increas-ing performance, and consistently high levels of investment in research and development by ICmanufacturers will keep CMOS the mainstream technology throughout the 1990s and beyond.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-3
1997 (EST)$127.2B
2002 (FCST)$349.5B
CMOS 69% CMOS 86%
Bipolar12%
Bipolar 8%
Other19%
Other 6%
20282ESource: ICE
Figure 4-3. CMOS IC Process Technology Dominance
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION4-4
100
90
80
70
60
50
40
30
20
10
01982
$10.2B1987
$29.0B
12%
41%
2%
22%
19%
4%
39%
24%
<1%
20%
12%
4%
<1%
ECL
TTL ANDOTHER
BIPOLARANALOG
PMOS
NMOS
CMOS
PE
RC
EN
T
YEAR12070VSource: ICE
1996$117.9B
1997$127.2B
(EST)
2002$349.5B(FCST)
1% GaAs AND OTHER
MOS
BIPOLAR
86%
<1%
8%
<1% ECL<1%TTL<1%
1%1%
BiCMOS
5%
18%
16%
69%71%
<1%
11%11%
1%
<1%
Figure 4-4. 1982-2002 IC Technology Market Trends ($)
Figure 4-7. 1982-2002 MOS (Excluding BiCMOS) Technology Market Trends
It is common industry knowledge that n-channel MOS (NMOS) replaced the slower and morepower-hungry p-channel MOS (PMOS) technology in the 1970s, and CMOS supplanted NMOS inthe 1980s. Today, as the data show, CMOS represents basically all of the total MOS market.Historically, CMOS became the technology of choice for MOS memory as memory densityreached and surpassed 1 megabit (1M). In addition, the swelling complexity and density of otherIC types like microprocessors and application specific ICs (ASICs) require the scalability and lowpower consumption benefits of CMOS. All 1M and denser DRAMs have thus far been producedusing CMOS technology.
The inherent advantages of CMOS include:
• Design and process experience.• Available from numerous device manufacturers.• Lowest price per function compared to other technologies at the same geometry.• Low power consumption.• High scalability with lithography process evolution.• Relatively good noise immunity and soft error protection.• Low threshold bias sensitivity.• Design simplicity and relatively easy layout, especially for ASICs.• Capability for lower power analog and digital circuitry on the same chip.
ICE projects that CMOS will dominate the semiconductor industry well into the future. Indeed,CMOS seems to have the life it needs to continue evolving to meet the majority of IC performancedemands. We have already seen a decline from conventional 5V power supply to 3.3V, and lower,on devices with 0.35 µm geometries and gate oxides less than 100Å (Figure 4-9). Now, with theindustry moving to feature sizes of 0.25µm and below, a 3.3V power supply is becoming imprac-tical and designers are looking at 2.5V or even 1.8V (Figure 4-10).
The trend with CMOS supply voltage is a good illustration of the degree of synergy that has beenrequired over the past few years between system designers and IC designers. In the transitionfrom 5V to lower voltage systems, system designers have been using several voltages on the sameprinted circuit board (Figure 4-11); this trend peaked in 1996 and is now declining. Still, however,
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION4-6
Technology
NMOS and PMOS
CMOS
Total
7,350
11,050
18,400
1987($M)
475
83,395
83,870
150
299,591
299,741
–23
25
20
1987 - 2002CAGR
(Percent)
2002($M,
FCST)
16811NSource: ICE
1997($M, EST)
1996($M)
445
87,270
87,715
Figure 4-8. MOS Technology Market Trends (1987-2002)
semiconductor manufacturer Lucent Technologies, for example, offers a standard cell library thatallows the user to mix and match 5V and 3V cells on the same chip. Other companies that are con-tinuing to help bridge the 5V to lower-voltage gap with mixed-voltage ICs include Oki, TexasInstruments (TI), Toshiba, Atmel, and Symbios Logic.
For 1998, the transition to voltage supplies other that 5V and the decline of mixed voltage systemscontinues. It is estimated that most of the 2002 IC market will be served by 3.3V; already all 64MDRAMs are designed for 3.3V power supply.
One of the drawbacks to moving to lower voltage levels is the difficulty in improving performanceat the same rate as was accomplished using 5V. As shown in Figure 4-12, low-voltage technologyperformance is expected to double every four generations as opposed to every two generationswhen using 5V. Figure 4-13 looks at some of the driving factors affecting the move to low-voltagedevice technology.
Even in 1997, the first ICs based on ≤0.25µm CMOS technology were coming to market, about ayear earlier than expected. Figure 4-14 compares several microprocessor-oriented 0.25µmprocesses. The routing index shown in the figure was calculated by MicroDesign Resources in anattempt to capture the circuit density of the processes. This index and the tabulated values sug-gest that IBM’s CMOS-6X and TI’s C07 offer the best circuit density, but IBM’s process is morecostly because of its additional metal layer and local interconnect.
Lacks industry infrastructure andvolume support base
DevicePhysics
HighPerformance
PortableProducts
20287ASource: Motorola
Figure 4-13. Voltage Reduction Drivers
The development of next-genera-tion 0.18µm CMOS technology isalready well underway withvolume production of ICs with0.18µm geometries (drawn gatelength) expected to start as early as1999, two years earlier thanexpected. TI released details of a0.18µm CMOS logic process inJune, 1997. Characteristics of theprocess are shown in Figure 4-15.TI believes potential applicationsfor the process include single-chipdigital radios and optical commu-nications chips.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION4-10
AMD
CS-44
K6+
2H97
2.5V
3.3V
0.25µm
0.18µm
n/a
5 metal
yes
yes
0.88µm
0.88µm
0.88µm
1.13µm
3.0µm
n/a
0.60µm2
$4.0
Digital
CMOS-7
21264+
1H98
1.8V
3.3V
0.25µm
0.16µm
45Å
6 metal
no
yes
0.84µm
0.84µm
1.7µm
1.7µm
1.7µm
11.5µm2
1.1µm2
$3.5
Fujitsu
CS-70
n/a
2H97
2.5V
3.3V
0.24µm
0.18µm
55Å
5 metal
yes
yes
0.9µm
0.9µm
0.9µm
0.9µm
2.7µm
n/a
0.62µm2
$4.0
PPC 60x+
2H97
1.8V
3.3V
<0.25µm
n/a
40Å
6 metal
yes
yes
0.7µm
0.9µm
0.9µm
0.9µm
0.9µm
8.6µm2
0.53µm2
$4.7
n/a
1H98
2.5V
3.3V
0.25µm
0.20µm
65Å
4 metal
no
yes
0.94µm
1.1µm
1.1µm
1.1µm
1.4µm
11.2µm2
1.0µm2
$3.6
n/a
3Q97
1.8V
3.3V
0.21µm
0.17µm
40Å
5 metal
no
yes
0.85µm
0.85µm
0.85µm
0.85µm
2.5µm
10.5µm2
0.56µm2
$4.1
Deschutes
3Q97
1.8V
2.5V
<0.25µm
n/a
45Å
5 metal
no
yes
0.64µm
0.93µm
0.93µm
1.6µm
2.6µm
10.3µm2
0.67µm2
$4.0
IBM*
CMOS-6X
IDT
CEMOS-10+Intel
P856
TI
C07
Vendor
Process Name
Example Product
First Production
Supply Voltage
I/O Voltage (Max)
Gate length (Drawn)
Channel length (Effective)
Gate Oxide Thickness
Number of Metal layers
Local Interconnect?
Stacked Vias?
M1 Contacted Pitch
M2 Contacted Pitch
M3 Contacted Pitch
M4 Contacted Pitch
M5 Contacted Pitch
SRAM Cell Size
Routing Index
Wafer Cost Index
Source: MicroDesign Resources 21747A
* Motorola's PPC4 is similar to CMOS-6X but may have smaller gates. + indicates shrink version.
Figure 4-14. A Look at Some 0.25µm Processes
Gate Length
Drawn
Effective
Inverter Delay
Power Consumption
Supply Voltage
Cutoff Frequency
pFET
nFET
Number of Metal Layers
Gate Oxide Thickness
Other Features
0.18µm
0.13µm
25ps/stage
11.6nW/µm
1.8V
40GHz
72GHz
6
4nm
A new low-k insulating material,low-resistivity metal, shallowtrench isolation, and a sputteredtungsten-silicide step
Source: EETimes/TI 22747
Figure 4-15. A Peek at TI’s Next-Generation 0.18µm Process Technology
While 0.1µm CMOS technology is not expected to be in widespread use before 2000, many largeIC producers with advanced research labs are already releasing data on such devices. Figure 4-16shows Fujitsu’s preliminary 0.1µm CMOS process parameters.
Bipolar ICs
Figures 4-17 and 4-18 show the bipolar IC market in dollars. Although the bipolar segment isshrinking in IC market share (from an estimated 11 percent in 1997 to about eight percent in 2002),the total bipolar dollar volume is forecast to display a 13 percent CAGR from 1997 to 2002.
Bipolar IC technology has survived along side the dominance of CMOS IC technology to remainstrong on two fronts: for analog ICs and for very high speed driver ICs. Both these product areasexploit the inherent capabilities of the bipolar transistor.
Bipolar technology remains popular in analog ICs because of the better gain and power handlingcapabilities of the bipolar transistor, as well as the fact that bipolar analog chips tend to be morerugged than their CMOS counterparts.
For digital applications, bipolar ICs still find design wins in very high speed applications, such ascommunications and mainframe computers. In other digital applications, on the other hand,bipolar technology has lost most of the advantages it once had over CMOS. Bipolar ICs consumea great deal of power per logic function, so when the highest absolute speed is not required,CMOS is the better solution. Figure 4-19 shows that the market for digital bipolar ICs is decliningin each of the product areas listed.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-11
NMOSParameter PMOS
Starting Material
Well
Isolation
Channel Implant
Gate Oxide
Gate Stack
Shallow Junction Implant
Spacer
Deep Junction Implant
Anneal
10Ωcm p-type (100)
Twin Well
350nm LOCOS
B+, 40keV, 7 x 1012
3.9nm (800°C)
Poly-Si 160nm + SiO2 50nm
As+, 10keV, 4 x 1013
SiN 60nm
As+, 30keV, 3.2 x 1015
850°C, 5 minutes
10Ωcm p-type (100)
Twin Well
350nm LOCOS
As+, 180keV, 5 x 1012
3.9nm (800°C)
Poly-Si 160nm + SiO2 50nm
BF2+, 5keV, 1 x 1014
SiN 60nm
BF2+, 20keV, 5 x 1015
850°C, 5 minutes
Source: Fujitsu/IEDM 19214A
Figure 4-16. Process Parameters of 0.1µm CMOS
For digital applications, inherently, bipolar ECL devices are very uniform, stable, and generatelow noise. Also, ECL requires only a 1V swing in 3-4ns compared with a typical bipolar transis-tor-transistor logic (TTL) chip that requires a 5V swing in the same time frame. ECL-based ICsinclude gate array ASICs, standard and special purpose logic devices, and static random accessmemory (SRAM) ICs (Figure 4-20).
Japanese semiconductor manufacturers have traditionally had the largest ECL IC market shareprimarily because of their emphasis on mainframe computers. However, computer manufactur-ers NEC and Fujitsu have revamped their mainframe lines to use CMOS ICs, and Hitachi hasmoved to BiCMOS parts.
The movement to using other technologies besides ECL for high-speed systems is especially dev-astating to the large military ECL IC market. The lackluster military IC market coupled with theincreasing use of CMOS, GaAs, and BiCMOS ICs will heavily contribute to the declining ECL ICindustry through the end of the 1990s.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-13
1996($M)
1997($M, EST)
2002($M, FCST)
1996 - 2002CAGR
(Percent)Product
General Purpose Logic
Special Purpose Logic
Gate Array/Std. Cell
MPU/MCU/MPR
FPL
Memory
Total
895
365
510
10
65
160
2,005
785
230
460
5
40
130
1,650
438
90
245
—
11
54
838
–11
–21
–12
–100
–26
–17
–14
18881HSource: ICE
Figure 4-19. Digital Bipolar IC Market
ASIC66%
Logic*15%
Memory19%
1992$1,320M
Memory13%
ASIC49%
Logic*38%
2002(FCST)$375M
ASIC50%Logic*
35%
Memory15%
1997(EST)$660M
*Includes General and Special Purpose LogicSource: ICE 21085D
Figure 4-20. ECL IC Market by Product Group
BiCMOS ICs
BiCMOS technology has long been thought of as a high-speed replacement for pure CMOSbecause it offers a performance edge by implementing both CMOS and bipolar transistors on thesame chip. Through the selective use of CMOS and bipolar circuitry, high-performance paths canbe created with bipolar, while lower-performance, high-density paths can be created with CMOSgates. More recently though, the growth in demand for mixed-signal ICs has been driving greateruse of BiCMOS technology.
BiCMOS architecture that consists of a small percentage of bipolar transistors is called CMOS-based. For this architecture, non-critical paths on the majority of the chip consist of CMOS gates,while bipolar transistors are used mainly for driving long metal lines and as output buffers forcritical paths. This is the most common type of BiCMOS technology.
Bipolar-based BiCMOS IC architecture consists of predominantly bipolar transistors with CMOStransistors available for the implementation of large storage elements. The resulting IC offersexcellent performance and density with a high level of programmability.
The main disadvantage of BiCMOS is the manufacturing cost penalty created by the complicatedprocess of building both bipolar and MOS transistors into a single IC. It is partly because of thisincreased complexity that Intel is moving its Pentium microprocessor (MPU) series from a 20-mask BiCMOS process to a 16-mask pure CMOS process technology. Another reason stated by thecompany is that while bipolar transistors provide some performance boost at 3.3V, the gain isinsignificant at 2.5V and below.
Because the performance advantage of BiCMOS decreases with lower voltage levels, the futureof BiCMOS in the systems of the late-1990s depends on the ability to economically produce spe-cialized BiCMOS processes. For example, Motorola has a specialized BiCMOS process that tar-gets ASIC, very high-speed, and low-voltage applications. The supply voltage versus 0.5µmBiCMOS manufacturing complexity issues will especially challenge the BiCMOS producers inthe late-1990s.
As shown in Figure 4-21, the BiCMOS market was led by microcomponent (i.e., Pentium like)products in 1997. The total BiCMOS IC market is expected to decline at a three percent averageannual rate from 1997-2002, and represent only five percent of the total IC market in 2002. Thisdecline is due to Intel’s plan to move its advanced microprocessor products from BiCMOS toCMOS in the late 1990s. Intel’s first pure-CMOS Pentiums started to appear in 1997, as the com-pany moved into a 0.28µm process. In summary, the timing and completeness of Intel’s conver-sion will have a tremendous impact on the total BiCMOS market figures in the late 1990s.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION4-14
Besides the Pentium-dominated microcomponent area, the analog-mixed-signal IC segment is astrong market for BiCMOS ICs. In fact, by the turn of the century, analog-mixed-signal ICs areexpected to take over the top market share position in the BiCMOS market. BiCMOS is also pop-ular for very high-speed SRAMs, with the access times of some BiCMOS SRAMs stated to be halfthose of most CMOS SRAMs of the same density. Furthermore, ECL SRAMs can’t match BiCMOSdensities.
As shown in Figure 4-22, Intel is by far the largest producer of BiCMOS ICs. Two European semi-conductor manufacturers—Philips and SGS-Thomson—are also heavily involved in BiCMOStechnology, with the focus of both being on analog and mixed-signal ICs. Motorola’s BiCMOS ICsencompass a variety of products, including memory, ASIC, logic, and analog ICs.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-15
Gate Arrays2%
SRAMs2%
Analog/Mixed Signal
15%
StandardCell 3%
StandardLogic
1%
Other<1%
1997 (EST)$23,300M
Microcomponents77%
GateArrays
4%SRAMs
6%
Analog/Mixed Signal
63%Standard Cell17%
StandardLogic
3% Other1%
2002 (FCST)$16,100M
13643SSource: ICE
Microcomponents6%
Figure 4-21. Worldwide BiCMOS Market
Intel
SGS-Thomson
Philips
Texas Instruments*
Motorola
Fujitsu
NEC
Analog Devices
Alcatel-Mietec
Others
Total
14,160
1,390
1,100
370
350
160
160
130
110
950
18,880
Company 1996 Sales ($M)
Source: ICE 21084D
*Acquired the major BiCMOS IC supplier, Silicon Systems, in 1996.
Figure 4-22. Major BiCMOS IC Suppliers
The following are the past-year’s significant BiCMOS business and technology announcements:
• Exponential Technology canceled its PowerPC-compatible X704 BiCMOS microprocessorprogram and closed its main office in San Jose. The super high performance chip design wascomplete and ready to begin shipments at speeds of 410MHz, but, the primary customer forthe part, Apple Computer, withdrew its plans to ship X704-based systems. Apple reportedlydecided to stick with the multisourced PowerPC microprocessor that fits into standard sys-tems rather than modifying its products to deal with the extra heat and unique socket of thesingle-sourced Exponential microprocessor.
• Micro Linear announced the addition of four new products to its family of 10Base-FLEthernet transceiver products that are implemented in an advanced BiCMOS process. Thecompany claims that the use of a BiCMOS process results in a reduction in power dissipa-tion of up to 35 percent.
• NEC introduced four 200MHz 4M synchronous SRAMs implemented in a 0.35µm BiCMOSprocess. The SRAMs are intended for use as cache memory for reduced instruction set com-puting (RISC) processors in high-end workstations.
Gallium-Arsenide ICs
Gallium-arsenide (GaAs) compound-semiconductor material has an inherent speed advantageover silicon. However, for years the relative high cost of GaAs wafers, problems with breakageduring processing (the material is very brittle), and the higher defect density with the corre-sponding lower device yields have kept market penetration lower than anticipated. Today, duemainly to the booming telecommunications end-use market over the past several years, GaAs ICmanufacturers are experiencing healthy double digit market growth.
GaAs technology continues to advance by shrinking device geometries and using more industrystandard low-cost packaging, and through GaAs IC manufacturers developing a better under-standing of how to work with this compound semiconductor material. All these factor continueto help make GaAs ICs approach cost competitiveness with silicon.
The total GaAs market (excluding development funding) is forecast to have a 1997-2002 CAGR of27 percent, growing to about $2.7 billion in 2002 (Figure 4-23). As also shown in the figure, growthin the demand for analog GaAs ICs is expected to significantly outpace that for digital GaAs ICsinto the next century, as it has over the past years. Analog ICs represented about 72 percent of theGaAs IC market in 1997, and that share is expected to increase to 83 percent by 2002.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION4-16
Figure 4-24 shows the GaAs IC market by end-use market. Clearly, the current growth of GaAssemiconductor technology is a direct result of telecommunications applications. Some of today’smost attractive market areas for GaAs technology are cellular phones, digital personal communi-cations systems, local networks, satellites, broad-band tuners, automotive sensors, and sophisti-cated space systems. High-speed computing and fiber-optic applications may offer substantialvolumes for high-performance GaAs devices as well. Several applications for analog GaAs ICsare shown in Figure 4-25, while digital GaAs IC applications are shown in Figure 4-26.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-17
0
200
400
600
800
1,000
1,200
1,400
1,600
1,800
2,000
2,200
2,400
2,600
2,800
2002200120001999199819971996199519941993
Development Funding
Digital IC Sales
Analog IC Sales
100
240
435
90
395
520
395
14055
590
60
500
160
720
60
885
640
185 20
1,055
820
21520 20 20 20
1,330
1,055
255
1,690
1,365
305
Year
Mill
ion
s o
f D
olla
rs
*Includes development funding.17134KSource: ICE
2,160
1,775
365
2,765
2,295
45095 120
Figure 4-23. Worldwide GaAs IC Merchant Market* Forecast
1997 (EST)$825M
Military/Aerospace
17%
Telecom56%
Other 6%
Computer13%
Consumer8%
2002 (FCST)$2,745M
Computer10%
Consumer9%
Other 4%
Telecom68%
Military/Aerospace
9%
13329QSource: ICE*Not including development funding.
Figure 4-24. Total GaAs IC Market* by End Use
Historically, at first the military and aerospace industries were expected to provide a large marketfor GaAs technology, since customers in those areas would likely pay the higher prices for GaAsICs to bypass silicon’s speed limits in microwave communications and radar. However, steepgovernment spending cuts on defense put a damper on that expectation. Then, GaAs wasexpected to make next-generation supercomputers lightning fast, allowing the technology tofinally shed its niche-market image. But that expectation faded too because advances in siliconallowed multiple-silicon-chip systems to do it, for less. In recent years, the booming market forcommunications equipment has led to the commercial success of GaAs IC technology.
High-volume use of analog GaAs ICs in 2.4GHz and higher performance wireless communica-tions is almost guaranteed. At speeds below 500 to 800MHz, silicon is almost always the betterchoice. However, beginning at 800 to 900MHz and above, the contest is much closer, and above2.4GHz, GaAs devices are almost always superior. GaAs also offers comparable or better low-noise performance, low-voltage operation, and better system level cost and performance begin-ning in the gigahertz range.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION4-18
MobileCommunications
SatelliteReceivers
Fiber-OpticCommunications
Wireless DataCommunications
• Cellular Telephones
• Cordless Telephones
• Personal Communications Networks
• Microwave Radio Links
• Global Positioning System
• Very Small Aperture Terminals
• Mobile Satellite Systems
• Fixed Satellite Systems
• Long-Haul
• LANs
• WANs
• Local Loop
• Wireless LANs
• WANs
• Pagers
Source: Epitaxial Products International 21749
Figure 4-25. Communications Applications for GaAs Analog ICs
Figure 4-26. Primary Applications for Digital GaAs ICs
High Speed Telecommunications:
• DEMUX, MUX, high-speed logic paths, decision circuits, and switching.
• Require high-speed, low power for SONET, SDW, ATM, and ISDN (up to 2.5GHz).
Data Telecommunications:
• High-speed serial data communications between mainframes, servers, workstations, and peripherals.
• Standards requiring GaAs performance include HiPPI, FDDI, SCI, ESCON, and FCS.
Automatic Test Equipment:
• Replaces ECL in applications requiring low power, lower cost, and improved performance.
High Speed Computing:
• Collapse of Cray Computer was big set back.
• Some major players still looking at GaAs, including: Fujitsu, HP, Unisys, ARPA (US), and IBM.
Source: Epitaxial Products International 21750
Currently the GaAs IC industry is dominated by planar-type structured circuits, so-called junctionfield effect transistor (JFET) and metal semiconductor FET (MESFET) technologies. But, het-erostructure-type circuits, such as heterojunction bipolar transistor (HBT), high-electron-mobilitytransistor (HEMT), and pseudomorphic HEMT (PHEMT) ICs are gaining wider acceptance. HBTsand HEMTs are generally considered more efficient than conventional MESFETs, especially athigh frequencies, but are more difficult and expensive to manufacture. HBTs and HEMTs are notexpected to replace MESFETs, but will be widely used in emerging high-frequency applications.
GaAs MOSFET technology is highly desirable because it could give gallium-arsenide technologythe same low power and high density capabilities enabled by silicon-based CMOS technology. Ingeneral, the impurity and poor quality of gallium oxides have been the stumbling blocks for GaAsMOSFETs. Work in 1996 at Bell Labs disclosed a special technique for depositing a special formu-lation of gallium oxide as the gate dielectric on a GaAs semi-insulating substrate to fabricate bothp-channel and n-channel MOSFETs (Figure 4-27). This is promising work that could accelerateGaAs into what are otherwise still silicon-dominated applications, but there is still much morework to be done before commercial products can be realized.
Because of strong GaAs IC sales into communications applications, the list of major GaAs manu-facturers continues to show strong growth in sales (Figure 4-28).
The healthy market for GaAs manufacturers is also indicated by their continued capacity expan-sions. For example, Vitesse Semiconductor is building a new $75 million 150mm GaAs wafer fab-rication facility in Colorado Springs, Colorado, which is slated for completion in the second halfof 1998. And, previously fabless RF Micro Devices is building its first 100mm GaAs wafer fabri-cation facility in Greensboro, North Carolina, with a start date in the first quarter of 1998.
The following are the past-year’s significant GaAs business and technology announcements:
• TriQuint unveiled a new GaAs process technology for highly integrated RF front ends.Integrating enhancement and depletion-mode MESFETs, power MESFETs, and three layersof metal interconnect, the TQTRx 0.6µm process allows designers to combine transmit andreceive circuitry on the same chip.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-19
DrainSource
P+ P+P-P-
Oxide (Ga2O3)
Gate
Source: Electronic News 22720
Figure 4-27. P-Channel GaAs MOSFET Fabricated by Bell Labs
• In an attempt to keep up with shorter product design cycles, Fujitsu revealed plans to con-solidate all its compound semiconductor businesses, from development to sales, in one unitat its production subsidiary, Fujitsu Quantum Devices, Yamanashi, Japan.
• Vitesse entered the standard cell ASIC business with the introduction of its SLX family of prod-ucts. The SLX ICs are based on Vitesse’s 0.4µm, four-layer-metal GaAs process and feature15,000-220,000 raw gates (60-70 percent usable), 87 to 187 I/Os, 100ps worst-case delay, andadvanced power management circuitry that powers down inactive portions of the chip.
• Anadigics introduced a dual-mode, dual-band amplifier that allows designers of digital cel-lular handsets to switch between 800MHz AMPS/DAMPS and 1,900MHz PCS operation.The chip is the first in a planned line of devices that the company intends to manufacture toaddress the issue of switching between the 18 or so existing standards in the cellular market.
Silicon-Germanium ICs
As semiconductor manufacturers struggle to put more transistors on each chip and increase cir-cuit speed, the physical and electrical limitations of silicon become a major concern. For years, itwas thought that GaAs would become the new wafer material of choice. However, even thoughthe GaAs IC market is forecast to grow strongly through the end of the decade, it will still con-tinue to represent only a very small percentage of the total IC market.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION4-20
18111KSource: ICE
CompanyAnalog Digital Total
1996 Sales* ($M)
Fujitsu
Anadigics
TriQuint
Vitesse
TI
Rockwell
Oki
Pacific Monolithics
UMS**
NEC
Others
Total
65
66
29
2
42
28
29
30
25
25
159
500
35
—
31
57
3
7
4
—
—
—
23
160
100
66
60
59
45
35
33
30
25
25
182
660
Not including development funding.United Monolithic Semiconductors (UMS) is an independent joint ventureof Thomson-CSF, TEMIC, and Daimler-Benz Aerospace that was formedin early 1996.
***
Analog Digital Total
1995 Sales* ($M)
56
50
18
1
30
22
27
22
22
25
122
395
36
—
28
38
5
6
5
—
—
—
22
140
92
50
46
39
35
28
32
22
22
25
144
535
Figure 4-28. Major GaAs IC Suppliers
Back in 1991, IBM announced it was dropping its gallium-arsenide efforts in favor of silicon-ger-manium (SiGe) technology. Reported work from IBM shows that SiGe technology provides a 200-300 percent increase in transistor speed with a minimal rise in production cost. Today, IBM is bymost evaluations the leader in SiGe research and development, and even pilot production. Shownin Figure 4-29 is a cross section of an IBM high-performance FET designed using a 0.25µmBiCMOS SiGe process.
The concept behind SiGe is to add, through the doping process, the benefit of germanium’s highcarrier mobility compared to silicon; electron mobility in silicon germanium is nearly twice that inpure silicon. (Electron mobility in germanium is 3,900cm2/Vs versus 1,500 in silicon. Hole mobil-ity is germanium is 1,900cm2/Vs versus 475 in silicon.) High mobility benefits both bipolar andfield effect transistor (FET) devices.
Over the years, IBM has been working with several other IC manufacturers in the industry to com-mercialize products based on its SiGe process technology. For example, in the forth quarter of1993, IBM and Analog Devices began working together to develop SiGe ICs targeting the wirelesscommunications market and challenging GaAs applications at frequencies at or above 1GHz.
In addition, European semiconductor manufacturer, Telefunken Semiconductors, began volumeproduction of a SiGe analog RF IC in 1996. The device contains 30 transistors, had a die size oftwo square millimeters with feature sizes of 1.0µm. It targeted 1.8GHz mobile telecommunica-tions GaAs applications.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-21
Figure 4-29. IBM’s High-Performance SiGe FET
Source Drain
SiO2
N+ Si
SiGe (30%)
Silicon
Two DegreeElectron Gas
Silicon Channel
Silicon-Germanium (SiGe)
Silicon-Germanium Graded Buffer
Gate
Source: IBM Corp. 18736
Late in 1997 and into 1998, IBM’s belief in SiGe-based IC technology seems to be paying off. Forexample, Canadian Nortel and IBM announced an agreement to work together to commercializeSiGe ICs for high-speed telecommunications applications. Nortel will design prototype ICs forfiber transport products and high-speed cellular and PCS wireless applications and IBM will man-ufacture the devices. IBM has a similar agreement with Hughes. ICE believes that in 1998 IBMand others will make similar announcements that will finally launch SiGe-based IC technologyinto the commercial market.
SiGe will not only be competing with GaAs, but also with BiCMOS and even bipolar technologiesin the wireless communications market. The technology that gains the greatest market share willbe the one that can economically meet the performance requirements of the growing number ofhigh-performance applications.
Semiconductor Manufacturing Macrotrends
Conventionally, leading-edge technology has been predicted by Moore’s Law where the semicon-ductor industry’s complexity doubles every twenty-four months and semiconductor performancedoubles every eighteen. As we enter 1998, this venerable maxim seems to be failing. According tothe pending revised SIA National Technology Roadmap for Semiconductors (which was pendingpublication after ICE Status 1998 went to press) the industry is advancing at a pace that exceedsconvention (Figure 4-30); the prediction is that by 1999 the industry will be two years ahead ofwhere Moore’s Law says it should.
The previous 1994 SIA technology roadmap predicted that the 0.18µm device generation wouldarrive in 2001 and the 0.07µm generation in 2010. The revised roadmap pulls these dates closer,to 1999 and 2007, respectively. Many believe the two-year jump in the roadmap is possiblebecause semiconductor manufacturers have discovered that they can build chips with 0.18µmgeometries with the same wafer fabrication equipment that will be used for 0.25µm processing.
The industry’s accelerated move to smaller devices is increasing the need to address critical tech-nological challenges in design methodologies and tools, materials, process technology, processing-equipment development, and other areas before they develop into insurmountable roadblocks.Part of the task of the SIA roadmap’s authoring team of industry experts is to identify the issuesand challenges that that the industry faces (Figure 4-31).
Feature Size Trends
Figure 4-32 shows feature sizes for loose and tight production resolutions (i.e., routine andadvanced); tight production resolution has decreased from about 3µm in 1980 to around 0.25µmfor leading-edge 1G DRAMs. This represents about a 15 percent decrease every year. This trendis expected to continue and feature sizes are forecast to be about 0.15µm by 2000 for tight pro-duction resolution.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION4-22
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-23
1997 1999 2001 2003 2006 2009 2012
Chip Generation(Feature Size in Microns)
DRAM (Bits)
Logic(Millions of Transistors per sq cm)
ASICs(Millions of Transistors per sq cm)
MPU Chip Size (sq. mm.)
Year 1
Year 2
Year 3
DRAM Chip Size (sq mm)
Year 1
Year 2
Year 3
LithographyField Size (mm)
Number of Pins
On-Chip Clock Speed (MHz)
Minimum Mask Count
256M
300
240
180
280
220
170
512
750
22
1G
360
290
220
400
320
240
512
1,250
22-24
2G
400
320
240
480
390
290
654
1,500
23
4G
430
340
260
560
450
340
768
2,100
24
16G
520
420
310
790
630
480
768
3,500
24-26
64G
620
500
370
1,120
900
670
1,024
6,000
26-28
256G
750
600
450
1,580
1,300
950
1,280
10,000
28
Source: SIA 22770A
22x22 25x32 25x34 25x36 25x40 25x44 25x52
4 7 9 12 25 40 64
7 13 18 25 50 90 120
0.25 0.18 0.15 0.13 0.10 0.07 0.05
Figure 4-30. Draft Version of Revised SIA Technology Roadmap
ProcessComponent
Concerns
Design
Test
Process Integration,Devices and Structures
Factory Integration
Front-EndProcess Challenges
Interconnect
Lithography
• Lack of standards• Built-in self-test• Verification
• Equipment costs• Testing at high frequencies• Contacts for access
• Barrier materials for copper• Low materials• New insulators and capacitors• Stacking gate and source
• $1.4B to $2.4 costs• Investment recovery• Process complexity
• Copper eventually ineffective• How to detect, eliminate material defects at atomic level
• Reliability• New materials integration
• Production-worthy systems for 0.13 micron• X-ray, e-beam, extreme-UV• Masks• Advanced resists
Source: SIA 22748A
Figure 4-31. Technological Challenges Facing the Industry
Reportedly, the pending revised SIA National Technology Roadmap will show an interestingdevelopment; for the first time, microprocessors and logic ICs will be a generation ahead ofDRAMs, the traditional technology driver for the industry (Figure 4-33). According to prelimi-nary roadmap data, pilot production has already begun on wafers with 0.2µm to 0.18µm featuresizes for advanced microprocessors and ASICs, compared to the 0.25µm level for DRAMs. By2003, initial production of logic wafers will be at 0.11µm and DRAMs at 0.13µm. As shown inFigure 4-34, Intel expects that by 2001 about half of its volume production will be at the 0.18µmlevel, providing further evidence that high-margin products like microprocessors are beingaggressively moved to smaller device geometries.
Deep-submicron technology has decreased the significance of gate length when it comes to deter-mining MOS circuit density. Today, a more accurate indicator is metal pitch, which is defined asthe sum of the metal linewidth at a via and the space between the via and an adjacent line. It isa measure of how closely the metal lines are placed together. Thus, as shown in Figure 4-35,metal pitch sets the drain-to-source pitch in an individual transistor and the drain-to-drain pitchof isolated transistors.
Deep-submicron technology is closely linked to wafer fabrication lithography capability. Havingsurvived various forecasted practical limits to its resolution, optical lithography is now on anotherthreshold. But, once again, due to its relative low cost, familiarity and technical advancements,
Loose Production ResolutionTight Production Resolution
Development
HMOS II(2.0µm)
HMOS IV(1.0µm) 4M DRAM
(0.8µm)16M DRAM
(0.5µm)64M DRAM
(0.35µm)
256K DRAM(1.6µm) 1M DRAM
(1.2µm)
16M DRAM(0.5µm)
64M DRAM(0.35µm)
4M DRAM(0.8µm)
WE 3210032-Bit MPU
(1.5µm)
10981SSource: ICE
95
256MDRAM
(0.25µm)
256MDRAM
(0.25µm)
97
1G DRAM(0.15µm)
Toshiba(0.1µm)
Toshiba(0.04µm)
98 0200
(2.0µm)
(1.0µm)
(0.7µm)
4GDRAM
(0.08µm)
1GDRAM
(0.15µm)
Figure 4-32. IC Feature Size Trends
optical lithography is now forecast to be viable to 0.15µm, possibly 0.1µm. Despite the continu-ous predictions of its limitations, most see optical lithography as the mainstream technology intothe turn of the century.
Beyond this, a significant amount of research is being performed on extreme ultraviolet (EUV)lithography, which is expected to allow for the fabrication of ICs with feature sizes of 0.1µm andbelow. X-ray exposure techniques are also being aggressively developed for this region of pro-duction lithography. Interestingly, as occurred at past thresholds of optical lithography’s limits,the choices between optical, EUV, and x-ray, and even electron beam and ion beam technologies,are widely debated. Lithography is a complex mix of tools, energy sources, mask making, andresist chemistry; the latter always seems to lag the race, but has always arrived on time for opti-cal lithography in the past. Most experts cite 1998 as the decision year for determining which lith-ography technique will emerge for features sizes below 0.15µm.
The following are some of the past-year’s business and technology announcements that reflectproduction linewidth trends in the semiconductor industry:
• Hitachi Semiconductor America of Texas began installing wafer fab equipment to support0.25µm processing. This technology will be used to launch production of the SH-4 300 MIPSRISC microcontroller.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-25
0.10
0.15
0.20
0.25
0.30
0.35
2004200320022001200019991998199719961995
Fea
ture
Siz
e (µ
m)
Year
Source: Semiconductor Business News/SIA 22749
Existing Roadmapfor all Devices
ProposedDRAM
Roadmap
ProposedMPU/LogicRoadmap
Figure 4-33. New SIA Roadmap Shows Logic Taking Over Memory as Technology Driver
• NEC is investing more than $2 million to convert its Roseville, California, wafer fabricationfacility into 0.18µm and 0.25µm lines to manufacture a third generation of 16M DRAM chips,high-performance ASICS and microcontrollers.
• Singapore’s Chartered Semiconductor Manufacturing, Taiwan SemiconductorManufacturing, and Taiwan’s United Microelectronics all announced plans to convert from0.35µm to 0.25µm wafer processing technology.
Wiring Levels
The number of aluminum metal wiring levels has tripled in the last decade for both logic andmemory products. For example, Figure 4-36 shows historical wiring level trends for IBM’s logicIC products through the mid-1990s. Today, five layers are common with 0.25µm process technol-ogy, with some companies using six.
The degree of difficulty with this number of aluminum wiring levels is eased somewhat withchemical mechanical polishing (CMP), which smoothes the surface of each interlayer dielectricinsulator; CMP has been adopted by most manufacturers of high-performance ICs. With CMP, thesurface of the IC remains planar, and thus, metal layers can be stacked vertically without the con-ventional problems associated with fabricating conformal metal patterns over steps.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION4-26
0
10
20
30
40
50
60
70
80
90
100
200120001999199819971996
Per
cen
tag
e
Year
Source: Intel 22750
0.18µ
0.25µ
0.35µ
0.5µ and above
Figure 4-34. Intel’s Expected Output by Geometry
However, beyond five or six aluminum wiring levels, additional levels may not reduce die sizeenough to offset higher processing cost. For many years the talked about and sought after solu-tions have revolved around replacing aluminum with copper and replacing conventional silicondioxide with a so-called high dielectric constant insulating layer between levels.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-27
Gate Gate
Source: Computer Design/VLSI Technology 21244
Drain Drain SourceSource
Figure 4-35. Influence of Metal Pitch on Deep-Submicron Device Layout
7
6
5
4
3
2
1
0'75 '77 '79 '81 '83 '85 '87 '89 '91 '93 '95
Year
Nu
mb
er o
f W
irin
g L
evel
s
Source: IBM 21757
Figure 4-36. Historical Logic IC Wiring Level Trends
Leading manufacturers are now adopting copper wiring; late in 1997 both IBM and Motorolaannounced use of this technology. ICE expects similar announcements from other semiconductormanufacturers in 1998.
Compared to aluminum, copper saves about two metal layers for a given device generation(Figure 4-37). When copper is combined with a low dielectric constant insulating material, addi-tional wiring levels can be saved. A report from Intel details that converting to copper and low-dielectric material can save four metal levels and postpone reaching an impractical number ofwiring levels by two IC generations.
IC Integration Density Trends
By shrinking IC feature sizes and adding more layers of metal, IC manufacturers have been ableto continually and dramatically increase integration levels (Figure 4-38). MOS memory IC inte-gration levels have increased an average of 50 percent per year for the past 26 years. The 1998DRAM density level is expected to contain over 256 million transistors. Devices with 1 billiontransistors per chip are forecast to appear on the market by 2000.
The transistor count of new microprocessors also continues to increase; here the rate is approxi-mately 35 percent each year. Intel’s Pentium with 3.1 million transistors and Pentium Pro with 5.5million transistors fell slightly short of the microprocessor-and-logic trend line in 1993 and 1995.However, this should not be taken as an indication that the growth in microprocessor integrationlevels is slowing. Other microprocessors, such as Digital’s Alpha 21164 with 9.7 million transis-tors and AMD’s K6 with 8.8 million transistors, fall on the escalating IC density trend.
Integration levels in ASICs are also growing rapidly. For example, LSI Logic claims its most recentG11-generation ASIC technology allows for the integration of up to 64 million transistors on asingle chip. In comparison, the company’s leading-edge technology in 1988 could pack one mil-lion transistors on a chip. Another leader in ASIC technology, Texas Instruments, claims to haveushered in the 100-million-transistor ASIC era with the introduction of its Timeline technologythat is capable of ICs with up to 125 million transistors.
Die Size Trends
With the escalation of transistors per die, average die sizes have also increased. Figure 4-39 showsthat the die area of leading-edge ICs, both memory and logic types, has increased about 13 per-cent per year. The trend toward larger die sizes, at least for memory, is forecast to continue at thisrate into the early part of the next decade.
Figure 4-40 provides a look at die sizes of leading-edge DRAMs, which are typically reported atthe annual International Solid-State Circuits Conference (ISSCC). The die sizes of 1G DRAMsdescribed at the 1995 and 1996 ISSCC ranged from 901,000 mils2 to 1,451,000 mils2. The NEC 4GDRAM, reported at ISSCC in 1997, is 1,527,000 mils2; interestingly, this is only slightly larger thanNEC’s 1G chip. NEC accomplished this using a technology that allows four levels of data to bestored in each cell, as compared to two levels in conventional cells. Figure 4-41 is an example ofone of the first working prototypes of the 4G DRAM from NEC. Other DRAM companies areevaluating and developing technologies like multilevel cell techniques to make future-generationDRAMs more economical to produce.
Similarly, by aggressively reducing chip linewidths and using additional metal layers, micro-processor manufacturers have been able to slow the rate of die size increase. In fact, Intel’s next-generation Merced P7 processor is expected to be roughly the same size as the first Pentium Pro.
The forces behind the semiconductor industry’s periodic change to larger silicon wafers is driven bythe savings from producing more dice per individual wafer while using the same, or only fraction-ally increased, number of process steps and volume of process materials. As 1998 begins, the world-wide semiconductor industry is on the pilot-line threshold of a transition to 300mm silicon wafers.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-31
FeatureSize (µm)
CellSize (µm2)Density
Chip Size(K sq. mils)
AccessTime (ns) Organization ConferenceCompany
Hyundai
Matsushita
Mitsubishi1
Oki2
Mitsubishi3
Samsung4
Hitachi
NEC
NEC5
256M
256M
256M
256M
1G
1G
1G
1G
4G
0.3
0.25
0.25
0.25
0.14
0.16
0.16
0.25
0.15
—
0.72
0.72
0.72
0.29
—
0.29
0.54
0.23
561
638
472
530
901
1,010
1,108
1,451
1,527
36
—
34
—
32
—
33
—
—
32M x 8
16M x 16
32M x 8
32M x 8
—
—
64M x 16
—
—
ISSCC '95
ISSCC '94
ISSCC '94
ISSCC '94
ISSCC '96
ISSCC '96
ISSCC '95
ISSCC '95
ISSCC '97
1 Produced using KrF excimer-laser lithography.2 Packaged in a 64-pin 600-mil TSOP, produced using e-beam lithography.3 SDRAM produced using synchrotron-generated x-ray lithography.4 SDRAM produced using KrF excimer-laser lithography.5 Each cell can store four levels of data, compared to two levels in conventional cells.
20289BSource: ICE
Figure 4-40. ISSCC Advanced DRAMs
Source: NEC 22410
Figure 4-41. A 4-Gbit DRAM
Based on historical trends, peak demand for 200mm wafers, the current leading edge for produc-tion, will be reached around 2003, as shown in Figure 4-42. This wafer-size life-cycle perspectivecan be used as a guide as the semiconductor industry continues to move to larger wafers.
While silicon-based semiconductor manufacturers are developing the technologies needed for300mm wafer processing, many GaAs semiconductor manufacturers are undergoing or consider-ing a transition to 150mm wafer processing from 100mm. Some of the leading manufacturers evenbegan using 150mm wafers in 1997. GaAs wafer supplier Simitomo Electric plans for its output ofraw 150mm GaAs wafers to reach 3,000 units per month by the end of 1998. Like with silicon-based semiconductor manufacturing, every incremental increase in GaAs wafer size brings withit gains in manufacturing productivity and reductions in IC manufacturing cost.
Wafer size increases are commonly evaluated in terms of increase in wafer area, as shown inFigure 4-43. Interestingly, the move from 100mm wafers to 150mm wafers increased the siliconarea by 125 percent—the same relative gain that will be realized when semiconductor companiesmake the transition from today’s 200mm wafers to 300mm wafers. Beyond 300mm, the same gainrequires a jump to 450mm wafers.
Early on, semiconductor manufacturers had said they wanted to be in full production of 300mmwafers in 1998. However, issues such as limited funding, the need for longer development time,and the extended life span of 200mm wafers have pushed full-scale production out several years.One of the latest polls shows that several companies, generically identified, expect pilot or low-volume fabrication on 300mm wafers to start in 1998, with high-volume facilities expected to enterproduction around 2000 (Figure 4-44). Hitachi, IBM, Intel, NEC, Samsung, and Texas Instrumentswill be among the first to operate 300mm fabs for volume IC production.
Semiconductor manufacturers have unquestionably stated that 300mm technology developmentwill not be performed solely by the themselves, as it was in previous generations with Intelenabling the transition to 150mm wafers and IBM managing the transition to 200mm wafers. Inthe case of 300mm wafers, the technical challenges are so involved that they require an unprece-dented level of industry-wide cooperation.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-33
0 50 100 150 200
125
56
78
125
78
156
125
56W
afer
Dia
met
er T
ran
siti
on
100mm → 125mm
100mm → 150mm
125mm → 200mm
150mm → 200mm
200mm → 250mm
Percent Increase
Source: ICE 18603A
250mm → 300mm
200mm → 300mm
300mm → 400mm
300mm → 450mm
44
Figure 4-43. Wafer Area Increases (Percent)
High Volume (20,000)
Medium Volume (10,000)
Low Volume (2,000)
Pilot Line (500-1,000)
Fab Size (Wafers per Month)
—
—
2
9
1998
—
1
5
5
1999
5
4
—
—
2000
4
—
—
—
2001
2
1
—
—
2002
Source: SEMI 22665
Figure 4-44. Planned 300mm Wafer Fabs
It is estimated that the industry’s overall cost of making the transition to 300mm wafers will bein the area of $15 billion to $20 billion. This includes development of the wafer processingequipment and techniques, development costs of wafer handling tools, computer integratedmanufacturing software, factory automation systems, and cleanroom technology. Texas
Instruments estimates that while300mm tool costs will increase by20-40 percent over 200mm wafers,an overall 27-39 percent reductionin the cost per chip can be realized(Figure 4-45). In addition, TexasInstruments estimates that laborcost, materials use, and factoryemissions should be comparablebetween the two wafer sizes andthat higher yields may be possible.
As of late 1997, the price of a prime 300mm wafer ranged from $1,000 to $1,500, depending onvolume. In the early years of the next decade, when 300mm wafer use is expected to be in highervolume, wafer costs are forecast to be in the range of $450 to $600.
Demand for 300 mm wafers is likely to surpass 1.2 million units in 2000, up from about 45,000wafers in 1998. One-third of the 300mm wafers in 2000 will be silicon epitaxy wafer starts.Understandably, initially over half the 300mm wafers will be test wafers. But part of the successof 300mm production will involve the development of in-situ and on-product-wafer metrologycapabilities that preclude the need for test wafers.
Samsung estimates that a 20,000-wafer-per-month 300mm manufacturing facility will cost approx-imately $2.4 billion, and will require a 130,000-square-foot cleanroom. A 30,000-wafer-per-monthfacility will cost approximately $3.6 billion and require 200,000 square feet of cleanroom space.
Two major industry consortia were formed in 1996 with the goal of lowering the barriers to devel-opment of 300mm technologies. One effort is the International 300mm Initiative, or I300I, formedby United States based Sematech in January, 1996. Participation in I300I is open to U.S. IC manu-facturers and foreign companies with wafer fabs located in the U.S. (Figure 4-46). I300I anticipateshaving 70-80 wafer processing systems tested and qualified by the end of 1998. Initially fundedat $26 million ($2 million from each of its 13 members), I300I’s program goals include:
• providing inputs to international standards activities,• developing consensus on performance metrics and demonstration methods,• demonstrating 300mm equipment and materials for 0.25µm processing, and• defining a program by mid-1998 for demonstrating and qualifying 0.18µm equipment,
which will be performed through 2000.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION4-34
Cost Per Square cm
Usable Portion of Wafer
Cost Per Chip
Labor
Tool Capital Cost
Materials Use
Emissions
Process/Probe Yield
25 - 30% Less
3 - 14% More
27 - 39% Less
About Equal
20 - 40% More
About Equal
About Equal
Slightly Better
Source: Texas Instruments 22623
Figure 4-45. 300mm Versus 200mm at Maturity
The Japanese formed their own consortium in February, 1996. Called the Semiconductor LeadingEdge Technologies venture, or SELETE, it is represented by Japan’s ten largest semiconductorcompanies (Figure 4-47). SELETE plans to spend roughly $350 million before the turn of the cen-tury. Like I300I, SELETE will first focus on 0.25µm, 300mm wafer manufacturing and subse-quently on 0.18µm fabrication and more stringent requirements. SELETE operates a cleanroomwithin an existing Hitachi wafer fabrication facility in Yokohama, Japan.
Continuing success in transitioning to 300mm wafers will depend on the level of interactionbetween organizations like I300I and SELETE for the purpose of developing global industry stan-dards. Developmental wafer specifications have been drafted and specifications for circuit qual-ity wafers are nearing completion. Device manufacturers have yet to agree as to how standardsfor wafer carriers and tool interfaces should be defined. There are eight possible combinations oflot sizes with 13 or 25 wafers, integral versus removable cassettes, and front-opening or side-open-ing boxes that are being proposed.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-35
U.S. Companies
European Companies
Korean Companies
Other Companies
Advanced Micro Devices
IBM
Intel
Lucent Technologies
Motorola
Texas Instruments
Philips
SGS-Thomson
Siemens
Hyundai
LG Semicon
Samsung
TSMC (Taiwan)
Source: ICE 21753
Figure 4-46. I300I Member Companies
Source: ICE 21754
• Fujitsu• Hitachi• Matsushita• Mitsubishi• NEC
• Oki• Sanyo• Sharp• Sony• Toshiba
Figure 4-47. SELETE Member Companies
Once standards are in place and equipment is readied, there are additional issues that must beremedied if 300mm wafer processing is to become a reality. A few of the many wafer processingquestions or concerns that must be addressed include:
• Ensuring uniformity of deposition and etch.• Ensuring the integrity of wafer flatness across the 300mm diameter.• Developing the necessary ion implantation processes (single wafer or batch)• Reducing or eliminating test wafer use.• Establishing lower furnace process temperatures (300mm wafers will require approximately
900°C maximum versus 1200°C for 200mm wafers).• Optimizing chemical quantities for processing.
Figure 4-48 compares the development time for each new wafer generation. As shown, the timerequired has increased significantly over prior generations. While it took five years for 200mmwafers to reach an annual production rate of 100 million square-inches per year, it has been esti-mated that eight years will be needed for 300mm wafers.
Longer term, the Japanese industry is already looking at 400mm silicon wafers. Its Super SiliconCrystal Research Institute, formed by seven major silicon wafer makers and the Japan KeyTechnology Center, is now studying silicon crystal pulling methods, wafer slicing techniques anddeveloping metrics for evaluating the properties of these giant wafers; this project is fundedthrough 2001. So far, this organization believes that the doping properties and quality of 400mmplus wafers can only be controlled with subsequent deposition of epitaxial layers, particularly ifthey are introduced for DRAM manufacturing.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION4-36
100mm
8 years (EST)
5 years
3 years
3 years
3 years
125mm
150mm
200mm
300mm
Source: Rose Associates 21192A
Figure 4-48. Wafer Development Time Requirements (Time to Reach 100 Million Square Inch Production Rate)
The Future of IC Technology
In general, there are several scenarios about advanced IC manufacturing at the turn of the century.The first is that post-2000 ICs will happen as planned and will be manufactured economically aswell. The reasoning behind this view lies in historical precedent: Since the 1990s-type ICsappeared impossible in the early 1980s, and yet were created with the assistance of significantadvances in manufacturing technology, the impossible appearing post-2000 ICs will follow thissame path to fruition. The second scenario reasons that it is not realistic to keep extrapolating his-torical trends in IC technology to infinity. At some point, physical or economic limits will prevail.
While it is easy to find refuge in the second scenario, the message of historical trends and incred-ible advances associated with semiconductor manufacturing cannot be ignored. Indeed, ICEbelieves that the latest thinking of the industry experts, reflected in the pending new SIAroadmap, indicate a third scenario that defines the likely trend for the turn of the century: Theindustry is diverting from historical trends, advancing beyond the traditional forecast of Moore’sLaw not slowing. Here, the more likely unknown factors involve the economic feasibility of manyof the new technologies.
IC PACKAGING TECHNOLOGY OVERVIEW
IC packaging is receiving much more attention now than in the past. Today, systems manufac-turers, as well as IC manufacturers, realize an increasing percentage of system performance, orperformance limits, is determined by the IC-and-package combination, rather than just the IC. Inaddition, packaging is increasingly more costly. ICE forecasts that IC packaging costs will con-tinue to rise significantly into the turn of the century since more of the newer ICs now requirehigh-lead-count, expensive packages.
Analyzing markets of various major packages types (Figures 4-49), the surface-mountable smalloutline package (SOP) had the greatest market share in 1997; surface mount technology continuesto dominate printed circuit boards (PCBs). In was just in 1994 that surface mount packaged ICsfirst out shipped conventional through-hole packaged ICs. It is expected that by 2002, surfacemount packages will have about seven times the unit market share of through-hole packages(Figure 4-50).
The primary advantage of surface mount packaging is improved performance and savings inspace at the PCB and system levels. Not only are surface mount packages smaller, they can alsobe placed on both sides of a PCB. This savings in space can reduce PCB costs by as much as 60percent, while improving performance at the same time
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-37
The current driving force on SOPs, especially for memory and logic IC packaging, is to reduce thethickness or profile of the package, particularly for memory applications (Figure 4-51). This willenable portable applications where size and weight are important constraints. For logic IC appli-cations in portable electronic equipment, semiconductor manufacturer TI unveiled a new chippackage that uses about 40 to 60 percent less board space than a shrink small outline package(SSOP). TI’s thin very small outline package (TVSOP) features a lead pitch of 0.4mm, comparedto SSOP’s 0.5mm pitch, and a mounted height of 1.2mm, which is only 50 percent greater than thethickness of a standard credit card.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION4-38
PackageType
1996
Units(M)
PercentOf Total
1997 (EST)
Units(M)
PercentOf Total
14737RSource: ICE
1997/1996PercentChange
*Includes UTSOPs, QSOPs, TSOPs, and SOJs.**Includes TAB-on-board, COB, flatpacks, metal cans, LLCC, LDCC, etc.
2002 (FCST)
Units(M)
PercentOf Total
1996-2002CAGR
(%)
13,400
445
40
115
100
90
23,120
2,270
6,390
2,830
48,800
Plastic DIP
CERDIP
Sidebraze DIP
Ceramic PGA
Plastic PGA
BGA/CSP
SOP*
PLCC
PQFP
Other**
Total
27
1
<1
<1
<1
<1
47
5
13
6
100
14,500
415
35
125
130
160
28,760
2,390
7,600
3,160
57,275
25
1
<1
<1
<1
<1
50
4
13
6
100
8
–7
–13
9
30
78
24
5
19
12
17
9,100
170
15
145
260
2,600
51,300
2,630
15,300
6,700
88,220
10
<1
<1
<1
<1
3
58
3
17
8
100
–6
–15
–15
4
17
75
14
2
16
15
10
Figure 4-49. Worldwide Merchant IC Package Marketshare (Units)
SurfaceMount73%
ThroughHole27%
SOP50%
Other23%
Other2%
PlasticDIP25%
Surface Mount88%
SOP58%
Other30%
Through Hole12%
Plastic DIP10% Other
2%
2002 (FCST)88.2B
16827NSource: ICE
1997 (EST)57.3B
Figure 4-50. IC Package Market Share (Units)
Of the various package types, SOPs, ball grid arrays (BGAs) and chip scale packages (CSPs), plas-tic pin grid arrays (PPGAs) and quad flat packs (QFPs) are anticipated to show the strongestgrowth through 2002. The dominant package types—SOPS, plastic dual inline packages (PDIPs),and plastic quad flat packs (PQFPs)—are forecast to make up about 86 percent of the IC-packageunit market in 2002.
The trend shown with estimated 1997 and forecasted 2002 IC markets by product type clearlyshows that surface mount technology is gaining almost complete dominance (Figure 4-52). Forexample, in 1997 MOS memory had a very high 94 percent penetration rate for surface mount.Even where surface mount unit volumes now only represent healthy 67 and 72 percent for analogand MOS logic, both these IC types show a significant increase to surface mount packages by 2002,to 82 and 92 percent respectively.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-39
PQFP TQFPTSOP
UTQFPUTSOP
mm 3.6 2.0 1.4 1.0 0.5-0.8
Source: Portable Design 22404
Figure 4-51. Package Profile Evolution
Product
Market ($B) ASP ($) Unit Volume (B)Percent
Surface MountSurface
Mount Units (B)
Digital Bipolar
Analog
Microcomponent
MOS Logic
Memory
Total
CAGR 1997-2002
1997(EST)
1997(EST)
1997(EST)
1997(EST)
1997(EST)
2002(FCST)
2002(FCST)
2002(FCST)
2002(FCST)
2002(FCST)
0.48
0.74
8.03
1.76
4.31
2.22
60
67
87
72
94
73
75
82
98
92
99
88
20313ESource: ICE
—
1.6
19.7
50.6
24.3
31.0
127.2
0.8
48.0
134.9
61.9
103.9
349.5
22% 12%
0.40
1.08
12.73
3.21
8.73
3.96
3.3
26.7
6.3
13.8
7.2
57.3
2.0
44.4
10.6
19.3
11.9
88.2
2.0
17.9
5.5
9.9
6.8
42.1
1.5
36.4
10.4
17.8
11.8
77.8
13%9%
Figure 4-52. 2002 Surface Mount Package IC Unit Forecast
The analog IC segment of the market will contribute over half of the annual increase in total IC andsurface mount unit volume shipments through 2002 (Figure 4-53). Since most analog componentsare low-density devices, the surface mount trend in this segment is primarily directed at SOPs.Overall, analog and memory products will represent the majority of SOP applications in 2002.
As for package materials, plastic packages will dominate more than 90 percent of packagesshipped (Figure 4-54). Ceramic packages have been losing market share to plastic packages forseveral reasons, including the industry’s move to plastic-packaged flash memories and awayfrom ceramic-packaged electrically programmable read only memories (EPROMs), the U.S. mil-itary’s implementation of plastic IC packages in many of the less-harsh system environments,and Intel’s 1996 decision to change the packaging of its advanced microprocessors from ceramicto plastic. The conductivity and dielectric qualities of laminate packages, which are multilayerplastic packages made of copper and epoxy resin, make them attractive for high-speed chips likeIntel’s microprocessors.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION4-40
Product1997/2002
Unit VolumeChange (B)
ContributionTo TotalIncrease(Percent)
1997/2002Surface MountUnit VolumeChange (B)
ContributionTo TotalIncrease(Percent)
Analog
MOS Logic
Microcomponent
Memory
Bipolar Digital
1997/2002Net Increase
57
18
14
15
–4
—
20314DSource: ICE
17.7
5.5
4.3
4.7
–1.3
30.9
18.5
7.8
4.9
5.0
–0.5
35.8
52
22
14
14
–1
—
Figure 4-53. Analog and MOS Logic Products Drive Surface Mount Volume
1997 (EST)57.3B
Ceramic2%
Other*5%
Plastic93%
2002 (FCST)88.2B Ceramic
1%
Other*7%
Plastic92%
12061USource: ICE
*Includes TAB-on-board, COB, flatpacks, metal cans, bare dice for MCMs, etc.
Figure 4-54. Worldwide Merchant IC Package Marketshare by Material (Units)
The increasing density and complexity of ICs are also pushing the state-of-the-art in pin count,especially for various gate arrays and microprocessors (Figure 4-55). Although high-pin countpackages currently represent a small percentage of the units shipped (Figure 4-56), the number ofpackages with pin counts over 68 is steadily increasing. Some packages with pin counts as highas 1,500 may be in production by the end of the decade (Figure 4-57).
Figure 4-56. IC Package Unit Shipments by Pin Count
As pin counts have increased, the industry has gravitated toward fine-pitch lead technology(FPT). The Institute for Interconnection and Packaging Electronic Circuits (IPC) defines FPT asthose devices that have lead pitches ranging from 0.5mm to 0.1mm (20mils to 4mils). Below0.1mm, the term ultrafine pitch has been suggested. With FPT, package leads are highly sus-ceptibility to damage. Fine-pitch leads cannot be touched before being placed on a board orsubstrate. In most cases an FPT IC must be placed and held in position until soldering of theleads is completed.
Lead coplanarity and integrity are also critical issues with today’s advanced packages. Specialcarriers are frequently used to hold a package’s outer leads until immediately before PCB attach-ment. These carriers also provide easily accessible test contacts so that chips can be fully testedbefore PCB assembly. The delicate nature of fine or ultrafine-pitch packages has many designersconsidering BGA package options.
Most IC assembly and packaging operations for semiconductor manufacturing are still located inAsia-Pacific (Figure 4-58). This is due primarily to low labor cost. However, the importance oflabor cost is decreasing, largely because packaging equipment advances are making packagingoperations more automated. This, coupled with the need for shorter lead times, will be a factor inmaking onshore packaging more attractive. Nevertheless, the existing experienced and sophisti-cated packaging infrastructure as well as economic benefits and tax breaks help to keep Asia-Pacific an attractive region for semiconductor assembly, the so-called back-end operations ofsemiconductor manufacturing, especially for high-volume IC packaging operations.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION4-42
0
200
400
600
800
1,000
1,200
1,400
1,600
1,800
20012000199919981997199619951994
Nu
mb
er o
f I/O
s P
er C
om
po
nen
t
Year21196Source: Mentor Graphics/EE Times
Figure 4-57. Pin Count Forecast
Ball Grid Arrays
One of the most talked about surface mount packages is the ball grid array (BGA), shown in anexploded view in Figure 4-59. A BGA package, rather than using pins for leads, mounts to a PCBusing solder balls located on the underside of the package. The BGA was first introduced by IBMas a ceramic package for its own internal use. It wasn’t until Motorola’s 1989 introduction of aplastic version of the BGA, labeled OMPAC, that the technology began to take hold commer-cially. Motorola worked with Compaq Computer on the first implementation of the package intonew products.
Proponents of the BGA say it provides benefits such as small size, good yields, excellent electricalperformance, and low profiles—features that have been demanded by system designers. Byspreading the contacts over the bottom of the packaged device, the size of the package is reducedcompared to QFPs. No longer are there many small, fragile leads jutting out from all sides of thepackage. The rising number of leads per package and lead pitch limitations are the driving forcesbehind the increasing popularity of BGAs (Figure 4-60).
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-43
Asia Pacific60%Japan 25%
NorthAmerica 8%
Europe5%
ROW 2%
57.3BUnits
20312ESource: Emissarius, Ltd.
Figure 4-58. Estimated 1997 Final IC Packaging by Location
Mounting Pads
Interconnection Matrix• Wirebond• TAB• Flip-Chip
Solder-BumpMounting Pads
BGA Substrate
Bare Chip
Printed Circuit Board
Source: Electronic Design 22767A
Cover
Figure 4-59. General BGA Construction
One of the early concerns with using a BGA was how to effectively inspect the final soldered balljoints that attached these packages to a PCB. With many of the solder joints hidden beneath thepackage, visual inspection is impossible, making it necessary to use x-ray machines. Recently,companies have found that every solder ball joint does not need to be checked if the process iscontrolled. The key to good BGA assembly processing is said to be in the solder paste.
Another concern has been the high costs associated with BGAs. Even with increased volumes,BGAs will more than likely command a greater price than QFPs since BGAs have an internal cir-cuit board that holds the chip and fans out the leads. BGAs also add to PCB complexity; althoughtheir PCB footprint is relatively small, PCBs accepting BGAs may require more layers. This canserve to increase the cost of the subsystem. Moreover, repairability is also difficult with currentBGA packages.
As further experience is gained, BGA packaging is expected to be widely used, especially for logicand memory ICs in high-performance applications, including pagers and cellular phones.
The following are some of 1997’s significant BGA-related business and technology announcements:
• Fujitsu and Toshiba jointly agreed on common specifications for a 48-pad BGA packagehousing multiple memory chips. The BGA configuration is aimed at encasing flash memoryand SRAM ICs in a single multichip package that occupies up to 70 percent less space thanconventional methods using two TSOPs. The package targets manufacturers of cellularphones and other mobile products.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION4-44
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
100 200 300 400 500 600 700 800 900I/Os
Pit
ch (
mm
)Ball-Grid Array (BGA)
Quad Flat Pack (QFP)
Technologicallimit for QFP
fine pitch
Technological jumpfrom QFP to BGA
Limit of what canbe done "simply"
Limit range of what can bereasonably accomplished in light of cost considerations
20315Source: IBL-Löttechnik
Figure 4-60. Fine Pitch, High I/Os Push Packaging to Ball-Grid Arrays
• A new type of area array package was developed by Belgium’s IMEC, in collaboration withSiemens Laboratories, that is said to offer higher density and better thermal handling capa-bilities than conventional PGA and BGA packages. The polymer stud grid array (PSGA) con-sists of a polymer injection molded body with a cavity for chip mounting and metallizedpolymer studs.
• ProLinx Labs, San Jose, California, announced an agreement with Taiwanese PCB manu-facturer, Unicap Electronics Industrial to build a $42 million facility focused on the produc-tion of BGAs based on ProLinx technologies. To be located in Taiwan, the new plant willimplement the Micro-filled Via (MfVia) process used to produce ProLinx’s ViperBGA(VBGA) substrate.
• In late January, 1997, Amkor Electronics announced it would build a 280,000-square-footBGA assembly facility in Chandler, Arizona. The first phase of the plant was expected to becompleted by mid-1997.
• S-MOS Systems added a BGA version to its SED 1560 series of 3V, single-chip LCD driversand controllers.
Chip-Scale Packages
Chip-scale packaging is one of the hottest topics in the packaging industry (Figure 4-61). In fact,the chip-scale package (CSP) has been called “the choice of the future,” having achieved verywidespread acceptance in a very short time. The CSP is only slightly larger than the die itself, typ-ically less than 20 percent larger. CSPs with peripheral leads are suited for low lead-count pack-ages with 50-100 pins, while CSP area arrays are particularly well suited for high lead-countpackages, eventually exceeding 1000 pins.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-45
Semiconductor Chip
Compliant Layer
ProtectiveCoating
Interconnect
Flex Circuit Bump Array – Gold Plated
The bump array, which is mounted on a compliant layer to reducethe mechanical stress of the solder joint and accommodate surfaceirregularities on the printed circuit board, uses gold plated bumpsfor reliability.
19505ASource: Tessera
Printed Circuit Board
Figure 4-61. Diagram of a Tessera µBGA Package
Chip-scale packaging has been labeled by some to be the solution that offers size and performancebenefits of packageless technologies such as flip chip, chip-on-board, and bare die, but at a lowercost and without requiring custom packaging. CSPs combine the best features of bare die assem-bly with the numerous advantages of fully packaged ICs (Figure 4-62). Furthermore, CSPs areshowing some promise to driving IC packaging costs below the much sought after benchmarkprice of one cent per pin or lead.
One disadvantage of CSPs is that some of the fine-pitch manufacturing problems solved in tran-sitioning from QFPs to BGAs are being reintroduced. In addition, the greater density of CSPs,when compared to BGAs, requires more complex sockets for test and burn-in. The resolution ofproblems such as these will determine how far CSPs take the industry.
Currently, there are in excess of 35 companies offering CSPs using a variety of technologies.Figure 4-63 describes the packages from several of the suppliers. Some of the CSPs that haveentered volume production include Tessera’s microBGA (µBGA), the MSMT package offered byChipScale and produced by Motorola, the CSBGA package from Amkor, TI’s MicroStar BGA,Fujitsu’s small-outline no-lead (SON) package, and an array CSPs from Sharp.
The most visible vendor for CSP is Tessera; for example, Tessera’s µBGA gained a significantamount of momentum in 1996 when Intel and Texas Instruments licensed the technology for usein packaging flash memory ICs. The company’s business plan is to license its technology toassembly, package, and IC suppliers, while providing the technical support and guidance to bringup its customers’ production lines. Semiconductor manufacturers Amkor, Shinko, Intel, AMD, TI,and Hitachi are among the licensees who are ramping up production volume.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION4-46
Bare ChipTechnologies*
Chip Scale PackagingTechnology
Traditional IC PackagingTechnology
Die Size
Short Electrical Path
High I/O Capability
Thermal Management
Die Size
Standard Foot Prints
Short Electrical Path
Low Cost
High I/O Capability
Assembly Infrastructure
Thermal Management**
Alpha Particle Protection
Ease of Test
Protection for Die
Immunity to Die Shrink**
Reworkable
Standard Foot Prints
Low Cost
Assembly Infrastructure
Alpha Particle Protection
Ease of Test
Protection for Die
Immunity to Die Shrink
Reworkable
* Flip-chip is generally considered to be superior to chip-and-wire technology in all listed categories and is therefore the primary reference for the chart above.
** Attributes will vary from CSP type to CSP type.Source: Semiconductor International 21775
Figure 4-62. CSP Offers Best of Both
Why Intel chose to use the µBGA package is clear in Figure 4-64. The company’s 0.4µm, 8M flashmemory packaged in a 5x8 ball matrix µBGA is 80 percent smaller and 17 percent thinner than its40-lead TSOP counterpart. It is interesting to note, however, that Intel believes the majority orabout two-thirds of its flash products will continue to be manufactured in TSOPs for the foresee-able future.
TI has said it is considering using the µBGA to package some of its other ICs. In addition, whileTessera will initially produce the packages for the company, TI plans to eventually produce thepackages itself.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-47
Package SupplierPrimary Package
ConstructionLead
Arrangement
Individual ChipProcessingCapable?
Wafer LevelProcessingCapable?
Amkor
ChipScale
Fujitsu
Matsushita
Mitsubishi
Motorola
NEC
Nitto Denko
Sandia
Sharp
ShellCase
Tessera
TI
Flexible interposer withcompliant encapsulant
Silicon sandwich withchevron beam leads
Lead on chip wire bondedand molded
Flip-chip with underfill onceramic carrier
Redistribution wiring onchip with transfer bumps
Flip-chip with underfill onorganic carrier
Flex circuit interposerwith bumped leads
Flex circuit interposerwith bumped leads
Rigid polyimide film withredistribution wiring
Wire bonding onto flexcarrier
Silicon and glass withedge wrapped leads
Flexible interposer withcomplaint encapsulant
Wire bonding onto flexcarrier
Area array
Peripheralleads
Peripheralleads
Area array
Area array
Area array
Area array
Area array
Area array
Area array
Peripheralleads
Area array
Area array
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
No
Yes
No
No
Yes
No
No
No
No
No
No
Yes
No
Yes
Yes
No
Source: Semiconductor International 21776
Figure 4-63. Examples of CSP Technologies
Multichip Modules
Virtually every large computer manufacturer, telecommunications manufacturer, high-volumeconsumer electronics manufacturer, and aerospace systems manufacturer are working on or con-sidering designs that include multichip modules (MCMs). There has been a dramatic increase inactivity over the last five years, with entire conferences being dedicated to MCMs. MCMs havegone through three phases in their growth:
Phase one was the widespread use in mainframe and super computers. The primary driving forcewas performance. These systems were predominantly ECL-IC based, with relatively low integra-tion levels. The MCM implementation allowed the re-integration of large scale integration (LSI)chips into very large scale integration (VLSI) modules, while keeping wiring delays small.
Phase two was the exploration of MCM technologies and the building of an infant infrastructureby the visionaries and champions of a merchant MCM industry. Many of these early pioneers hadtheir start in large system companies. This was a period of high expectations being set. MCMswere viewed as taking over all of packaging. The single-chip package was declared dead. Endusers of everything from computers to consumer products, such as Sun, Silicon Graphics, AppleComputers, LSI Logic, and Kodak, had designed and built a number of prototype MCMs to eval-uate the vendor base, technology options, and cost-performance benefits to MCMs. A few of thesedesigns actually went into limited production. Figure 4-65 is an example of a four-chip graphicscontroller module LSI Logic designed for Silicon Graphics, currently in production.
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION4-48
Source: Tessera 22766
40-Pin TSOP1.00x
40-Bump µBGA0.20x
Figure 4-64. Switching from TSOP to CSP Shrinks Intel’s Flash 80 Percent
The third phase rose out of the visionary second phase. This included the establishment of astrong merchant infrastructure and the introduction of MCM designs that are in volume produc-tion, spanning the range from high-end computers to low-end consumer products. It is princi-pally the portable and wireless consumer products that have fueled this third wave of applicationand integration of MCMs.
Through the pioneering efforts of the early visionary individuals and companies, and stimulatedby strong competition from off-shore suppliers, multichip modules are today moving into volumeproduction in the merchant market. As shown in Figure 4-66, the MCM market is forecast to growfrom about $1.3 billion in 1998 to near $2.9 billion in 2002, an average annual growth rate of 25percent (the figures exclude the value of ICs in MCMs).
IC Device and Packaging Technology Trends
INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-49
Courtesy of LSI Logic 22343
Figure 4-65. LSI Logic MCM-C
The generally accepted definition of an MCM is a collection of more than one bare die ormicropackage on a common substrate. Based on this definition, the evolving four families ofMCMs include:
• Hybrids: traditional thick-film substrates with typically small die and a low density ofinterconnects, using a custom hermetic can package. An example of a hybrid is shown inFigure 4-67.
• Chip-on-Board (COB): bare dice on organic laminate substrates, such as FR-4, along withother surface mount ICs, both packaged devices and discrete components. The package istypically a small daughter card, such as PC cards, smart cards, or small motherboard. Figure4-68 is an example of a video subsystem for a laptop computer; the large chip in the centeris an ASIC controller surrounded by various peripheral interface chips.
• Few-Chip Packages or Multi-Chip Packages (MCPs): a small module with an external formfactor that matches a single-chip package, and typically contains two to five bare dice. Thepackage can be a PQFP, PGA, or BGA. An example of an MCP is shown in Figure 4-69.
• High-End MCMs: includes large, high-density substrates with as many chips as used inmainframe computers and large military hybrids that have multiple high-density dice and acustom package. An example is shown in Figure 4-70.
Among these four families of MCMs, there is one common feature that drives their use: the single-chip package is eliminated. This one change allows for four potential gains over the conventionalapproach of single-chip packages on circuit boards:
• Smaller size• Less weight• Higher performance• Lower cost
The size reduction possible with an MCM implementation is graphically apparent when two iden-tical designs are compared; figure 4-71 shows a direct comparison between single-chip packageson a substrate and the same chip set in an MCM.
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INTEGRATED CIRCUIT ENGINEERING CORPORATION4-52
Source: Fujitsu 22057
Figure 4-69. Wireless Module in a Single Multichip Package (MCP)
Courtesy of Hughes Microelectronics 22562
Figure 4-70. High Performance Avionics Controller with 4 Thin Film MCMs Mounted on One Card
The performance of a system can be increased by an MCM implementation only if critical netsexist between chips. If the clock frequency is limited by propagation delays within the core of thechip, no amount of packaging innovations will increase the clock frequency. However, if wiringdelays influence the clock frequency, then the delays can be reduced by one-third to one-tenth,simply based on interconnect length reductions. This was the motivation of Intel to use an MCMfor the Pentium Pro, shown in Figure 4-72; the proximity of the L2 cache to the CPU helps thismodel of the Pentium Pro achieve a 200MHz clock frequency.
Another performance benefit that may be gained in an MCM approach over a conventionalapproach is the reduction in switching noise, which allows for higher bandwidths.
There has been a tendency of associating substrate choice with a type of MCM. The followingclassifications have been defined by the IPC:
• MCM-L: uses a laminate substrate such as FR-4• MCM-C: uses a cofired ceramic-based, multilayer substrate, either HTCC or LTCC, but not
thick film• MCM-D: uses a thin-film, multilayer, deposited substrate, with substrates of silicon, ceramic
or aluminum
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Source: nChip 15882
Figure 4-71. Comparison of Conventional and MCM RISC Microprocessor Chip Sets
• MCM-C/D: uses a multilayer cofired ceramic base with thin film built on top• MCM-L/D: uses a laminate base, with thin film built on top—sometimes referred to as
build-up multilayer (BUM) or build-up board (BUB) technology• Silicon-on-silicon: uses a silicon substrate and thin-film multilayer interconnects
Figures 4-73 and 4-74 compare the major substrate types. As can be seen, MCM-D provides thehighest interconnection density and performance, in addition to the lowest weight and size, butalso has the highest cost. Since cost is the governing factor effecting widespread use, MCM-Dshave thus far been used only in high-performance and specialized applications.
The MCM industry is combining substrate technologies to optimize technical solutions. In par-ticular, combinations of an MCM-C substrate containing ground and power connections with anMCM-D substrate providing the signal layers have proven viable. ICE expects this trend to con-tinue with the best features of each substrate style used as the application requires (Figure 4-75).
As shown in Figure 4-76, laminate-based MCMs accounted for the majority of MCMs sold in1997; the figure includes sales of MCM-C/Ds in the MCM-C category and MCM-L/Ds in theMCM-L category. By 2002, MCM-Ls will still make up 55 percent of the multichip modulemarket, but there will be significant movement to MCM-Ds as pricing becomes more competitivefor these parts.
MCM-C, MCM-C/D — still need hermeticpackaging, chip-and-wire assembly
MCM-C for implantable products,MCM-L for instruments
MCM-D and MCM-L/D for performance— flip chip will be dominant
MCM-D and MCM-L/D — siliconsubstrates heavily used
MCM-L — flip chip, well establishedfor MCM-C, will be used with MCM-L,some MCM-C under hood
MCM-L, strong user of TAB, willmigrate to flip chip
MCM-D with glass substrate, TAB and direct chip-on-glass with TAB forflip chip
Application Substrate Type
19476Source: Consultar
Figure 4-75. MCM Applications by Substrate Type
MCM-L63%
MCM-C9%
MCM-D28%
*Not including components.
1997 (EST)$950M MCM-L
55%
MCM-D40%
MCM-C5%
2002 (FCST)$2,900M
18526JSource: ICE
Figure 4-76. MCM Market Projections* ($)
Known Good Die Issues
The availability of known-good die (KGD) continues to improve, but is still the most significantbarrier in the bare-die-based MCM market. Even with the wide variation in the industry on whatconstitutes a KGD, there are increasing numbers of suppliers, both IC manufacturers and thirdparty distributors that are now offering KGD (Figure 4-77).
As specifications for KGD standardize and technologies to implement them move up the learningcurve, the price adders from KGD will converge. Currently, there is a wide variation among sup-pliers of KGD. National Semiconductor and Samsung offer some die at a lower price than the
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INTEGRATED CIRCUIT ENGINEERING CORPORATION 4-57
Advanced Micro Devices
Allegro MicroSystems
American Microsystems
Analog Devices
Calogic
Chip Express
Chip Supply
Cypress Semiconductor
Device Engineering
Elmo Semiconductor
Eltek Semiconductor
Harris Semiconductor
IBM Microelectronics
Integrated Device Technology
Intel
LSI Logic
Micron Technology
Minco Technology Labs
Motorola
National Semiconductor
Rood Testhouse
Semi Dice
SGS-Thomson
Texas Instruments
Vitesse Semiconductor
VLSI Technology
Company
Functionaland DC
ParametricTest
At-Speed andAt-Temperature
Test
Full KGDWith Burn-In
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Source: EP&P 22388A
Figure 4-77. Bare Die Suppliers
packaged units; here the range is 0.8 to 1.2 times. Intel offers KGD at parity to packaged die pricesin its SmartDie program. Most other suppliers, especially distributors, sell KGD at a 1.5 to 5 timespremium justified by the extra efforts associated with acquiring, specifying, testing, and, for somesuppliers, burn-in.
Key enablers to even faster proliferation of MCMs is decreasing the cost of KGD and increasingthe number of suppliers. One test solution for KGD provides an example of the complexityinvolved: Texas Instruments teamed with MicroModule Systems (MMS) developed a temporarypackage called DieMate that allows manufacturers to test bare dice with area pads used in flip-chip technology. MMS supplies the thin-film packages that are custom made for a given chiptype. The carrier (Figure 4-78) has contacts and an interconnect pattern laid on it so the chip forwhich it is made can be placed upside down with its bonding pads matching up to contacts in thecarrier. The chip is held to the carrier with pressure during burn-in and testing, and is thenreleased and removed, with an operator knowing whether the die is good or bad.
Other companies, including Chip Supply, IBM, Intel, Lucent Technologies, Micron, and Motorola,have developed methods of testing known good die as well. Intel claims that revenues from itsSmartDie program have been increasing at an average annual rate of 150 percent.
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Force DeliveryMechanism
Lid Die
Die EdgeRegistration
Feature
Carrier
Socket
Interconnect Compliant Material
Source: Semiconductor International/MMS 19228
Figure 4-78. Temporary Carrier for Die-Level Burn-In
