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CMPEN 411VLSI Digital Circuits

Spring 2009

Lecture 15:

Dynamic CMOS

[Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

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Power and Energy Design Space

Constant Throughput/Latency

Variable Throughput/Latency

Energy Design Time Non-active Modules Run Time

Active

(Dynamic)

Logic design

Reduced Vdd

TSizing

Multi-Vdd

Clock Gating

DFS, DVS

(Dynamic Freq, Voltage Scaling)

Leakage

(Standby)

Multi-VT

Stack effect

Pin ordering

Sleep Transistors

Multi-Vdd

Variable VT

Input control

Variable VT

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Industry Example: IBM Cu11 (0.13 um)

ASIC Cu11 (130nm) Library : Dual-vt library Nominal Vt level (~300mv) Low Vt level (~210mv)

Low-vt version has same physical footprint ~15% improvement in gate delay ~10x increase in leakage power

Dual-VDD (Voltage Island)

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How about Gate Leakage? multiple gate oxide (Sylvester et.al., DATE-2004)

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Dynamic CMOS

In _________ circuits at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path.

fan-in of N requires ______ devices

_________ circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.

requires only _________ transistors takes a sequence of ___________ and conditional

__________phases to realize logic functions

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Dynamic Gate

In1

In2 PDN

In3

Me

Mp

CLK

CLK

Out

CL

Out

CLK

CLK

A

BC

Mp

Me

Two phase operation ________ (CLK = 0) ________ (CLK = 1)

on

off

1

off

on

!((A&B)|C)

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Conditions on Output

Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation.

Inputs to the gate can make ________ transition(s) during evaluation.

Output state is stored on CL

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Properties of Dynamic Gates Logic function is implemented by the PDN only

number of transistors is _____(versus 2N for static complementary CMOS)

should be smaller in area than static complementary CMOS

Full swing outputs (VOL = GND and VOH = VDD)

Non-ratioed - sizing of the devices is not important for proper functioning (only for performance)

Faster switching speeds reduced load capacitance due to lower number of transistors per

gate (Cint) so a reduced logical effort reduced load capacitance due to smaller fan-out (Cext) no Isc, so all the current provided by PDN goes into discharging CL

Ignoring the influence of precharge time on the switching speed of the gate, tpLH = 0 but the presence of the evaluation transistor slows down the tpHL

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Properties of Dynamic Gates, con’t Power dissipation should be lower

no ______________power consumption since the pull-up path is not on when evaluating

lower ____________- both Cint (since there are fewer transistors connected to the drain output) and Cext (since there the output load is one per connected gate, not two)

by construction can have at most one transition per cycle – no _______________

But power dissipation can be significantly higher due to _______________________ extra load on ____________

Needs a precharge clock

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Dynamic Behavior

-0.5

0.5

1.5

2.5

0 0.5 1

CLK

CLK

In1

In2

In3

In4

Out

In &CLK

Out

Time, ns

Vol

tage

#Trns VOH VOL VM NMH NML tpHL tpLH tpre

6 2.5V 0V VTn 2.5-VTn VTn110ps 0ns 83ps

Evaluate

Precharge

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Power Consumption of Dynamic Gate

In1

In2 PDN

In3

Me

Mp

CLK

CLK

Out

CL

Power only dissipated when previous Out = 0

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Dynamic Power Consumption is Data Dependent

A B Out

0 0 1

0 1 0

1 0 0

1 1 0

Dynamic 2-input NOR Gate

Assume signal probabilities PA=1 = 1/2 PB=1 = 1/2

Then transition probability P01 = Pout=0 x Pout=1

= ___________

Switching activity can be higher in dynamic gates!P01 =__________

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Issues in Dynamic Design : Charge Leakage

CL

CLK

CLK

Out

A=0

Mp

Me

Minimum clock rate of a few kHz

Leakage

CLK

VOut

Precharge

Evaluate

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Impact of Charge Leakage Output settles to an intermediate voltage determined by

a resistive divider of the pull-up and pull-down networks Once the output drops below the switching threshold of the

fan-out logic gate, the output is interpreted as a low voltage.

-0.5

0.5

1.5

2.5

0 20 40

Time (ms)

Volta

ge (V

)

CLK

Out

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A Solution to Charge Leakage

CL

CLK

CLK

Me

Mp

A

B

!Out

Mkp

Same approach as level restorer for pass transistor logic

Keeper

Keeper compensates for the charge lost due to the pull-down leakage paths.

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Issues in Dynamic Design : Charge Sharing

CL

CLK

CLK

Ca

Cb

B=0

A

OutMp

Me

Charge stored originally on CL is redistributed (shared) over CL and CA leading to static power consumption by downstream gates and possible circuit malfunction.

When Vout = - VDD (Ca / (Ca + CL )) the drop in Vout is large enough to be below the switching threshold of the gate it drives causing a malfunction.

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Solution to Charge Redistribution

CLK

CLK

Me

Mp

A

B

OutMkp

CLK

Precharge internal nodes using a clock-driven transistor (at the cost of increased area and power)

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Issues in Dynamic Design : Cascading Gates

CLK

CLK

Out1

In

Mp

Me

Mp

Me

CLK

CLK

Out2

V

t

CLK

In

Out1

Out2V

VTn

Only a single 0 1 transition allowed at the inputs during the evaluation period!

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Domino Logic

In1

In2 PDN

In3

Me

Mp

CLK

CLKOut1

In4 PDN

In5

Me

Mp

CLK

CLKOut2

Mkp

1 11 0

0 00 1

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Why Domino?

In1

CLK

CLK

Ini PDNInj

Ini

Inj

PDN Ini PDNInj

Ini PDNInj

Like falling dominos!

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Domino Zero Detector

CLK

In7 In6 In5 In4 In3 In2 In0In1

not zero

How would you build it in static CMOS?

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Properties of Domino Logic

Only non-inverting logic can be implemented, fixes include

can reorganize the logic using Boolean transformations use differential logic (dual rail) use np-CMOS (zipper)

Very high speed tpHL = 0 static inverter can be optimized to match fan-out (separation of

fan-in and fan-out capacitances)

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Differential (Dual Rail) Domino

A

B

Me

Mp

CLK

CLK

!Out = !(AB)

!A !B

MkpCLK

Out = AB

Mkp Mp

Due to its high-performance, differential domino is very popular and is used in several commercial

microprocessors!

1 0 1 0

onoff

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Other Domino Variations

Multiple output domino logic – exploits the fact that certain outputs are subsets of other outputs to generate a number of logic functions in a single gate.

Compound domino

A

B

Me

Mp

CLK

CLK

C

D

E

MeCLK

F

MpCLK

G

Me

H

Mp

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np-CMOS (Zipper)

In1

In2 PDN

In3

Me

Mp

CLK

CLKOut1

In4 PUN

In5

Me

Mp!CLK

!CLK

Out2(to PDN)

1 11 0

0 00 1

Only 0 1 transitions allowed at inputs of PDN Only 1 0 transitions allowed at inputs of PUN

to otherPDN’s

to otherPUN’s

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DCVS Logic (Differential Cascade Voltage Switch

In1

In2

PDN1

Out

!In1

!In2

PDN2

!Out

PDN1 and PDN2 are mutually exclusive

1 0 0on off

off on on off

on off 1

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DCVSL Example

Out

!Out

B

A !A

B!B!B

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How to Choose a Logic Style

Must consider ease of design, robustness (noise immunity), area, speed, power, system clocking requirements, fan-out, functionality, ease of testing

Style # Trans Ease Ratioed? Delay Power

Comp Static 8 1 no 3 1

CPL* 12 + 2 2 no 4 3

domino 6 + 2 4 no 2 2 + clk

DCVSL* 10 3 yes 1 4

4-input NAND

* Dual Rail

Current trend is towards an increased use of complementary static CMOS: design support through DA tools, robust, more amenable to voltage scaling.

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Itanium 2 Domino Circuitry

Integer execution unit

Multimedia execution unit

2 Floating point units

Register Files

Out of order control issue logic

– Source: “Advanced Domino Circuit Design” , Intel, Tom Grutkowski, DATE 2004

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What is Soft Error

Soft errors are circuit errors caused due to excess charge carriers induced primarily by external radiations

These errors cause an upset event but the circuit it self is not damaged.

Same a SEU (single event upset)

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B

p substrate

G

n+n+

n channel

Soft Errors

The Phenomena

+ - + -+ -

+ -+-

+ -+ -

+ -+ -

A particle strikeCurrent

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Soft Errors The Phenomena

VDD

Vout

CL

Vin

A particle strike

Bit Flip !!!

A particle strike

!BL

BL

WL

0->11->0 0

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What cause Soft Errors?

At ground level, there are three major contributors to Soft errors.

1. Cosmic Ray induced neutrons

2. Alpha particles emitted by decaying radioactive impurities in packaging or interconnect materials.

3. Neutron induced 10B fission which releases a Alpha particle and 7Li

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Evidence of Cosmic Ray Strikes

Documented strikes in large servers found in error logs Normand, “Single Event Upset at Ground Level,” IEEE Transactions

on Nuclear Science, Vol. 43, No. 6, December 1996.

Sun Microsystems, 2000 Cosmic ray strikes on L2 cache with no error detection or correction

- caused Sun’s flagship servers to suddenly and mysteriously crash!

Companies affected

- Baby Bell (Atlanta), America Online, Ebay, & dozens of other corporations

- Verisign moved to IBM Unix servers (for the most part)

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Reactions from Companies

Fujitsu SPARC in 130 nm technology 80% of 200k latches protected with parity compare with very few latches protected in Mckinley ISSCC, 2003

IBM declared 1000 years system MTBF as product goal very hard to achieve this goal in a cost-effective way

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Space redundancy: Redundant Logic

Logic 1

Logic 2 Voter

Logic3Point of failure!!

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Next Lecture and Reminders Next lecture

Timing metrics, static sequential circuits - Reading assignment – Rabaey, et al, 7.1-7.2