Sp09 CMPEN 411 L21 S.1 CMPEN 411 VLSI Digital Circuits Spring 2009 Lecture 21: Shifters, Decoders, Muxes [Adapted from Rabaeys Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] Sp09 CMPEN 411 L21 S.2 Review: Basic Building Blocks Datapath l Execution units -Adder, multiplier, divider, shifter, etc. l Register file and pipeline registers l Multiplexers, decoders Control l Finite state machines (PLA, ROM, random logic) Interconnect l Switches, arbiters, buses Memory l Caches (SRAMs), TLBs, DRAMs, buffers Sp09 CMPEN 411 L21 S.3 Parallel Programmable Shifters Data In Control Data Out Shifters used in multipliers, floating point units Consume lots of area if done in random logic gates Shift amount (Sh 2 Sh 1 Sh 0 ) Shift direction (left, right) Shift type (logical, arithmetic, circular) = Sp09 CMPEN 411 L21 S.4 A Programmable Binary Shifter rgtnopleft AiAi A i-1 B i-1 BiBi AiAi A i-1 rgtnopleftBiBi B i-1 A1A1 A0A0 010A1A1 A0A0 A1A1 A0A0 1000A1A1 A1A1 A0A0 001A0A0 0 0 Sp09 CMPEN 411 L21 S.5 A Programmable Binary Shifter rgtnopleft AiAi A i-1 B i-1 BiBi AiAi A i-1 rgtnopleftBiBi B i-1 A1A1 A0A0 010A1A1 A0A0 A1A1 A0A0 1000A1A1 A1A1 A0A0 001A0A0 0 0 Sp09 CMPEN 411 L21 S.6 4-bit Barrel Shifter A0A0 A1A1 A2A2 A3A3 B0B0 B1B1 B2B2 B3B3 Area dominated by wiring Example: !Sh 1 !Sh 0 = 1 B 3 B 2 B 1 B 0 = A 3 A 2 A 1 A 0 !Sh 1 Sh 0 = 1 B 3 B 2 B 1 B 0 = A 3 A 3 A 2 A 1 Sh 1 !Sh 0 = 1 B 3 B 2 B 1 B 0 = A 3 A 3 A 3 A 2 Sh 1 Sh 0 = 1 B 3 B 2 B 1 B 0 = A 3 A 3 A 3 A 3 Sh 1 !Sh 0 !Sh 1 Sh 0 !Sh 1 !Sh 0 Sh 1 Sh 0 Sh 1 !Sh 0 !Sh 1 Sh 0 Sp09 CMPEN 411 L21 S.7 4-bit Barrel Shifter Layout Width barrel ~ O(N) Delay ~ 1 fet + N diff caps Width barrel Only one Sh# active at a time l Sh 1 Sh 0 Sh 1 !Sh 0 !Sh 1 Sh 0 !Sh 1 !Sh 0 Sp09 CMPEN 411 L21 S.8 Logarithmic Shifter Structure xxx Data In Data Out shifts of 0 or 1 bits !Sh 0 Sh 0 0,1 shifts shifts of 0 or 2 bits !Sh 1 Sh 1 0,1,2,3 shifts shifts of 0 or 4 bits !Sh 2 Sh 2 0,1,2,3,4, 5,6,7 shifts shifts of 0 or 8 bits !Sh 3 Sh 3 0,1,215 shifts shifts of 0 or 16 bits !Sh 4 Sh 4 0,1,231 shifts Sp09 CMPEN 411 L21 S.9 8-bit Logarithmic Shifter A3A3 A2A2 A1A1 A0A0 !Sh 0 Sh 0 !Sh 1 Sh 1 !Sh 2 Sh 2 B0B0 B1B1 B2B2 B3B log N stages Sp09 CMPEN 411 L21 S.10 8-bit Logarithmic Shifter Layout Slice K = log 2 N Delay ~ K fets + 2 diff caps A0A0 B3B3 B2B2 B1B1 B0B0 A1A1 A2A2 A3A3 124 Sp09 CMPEN 411 L21 S.11 Shifter Implementation Comparisons NK BarrelLogarithmic WidthSpeedWidthSpeed 2 N p m 1 + N diffsp m (2 K +2K-1)K + 2 diffs 8316 p m p m p m p m p m p m p m p m Barrel shifter needs an K x 2 K shift amount decoder Sp09 CMPEN 411 L21 S.12 Decoders Decodes inputs to activate one of many outputs l In random gate logic need two inverters, four 2-input nand gates, four inverters plus enable logic l how about for a 3-to-8, 4-to-16, etc. decoder? In 0 In 1 Enable Out 0 = !In 1 & !In 0 Out 1 = !In 1 & In 0 Out 2 = In 1 & !In 0 Out 3 = In 1 & In 0 2x4 Sp09 CMPEN 411 L21 S.13 Dynamic NOR Row Decoder V DD !A 0 A0A0 !A 1 A1A1 Out 3 Out 2 Out 1 Out 0 precharge 0 0 1 on on GND Sp09 CMPEN 411 L21 S.14 Dynamic NAND Row Decoder !A 0 A0A0 !A 1 A1A1 Out 0 precharge Out 1 Out 2 Out 1 0 on Sp09 CMPEN 411 L21 S.15 Building Big Decoders from Small 1x2 A4A4 enable A3A3 A2A2 2x4 A1A1 A0A 0 1 Active low enable Active low output Sp09 CMPEN 411 L21 S.16 Multiplexers Selects one of several inputs to gate to the single output l In random gate logic need two inverters, four 3-input nands, one 4-input nand l how about for an 8x1, 16x1, etc. mux? In 0 S 1 S 0 Out = In 0 & !S 1 & !S 0 | In 1 & !S 1 & S 0 | In 2 & S 1 & !S 0 | In 3 & S 1 & S 0 In 1 In 2 In 3 4x1 Sp09 CMPEN 411 L21 S.17 Review: TG 2x1 Multiplexer GND V DD In 1 In 2 SS SS S S !S In 2 In 1 F F F = !((In 1 & S) | (In 2 & !S)) Sp09 CMPEN 411 L21 S.18 Building Big Muxes from Small A0A0 S0S0 A1A1 2x1 A2A2 A3A3 S1S1 Out 10 Sp09 CMPEN 411 L21 S.19 Memory Definitions Size Kbytes, Mbytes, Gbytes, Tbytes Speed l Read Access delay between read request and the data available l Write Access delay between write request and the writing of the data into the memory l (Read or Write) Cycle - minimum time required between successive reads or writes Read Write Data Read Cycle Read Access Write Cycle Data Valid Write Setup Write Access Data Written Sp09 CMPEN 411 L21 S.20 Second Level Cache (SRAM) A Typical Memory Hierarchy Control Datapath Secondary Memory (Disk) On-Chip Components RegFile Main Memory (DRAM) Data Cache Instr Cache ITLB DTLB eDRAM Speed (ns):.1s 1s 10s 100s 1,000s Size (bytes): 100s Ks 10Ks Ms Ts Cost: highest lowest By taking advantage of the principle of locality, we can l present the user with as much memory as is available in the cheapest technology l at the speed offered by the fastest technology. Sp09 CMPEN 411 L21 S.21 Random Access Read Write Memories SRAM Static Random Access Memory l data is stored as long as supply is applied l large cells (6 fets/cell) so fewer bits/chip l fast so used where speed is important (e.g., caches) l differential outputs (output BL and !BL) l use sense amps for performance l compatible with CMOS technology DRAM - Dynamic Random Access Memory l periodic refresh required (every 1 to 4 ms) to compensate for the charge loss caused by leakage l small cells (1 to 3 fets/cell) so more bits/chip l slower so used for main memories l single ended output (output BL only) l need sense amps for correct operation l not typically compatible with CMOS technology Sp09 CMPEN 411 L21 S.22 Next Lecture and Reminders Next lecture l SRAM, DRAM, and CAM cores -Reading assignment Rabaey, et al,