CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07...

CMPEN 411VLSI Digital Circuits

Spring 2011Lecture 07: Pass Transistor Logic

Sp11 CMPEN 411 L07 S.1

[Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

Heads up

� This lecture

� Pass transistor logic

- Reading assignment – Rabaey, et al, 6.2.3


� Next lecture

� MOS transistor dynamic behavior

- Reading assignment – Rabaey, et al, 3.2.3 & 3.3.3-3.3.5

� Wiring capacitance

- Reading assignment – Rabaey, et al, 4.1-4.3.1

Review: Static Complementary CMOS

VDD

F(In1,In2,:InN)

In1

In2

InN

PUN

� High noise margins

� VOH and VOL are at VDD and GND, respectively

� Low output impedance, high input impedance

� No static power consumption

� Never a direct path between


F(In1,In2,:InN)

In1

In2

InN

PDN

PUN and PDN are dual logic networks

� Never a direct path between VDD and GND in steady state

� Delay a function of load capacitance and transistor on resistance

� Comparable rise and fall times (under the appropriate relative transistor sizing conditions)

Review: Static Complementary CMOS

VDD

F(In1,In2,:InN)

In1

In2

InN

PUN

� Question:

Why PUN use only PMOS and PDN use only NMOS?

ANSWER:


F(In1,In2,:InN)

In1

In2

InN

PDN

PUN and PDN are dual logic networks

ANSWER:

NMOS transistors pass a

______ 0 but a _____ 1

PMOS transistors pass a

______ 1 but a ______ 0

NMOS Transistors in Series/Parallel

� Primary inputs drive both gate and source/drain terminals

� NMOS switch closes when the gate input is ______

A B

X YX = Y if ______


� Remember - NMOS transistors pass a ______ 0 but a ______1

X Y

X Y

A

B X = Y if _______

PMOS Transistors in Series/Parallel

� Primary inputs drive both gate and source/drain terminals

� PMOS switch closes when the gate input is low

A B

X YX = Y if _______________


� Remember - PMOS transistors pass a ______ 1 but a _____0

X Y

X Y

A

B X = Y if ____________

Pass Transistor (PT) Logic

A

B

FB

0

A

0

B

B= _____

F = _____


� Gate is ______– a path exists to both supply rails under

all circumstances

� ____ transistors instead of 2N (for CMOS)

� No static power consumption

� Ratioless

� Bidirectional (versus undirectional)

VTC of PT AND Gate

A

B

B0.5/0.25

0.5/0.25

1.5/0.25

1

2

B=VDD, A=0→VDD

A=V , B=0→V

Vout,

V


0

BF= A•B

0.5/0.250

0 1 2

A=VDD, B=0→VDD

A=B=0→VDD

� Pure PT logic is not regenerative - the signal

gradually degrades after passing through a number

of PTs (can fix with static CMOS inverter insertion)

Differential PT Logic (DPL/CPL)

A

B

AB

PT NetworkF

A

B

AB

Inverse PT

Network F

F

F


F=AB

A

A

B F=AB

B

B B

AND/NAND

A

A

B F=A+B

BF=A+B

BB

OR/NOR

A

A F=A⊕B

F=A⊕B

BB

XOR/XNOR

A

A

Why NFET?

CPL Properties

� Differential so complementary data inputs and outputs are always available (so don’t need extra inverters)

� Still static, since the output defining nodes are always tied to VDD or GND through a low resistance path

� Design is _________; all gates use the same topology, only the inputs are permuted.

Sp11 CMPEN 411 L07 S.10

only the inputs are permuted.

� Simple XOR makes it attractive for structures like ______

� Fast (assuming number of transistors in series is small)

� Additional routing overhead for complementary signals

CPL Full Adder

A

A

BB CinCin

!Sum

Sum

Sp11 CMPEN 411 L07 S.11

Cout

!CoutA

A

B

B

B

B Cin Cin

Cin

Cin

CPL Full Adder

A

A

BB CinCin

!Sum

Sum

Sp11 CMPEN 411 L07 S.12

Cout

!CoutA

A

B

B

B

B Cin Cin

Cin

Cin

NMOS Only PT Driving an Inverter

In = VDD

A = VDD

Vx = ___

M1

M2

B

SD

VGS

Sp11 CMPEN 411 L07 S.13

� Vx does not pull up to VDD, but _________

� Threshold voltage drop causes static power consumption (M2 may be weakly conducting forming a path from VDD to GND)

� Notice VTn increases for pass transistor due to body effect (VSB)

Voltage Swing of PT Driving an Inverter

In = 0 → VDD

VDD

xOut

0.5/0.25

0.5/0.25

1.5/0.25

1

2

3

Vo

lta

ge

, V

In

Out

x = 1.8VD

S

B

Sp11 CMPEN 411 L07 S.14

� Body effect – large VSB at x - when pulling high (B is tied to GND and S charged up close to VDD)

� So the voltage drop is even worse

Vx = VDD - (VTn0 + γ(√(|2φf| + Vx) - √|2φf|))

0

0 0.5 1 1.5 2

Time, ns

Out

Cascaded NMOS Only PTs

B = VDD

Out

M1

yM2

xM1

B = VDD

OutyM2

C = VDD

A = VDD

C = VDD

A = VDDx = VDD - VTn1

G

S

G

S

Sp11 CMPEN 411 L07 S.15

Swing on y = VDD - VTn1 - VTn2 Swing on y = VDD - VTn1

� Pass transistor gates should never be cascaded as on

the left

� Logic on the right suffers from static power dissipation

and reduced noise margins

Solution 1: Level Restorer

Level Restorer

M1

M2

A=0 Mn

Mr

x

B

Out =1

off

= 0A=1 Out=0

on

1

Sp11 CMPEN 411 L07 S.16

� For correct operation Mr must be sized correctly (ratioed)

� Full swing on x (due to Level Restorer) so no static power consumption by inverter

� No static backward current path through Level Restorer and PT since Restorer is only active when A is high

Transient Level Restorer Circuit Response

1

2

3V

olta

ge

, V

W/Lr=1.75/0.25

W/Lr=1.50/0.25

W/Ln=0.50/0.25

W/L2=1.50/0.25

W/L1=0.50/0.25

node x never goes below VM

of inverter so output never

switches

Sp11 CMPEN 411 L07 S.17

0

1

0 100 200 300 400 500

Vo

lta

ge

, V

Time, ps

W/Lr=1.25/0.25W/Lr=1.0/0.25

� Restorer has speed and power impacts: increases the capacitance at x, slowing down the gate; increases tr (but decreases tf)

Solution 2: Multiple VT Transistors

� Technology solution: Use (near) zero VT devices for the NMOS PTs to eliminate most of the threshold drop (body effect still in force preventing full swing to VDD)

In2 = 0V A= 2.5V

low VT transistors

on

Sp11 CMPEN 411 L07 S.18

� Impacts static power consumption due to subthreshold currents flowing through the PTs (even if VGS is below VT)

Out

In1 = 2.5V B = 0V

sneak path

off but

leaking

Solution 3: Transmission Gates (TGs)

A B

C

C

A B

C

C� Most widely used

solution

Sp11 CMPEN 411 L07 S.19

� Full swing bidirectional switch controlled by the gate signal C, A = B if C = 1

B

C = VDD

C = GND

A = VDD B

C = VDD

C = GND

A = GND

Solution 3: Transmission Gates (TGs)

A B

C

C

A B

C

C

C = GND C = GND

� Most widely used solution

Sp11 CMPEN 411 L07 S.20

� Full swing bidirectional switch controlled by the gate signal C, A = B if C = 1, minimum size (ratioless)

B

C = VDD

C = GND

A = VDD B

C = VDD

C = GND

A = GND

TG Multiplexer

VDD

S S

S

S

In2

F

F

Sp11 CMPEN 411 L07 S.21

GND

In1 In2S S

S

In1

F = !(In1 • S + In2 • S)

Transmission Gate XOR

A A ⊕ B

Sp11 CMPEN 411 L07 S.22

B

A A ⊕ B

How many FETs for CMOS implementation? 10-12

Transmission Gate XOR

A A ⊕ B

offon A • !B

Sp11 CMPEN 411 L07 S.23

B

A A ⊕ B

1

off

an inverter

B • !A

0

on

TG Full Adder

B

Cin

Sp11 CMPEN 411 L07 S.24

Sum

Cout

A

How many transistors?

Differential TG Logic (DPL)

A

A

B

B

B F=A⊕B

A B A

F=AB

A

B

B A B A

GND

GND

Sp11 CMPEN 411 L07 S.25

B

AND/NAND

F=A⊕B

XOR/XNOR

A

B

A

B

F=ABA

GND

VDD

VDD

B

6-transistor SRAM Storage Cell

WL

M1

M2

M3

M4

M5

M6Q

!Q

Sp11 CMPEN 411 L07 S.26

!BL BL

M1 M3

� Will cover how the cell works in detail later

MOS OR ROM Cell Array

WL(0)

WL(1)

VDD

BL(0) BL(1) BL(2) BL(3)

0 0 0 0

0

0 → 1 on on

1 0 0 1

Sp11 CMPEN 411 L07 S.27

predischarge

WL(2)

WL(3)

VDD

1 → 0

0

0

Next Lecture and Reminders

� Next lecture

� MOS transistor dynamic behavior

- Reading assignment – Rabaey, et al, 3.2.3 & 3.3.3-3.3.5

� Wiring capacitance

- Reading assignment – Rabaey, et al, 4.1-4.3.1

Sp11 CMPEN 411 L07 S.28

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CMPEN 411 VLSI Digital Circuits Spring 2011 Lecture 07...

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